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White Rabbit Switch - Gateware
Commit 9a3f56b5 authored by Maciej Lipinski's avatar Maciej Lipinski
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Importing altera to the new repo: adding altera files from the old repo to the new repo

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platform/altera/.gitignore 0 → 100644
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# /
/*.mpf
/*.bak
/*.state
/*.wlf
/*.summary
/*.rpt
/*.done
/*.pin
/*.sof
/*.smsg
/*.dpf
/*.rbf
/incremental_db
/*.ddb
/PLLJ_PLLSPE_INFO.txt
platform/altera/Makefile 0 → 100644
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SRCS_VHDL = platform_specific.vhd \
alt_clock_divider.vhd \
../genrams/genram_pkg.vhd \
../genrams/altera/generic_dpram.vhd \
../genrams/altera/generic_spram.vhd \
../genrams/altera/generic_sync_fifo.vhd \
../genrams/altera/generic_async_fifo.vhd \
../generic_ssram_dualport_singleclock.vhd
VPATH=../genrams/altera ../genrams
WORK = work
include ../../scripts/modules.mk
platform/altera/Manifest.py 0 → 100644
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files= ["platform_specific.vhd",
"alt_clock_divider.vhd"];
platform/altera/alt_clock_divider.vhd 0 → 100644
View file @ 9a3f56b5
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clock_divider.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY alt_clock_divider IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END alt_clock_divider;
ARCHITECTURE SYN OF alt_clock_divider IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
locked <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=clock_divider",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c1"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "62.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock_divider.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
platform/altera/generic_clock_mux3.vhd 0 → 100644
View file @ 9a3f56b5
-------------------------------------------------------------------------------
-- Title : Generic platform-independent 4-input clock mux
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : generic_clock_mux.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-06-21
-- Last update: 2010-06-21
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: 4 input clock multiplexer - a wrapper for ALTCLKCTRL component.
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-21 1.0 twlostow Created
-------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
--synthesis_resources = clkctrl 1 reg 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clkmux2_altera_altclkctrl_0fi IS
PORT
(
clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
ena : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
outclk : OUT STD_LOGIC
);
END clkmux2_altera_altclkctrl_0fi;
ARCHITECTURE RTL OF clkmux2_altera_altclkctrl_0fi IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
SIGNAL ena_reg : STD_LOGIC
-- synopsys translate_off
:= '1'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF ena_reg : SIGNAL IS "POWER_UP_LEVEL=HIGH";
SIGNAL wire_ena_reg_w_lg_q6w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL select_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF select_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_select_reg_w_q_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_select_reg_w_q_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_clkctrl1_w_lg_outclk5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_clkctrl1_clkselect : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_clkctrl1_outclk : STD_LOGIC;
SIGNAL wire_w_lg_w_select_enable_wire_range15w20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_clkselect_wire_range13w14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_clkselect_wire_range18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL clkselect_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL inclk_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL select_enable_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_clkselect_wire_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_clkselect_wire_range3w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_clkselect_wire_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_select_enable_wire_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT cycloneiii_clkctrl
GENERIC
(
clock_type : STRING;
ena_register_mode : STRING := "falling edge";
lpm_type : STRING := "cycloneiii_clkctrl"
);
PORT
(
clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ena : IN STD_LOGIC;
inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
wire_vcc <= '1';
wire_w_lg_w_select_enable_wire_range15w20w(0) <= wire_w_select_enable_wire_range15w(0) OR wire_w_lg_w_clkselect_wire_range18w19w(0);
wire_w_lg_w_clkselect_wire_range13w14w(0) <= wire_w_clkselect_wire_range13w(0) XOR wire_select_reg_w_q_range12w(0);
wire_w_lg_w_clkselect_wire_range18w19w(0) <= wire_w_clkselect_wire_range18w(0) XOR wire_select_reg_w_q_range17w(0);
clkselect_wire <= ( clkselect);
inclk_wire <= ( inclk);
outclk <= (wire_clkctrl1_outclk AND ena_reg);
select_enable_wire <= ( wire_w_lg_w_select_enable_wire_range15w20w & wire_w_lg_w_clkselect_wire_range13w14w);
wire_w_clkselect_wire_range13w(0) <= clkselect_wire(0);
wire_w_clkselect_wire_range3w <= clkselect_wire(1 DOWNTO 0);
wire_w_clkselect_wire_range18w(0) <= clkselect_wire(1);
wire_w_select_enable_wire_range15w(0) <= select_enable_wire(0);
PROCESS (wire_clkctrl1_outclk)
BEGIN
IF (wire_clkctrl1_outclk = '0' AND wire_clkctrl1_outclk'event) THEN ena_reg <= (ena AND (NOT select_enable_wire(1)));
END IF;
END PROCESS;
PROCESS (wire_clkctrl1_outclk)
BEGIN
IF (wire_clkctrl1_outclk = '0' AND wire_clkctrl1_outclk'event) THEN
IF (ena_reg = '0') THEN select_reg <= wire_w_clkselect_wire_range3w;
END IF;
END IF;
END PROCESS;
wire_select_reg_w_q_range12w(0) <= select_reg(0);
wire_select_reg_w_q_range17w(0) <= select_reg(1);
wire_clkctrl1_w_lg_outclk5w(0) <= NOT wire_clkctrl1_outclk;
wire_clkctrl1_clkselect <= ( select_reg);
clkctrl1 : cycloneiii_clkctrl
GENERIC MAP (
clock_type => "Global Clock"
)
PORT MAP (
clkselect => wire_clkctrl1_clkselect,
ena => wire_vcc,
inclk => inclk_wire,
outclk => wire_clkctrl1_outclk
);
END RTL; --clkmux2_altera_altclkctrl_0fi
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clkmux2_altera IS
PORT
(
clkselect : IN STD_LOGIC := '0';
inclk0x : IN STD_LOGIC ;
inclk1x : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
END clkmux2_altera;
ARCHITECTURE RTL OF clkmux2_altera IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "altclkctrl";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "ena_register_mode=falling edge;intended_device_family=Cyclone III;use_glitch_free_switch_over_implementation=ON;clock_type=Global Clock;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5_bv : BIT_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT clkmux2_altera_altclkctrl_0fi
PORT (
ena : IN STD_LOGIC ;
outclk : OUT STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= '1';
sub_wire5_bv(1 DOWNTO 0) <= "00";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= inclk1x;
outclk <= sub_wire0;
sub_wire2 <= inclk0x;
sub_wire3 <= sub_wire5(1 DOWNTO 0) & sub_wire4 & sub_wire2;
sub_wire6 <= clkselect;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
clkmux2_altera_altclkctrl_0fi_component : clkmux2_altera_altclkctrl_0fi
PORT MAP (
ena => sub_wire1,
inclk => sub_wire3,
clkselect => sub_wire7,
outclk => sub_wire0
);
END RTL;
library cycloneiii;
use cycloneiii.all;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.platform_specific.all;
entity generic_clock_mux3 is
port (
-- clock select
clk_sel_i : in std_logic_vector(1 downto 0);
-- clock inputs
inclk0_i : in std_logic;
inclk1_i : in std_logic;
inclk2_i : in std_logic;
-- clock MUX output
outclk_o : out std_logic
);
end generic_clock_mux3;
architecture rtl of generic_clock_mux3 is
component clkmux2_altera
port (
clkselect : IN STD_LOGIC := '0';
inclk0x : IN STD_LOGIC;
inclk1x : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component;
signal clk_01_muxed : std_logic;
begin
mux01: clkmux2_altera
port map (
clkselect => clk_sel_i(1),
inclk0x => inclk0_i,
inclk1x => inclk1_i,
outclk => outclk_o);
end rtl;
platform/altera/generic_pipelined_multiplier.vhd 0 → 100644
View file @ 9a3f56b5
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.all;
library work;
use work.platform_specific.all;
entity generic_pipelined_multiplier is
generic(
g_width_a : natural;
g_width_b : natural;
g_width_out : natural;
g_sign_mode : string := "signed"
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(g_width_a -1 downto 0);
b_i : in std_logic_vector(g_width_b -1 downto 0);
q_o : out std_logic_vector(g_width_out-1 downto 0)
);
end generic_pipelined_multiplier;
architecture SYN of generic_pipelined_multiplier is
signal sub_wire0 : std_logic_vector (g_width_out-1 downto 0);
component lpm_mult
generic (
lpm_hint : string;
lpm_pipeline : natural;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
dataa : in std_logic_vector (g_width_a-1 downto 0);
datab : in std_logic_vector (g_width_b-1 downto 0);
clock : in std_logic;
result : out std_logic_vector (g_width_out-1 downto 0)
);
end component;
begin
q_o <= sub_wire0(g_width_out-1 downto 0);
lpm_mult_component : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => g_width_a,
lpm_widthb => g_width_b,
lpm_widthp => g_width_out
)
port map (
dataa => a_i,
datab => b_i,
clock => clk_i,
result => sub_wire0
);
end SYN;
platform/altera/generic_ssram_dualport_singleclock.vhd 0 → 100644
View file @ 9a3f56b5
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: aaa.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_ssram_dualport_singleclock is
generic (
g_width : natural := 8;
g_addr_bits : natural := 10;
g_size : natural := 1024;
g_init_file : string := "UNUSED");
port
(
data_i : in std_logic_vector (g_width-1 downto 0);
clk_i : in std_logic;
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0)
);
end generic_ssram_dualport_singleclock;
architecture SYN of generic_ssram_dualport_singleclock is
signal sub_wire0 : std_logic_vector (g_width-1 downto 0);
component altsyncram
generic (
address_aclr_b : string;
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
read_during_write_mode_mixed_ports : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
INIT_FILE : string ;
width_byteena_a : natural
);
port (
wren_a : in std_logic;
clock0 : in std_logic;
address_a : in std_logic_vector (g_addr_bits-1 downto 0);
address_b : in std_logic_vector (g_addr_bits-1 downto 0);
q_b : out std_logic_vector (g_width-1 downto 0);
data_a : in std_logic_vector (g_width-1 downto 0)
);
end component;
begin
q_o <= sub_wire0(g_width-1 downto 0);
altsyncram_component : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => g_addr_bits,
widthad_b => g_addr_bits,
width_a => g_width,
width_b => g_width,
width_byteena_a => 1,
INIT_FILE => g_init_file
)
port map (
wren_a => wr_en_i,
clock0 => clk_i,
address_a => wr_addr_i,
address_b => rd_addr_i,
data_a => data_i,
q_b => sub_wire0
);
end SYN;
platform/altera/platform_specific.vhd 0 → 100644
View file @ 9a3f56b5
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lpm;
use lpm.all;
-------------------------------------------------------------------------------
package platform_specific is
component alt_clock_divider
port (
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
locked : out std_logic);
end component;
component generic_pipelined_multiplier
generic (
g_width_a : natural;
g_width_b : natural;
g_width_out : natural;
g_sign_mode : string);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(g_width_a -1 downto 0);
b_i : in std_logic_vector(g_width_b -1 downto 0);
q_o : out std_logic_vector(g_width_out-1 downto 0));
end component;
end platform_specific;
-------------------------------------------------------------------------------
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