Commit 9cbde414 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

move wrsw_txtsu to wr-cores repository

parent 2973034b
modules = { "local" : [
"modules/wrsw_rt_subsystem",
"modules/wrsw_txtsu",
"modules/wrsw_swcore",
"modules/wrsw_rtu",
"modules/wrsw_tru",
......
Subproject commit 5b002c352f1b565ac8e39b1a8a53dd1f371243aa
Subproject commit 6ea37961319d1d590005ff06d30323207a95430f
files = ["xwrsw_txtsu.vhd",
"wrsw_txtsu_wb.vhd",
"wrsw_txtsu_pkg.vhd"]
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wrsw_txtsu_wb";
-- TXTSU shared FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf";
name = "Timestamp FIFO";
description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
- VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
- VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames;\
- INCORRECT - timestamp may be incorrect, it has been generated during timebase adjustment";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Rising edge timestamp";
descritpion = "Timestamp value taken on rising clock edge (full word)";
prefix = "val_r";
type = SLV;
size = 28;
};
field {
name = "Falling edge timestamp";
description = "Timestamp value taken on falling clock edge (few LSBs)";
prefix = "val_f";
type = SLV;
size = 4;
};
field {
name ="Physical port ID";
description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
prefix = "pid";
type = SLV;
size = 5;
align= 16;
};
field {
name = "Frame ID";
description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
prefix = "fid";
type = SLV;
size = 16;
align = 16;
};
field {
name = "Timestamp (possibly) incorrect";
description = "1: This timestamp may be incorrect (generated during PPS adjustment)\
0: Timestamp is correct.";
prefix = "incorrect";
type = BIT;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_1;
};
};
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
package wrsw_txtsu_pkg is
-- t_txtsu_timestamp was here, but now it's moved to wr_endpoint_pkg.
end wrsw_txtsu_pkg;
This diff is collapsed.
-------------------------------------------------------------------------------
-- Title : TX Timestamping Unit
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : xwrsw_txtsu.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-07-31
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Shared timestamping unit for all switch endpoints. It collects
-- TX timestamps with associated frame identifiers and puts them (along
-- with the identifier of requesting port) in a shared FIFO. Each FIFO entry
-- contains:
-- - Frame ID value (from OOB field of transmitted frame)
-- - Timestamp value (from the endpoint)
-- - Port ID value (ID of the TXTSU port to which the timstamp+frame id came).
-- FIFO is accessible from the Wishbone bus. An IRQ (level-active) is triggered
-- when the FIFO is not empty. The driver reads TX timestamps (with associated
-- port and frame identifiers) and passes them to PTP daemon.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 - 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-04-26 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
entity xwrsw_tx_tsu is
generic (
g_num_ports : integer := 10;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
-- reference clock / 2 (62.5 MHz). All signals below are synchronous to this clock
clk_sys_i : in std_logic;
-- sync reset, active LO
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- TX timestamp interface (from endpoints)
-------------------------------------------------------------------------------
-- frame identifier inputs (separate for each port)
timestamps_i : in t_txtsu_timestamp_array(g_num_ports-1 downto 0);
timestamps_ack_o : out std_logic_vector(g_num_ports -1 downto 0);
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
int_o : out std_logic
);
end xwrsw_tx_tsu;
architecture syn of xwrsw_tx_tsu is
component wrsw_txtsu_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
txtsu_tsf_wr_req_i : in std_logic;
txtsu_tsf_wr_full_o : out std_logic;
txtsu_tsf_wr_empty_o : out std_logic;
txtsu_tsf_val_r_i : in std_logic_vector(27 downto 0);
txtsu_tsf_val_f_i : in std_logic_vector(3 downto 0);
txtsu_tsf_pid_i : in std_logic_vector(4 downto 0);
txtsu_tsf_fid_i : in std_logic_vector(15 downto 0);
txtsu_tsf_incorrect_i : in std_logic;
irq_nempty_i : in std_logic);
end component;
signal txtsu_tsf_wr_req : std_logic;
signal txtsu_tsf_wr_full : std_logic;
signal txtsu_tsf_wr_empty : std_logic;
signal txtsu_tsf_val_r : std_logic_vector(27 downto 0);
signal txtsu_tsf_val_f : std_logic_vector(3 downto 0);
signal txtsu_tsf_pid : std_logic_vector(4 downto 0);
signal txtsu_tsf_fid : std_logic_vector(15 downto 0);
signal txtsu_tsf_incorrect : std_logic;
signal irq_nempty : std_logic;
signal scan_cntr : unsigned(4 downto 0);
type t_txtsu_state is (TSU_SCAN, TSU_ACK);
signal state : t_txtsu_state;
signal cur_ep : integer;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin -- syn
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
slave_i => wb_i,
slave_o => wb_o);
cur_ep <= to_integer(scan_cntr);
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= TSU_SCAN;
scan_cntr <= (others => '0');
txtsu_tsf_wr_req <= '0';
timestamps_ack_o <= (others => '0');
else
case state is
when TSU_SCAN =>
if(timestamps_i(cur_ep).stb = '1') then
timestamps_ack_o(cur_ep) <= '1';
state <= TSU_ACK;
if(txtsu_tsf_wr_full = '0') then
txtsu_tsf_pid <= timestamps_i(cur_ep).port_id(4 downto 0);
txtsu_tsf_fid <= timestamps_i(cur_ep).frame_id;
txtsu_tsf_val_f <= timestamps_i(cur_ep).tsval(31 downto 28);
txtsu_tsf_val_r <= timestamps_i(cur_ep).tsval(27 downto 0);
txtsu_tsf_incorrect <= timestamps_i(cur_ep).incorrect;
txtsu_tsf_wr_req <= '1';
end if;
else
if(scan_cntr = g_num_ports-1)then
scan_cntr <= (others => '0');
else
scan_cntr <= scan_cntr + 1;
end if;
end if;
when TSU_ACK =>
timestamps_ack_o(cur_ep) <= '0';
txtsu_tsf_wr_req <= '0';
state <= TSU_SCAN;
if(scan_cntr = g_num_ports-1)then
scan_cntr <= (others => '0');
else
scan_cntr <= scan_cntr + 1;
end if;
when others => null;
end case;
end if;
end if;
end process;
U_WB_SLAVE : wrsw_txtsu_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_int_o => int_o,
txtsu_tsf_wr_req_i => txtsu_tsf_wr_req,
txtsu_tsf_wr_full_o => txtsu_tsf_wr_full,
txtsu_tsf_wr_empty_o => txtsu_tsf_wr_empty,
txtsu_tsf_val_r_i => txtsu_tsf_val_r,
txtsu_tsf_val_f_i => txtsu_tsf_val_f,
txtsu_tsf_pid_i => txtsu_tsf_pid,
txtsu_tsf_fid_i => txtsu_tsf_fid,
txtsu_tsf_incorrect_i => txtsu_tsf_incorrect,
irq_nempty_i => irq_nempty);
irq_nempty <= not txtsu_tsf_wr_empty;
end syn;
`define ADDR_TXTSU_EIC_IDR 5'h0
`define TXTSU_EIC_IDR_NEMPTY_OFFSET 0
`define TXTSU_EIC_IDR_NEMPTY 32'h00000001
`define ADDR_TXTSU_EIC_IER 5'h4
`define TXTSU_EIC_IER_NEMPTY_OFFSET 0
`define TXTSU_EIC_IER_NEMPTY 32'h00000001
`define ADDR_TXTSU_EIC_IMR 5'h8
`define TXTSU_EIC_IMR_NEMPTY_OFFSET 0
`define TXTSU_EIC_IMR_NEMPTY 32'h00000001
`define ADDR_TXTSU_EIC_ISR 5'hc
`define TXTSU_EIC_ISR_NEMPTY_OFFSET 0
`define TXTSU_EIC_ISR_NEMPTY 32'h00000001
`define ADDR_TXTSU_TSF_R0 5'h10
`define TXTSU_TSF_R0_VAL_R_OFFSET 0
`define TXTSU_TSF_R0_VAL_R 32'h0fffffff
`define TXTSU_TSF_R0_VAL_F_OFFSET 28
`define TXTSU_TSF_R0_VAL_F 32'hf0000000
`define ADDR_TXTSU_TSF_R1 5'h14
`define TXTSU_TSF_R1_PID_OFFSET 0
`define TXTSU_TSF_R1_PID 32'h0000001f
`define TXTSU_TSF_R1_FID_OFFSET 16
`define TXTSU_TSF_R1_FID 32'hffff0000
`define ADDR_TXTSU_TSF_R2 5'h18
`define TXTSU_TSF_R2_INCORRECT_OFFSET 0
`define TXTSU_TSF_R2_INCORRECT 32'h00000001
`define ADDR_TXTSU_TSF_CSR 5'h1c
`define TXTSU_TSF_CSR_FULL_OFFSET 16
`define TXTSU_TSF_CSR_FULL 32'h00010000
`define TXTSU_TSF_CSR_EMPTY_OFFSET 17
`define TXTSU_TSF_CSR_EMPTY 32'h00020000
`define TXTSU_TSF_CSR_USEDW_OFFSET 0
`define TXTSU_TSF_CSR_USEDW 32'h000000ff
`ifndef __SIMDRV_WR_TXTSU_SVH
`define __SIMDRV_WR_TXTSU_SVH 1
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`include "regs/txtsu_regs.vh"
class CSimDrv_TXTSU;
CBusAccessor acc_regs;
uint64_t base_addr;
function new(CBusAccessor regs_, uint64_t base_addr_);
base_addr = base_addr_;
acc_regs = regs_;
endfunction // new
task init();
writel(`ADDR_TXTSU_EIC_IER, 1);
endtask // init
task writel(uint32_t addr, uint32_t val);
acc_regs.write(base_addr + addr, val, 4);
endtask // writel
task readl(uint32_t addr, output uint32_t val);
uint64_t tmp;
acc_regs.read(base_addr + addr, tmp, 4);
val = tmp;
endtask // readl
task update(bit txts_irq);
uint32_t csr, r0, r1, r2;
if(!txts_irq)
return;
while(1) begin
readl(`ADDR_TXTSU_TSF_CSR, csr);
if(csr & `TXTSU_TSF_CSR_EMPTY)
break;
readl(`ADDR_TXTSU_TSF_R0, r0);
readl(`ADDR_TXTSU_TSF_R1, r1);
readl(`ADDR_TXTSU_TSF_R2, r2);
$display("txtsu: val %x pid %d fid %d incorrect %1b", r0, r1 & 'h1f, r1 >> 16, r2 & 1);
end // while (1)
endtask // update
endclass
`endif // `ifndef __SIMDRV_WR_TXTSU_SVH
......@@ -42,7 +42,7 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.hwinfo_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
......@@ -1045,7 +1045,7 @@ begin
end generate gen_dummy_resets;
end generate gen_no_network_stuff;
U_Tx_TSU : xwrsw_tx_tsu
U_Tx_TSU : xwr_tx_tsu
generic map (
g_num_ports => c_NUM_PORTS,
g_interface_mode => PIPELINED,
......
......@@ -76,7 +76,7 @@ package wrs_sdb_pkg is
date => x"20140916",
name => "WRSW NIC ")));
constant c_xwrsw_txtsu_sdb : t_sdb_device := (
constant c_xwr_txtsu_sdb : t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -280,7 +280,7 @@ package wrs_sdb_pkg is
1 => f_sdb_embed_device(c_xwr_nic_sdb, x"00020000"), --NIC
2 => f_sdb_embed_bridge(c_epbar_bridge_sdb, x"00030000"), --Endpoints
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00050000"), --VIC
4 => f_sdb_embed_device(c_xwrsw_txtsu_sdb, x"00051000"), --Txtsu
4 => f_sdb_embed_device(c_xwr_txtsu_sdb, x"00051000"), --Txtsu
5 => f_sdb_embed_device(c_xwrsw_rtu_sdb, x"00060000"), --RTU
6 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00053000"), --GPIO
7 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00054000"), --I2C
......
......@@ -39,7 +39,7 @@ use ieee.STD_LOGIC_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.hwinfo_pkg.all;
package wrsw_components_pkg is
......@@ -160,7 +160,7 @@ package wrsw_components_pkg is
tm_time_valid_o : out std_logic);
end component;
component xwrsw_tx_tsu
component xwr_tx_tsu
generic (
g_num_ports : integer;
g_interface_mode : t_wishbone_interface_mode;
......
......@@ -37,7 +37,7 @@ use ieee.STD_LOGIC_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.endpoint_pkg.all;
......@@ -160,7 +160,7 @@ package wrsw_top_pkg is
tm_time_valid_o : out std_logic);
end component;
component xwrsw_tx_tsu
component xwr_tx_tsu
generic (
g_num_ports : integer;
g_interface_mode : t_wishbone_interface_mode;
......
......@@ -43,7 +43,7 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
......
......@@ -43,7 +43,7 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.hwinfo_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
......@@ -1107,7 +1107,7 @@ begin
end generate gen_dummy_resets;
end generate gen_no_network_stuff;
U_Tx_TSU : xwrsw_tx_tsu
U_Tx_TSU : xwr_tx_tsu
generic map (
g_num_ports => c_NUM_PORTS,
g_interface_mode => PIPELINED,
......
......@@ -77,7 +77,7 @@ package wrs_sdb_pkg is
date => x"20140916",
name => "WRSW NIC ")));
constant c_xwrsw_txtsu_sdb : t_sdb_device := (
constant c_xwr_txtsu_sdb : t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -345,7 +345,7 @@ package wrs_sdb_pkg is
1 => f_sdb_embed_device(c_xwr_nic_sdb, x"00020000"), --NIC
2 => f_sdb_embed_bridge(c_epbar_bridge_sdb, x"00030000"), --Endpoints
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00050000"), --VIC
4 => f_sdb_embed_device(c_xwrsw_txtsu_sdb, x"00051000"), --Txtsu
4 => f_sdb_embed_device(c_xwr_txtsu_sdb, x"00051000"), --Txtsu
5 => f_sdb_embed_device(c_xwrsw_rtu_sdb, x"00060000"), --RTU
6 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00053000"), --GPIO
7 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00054000"), --I2C
......
......@@ -39,7 +39,7 @@ use ieee.STD_LOGIC_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.hwinfo_pkg.all;
package wrsw_components_pkg is
......@@ -160,7 +160,7 @@ package wrsw_components_pkg is
tm_time_valid_o : out std_logic);
end component;
component xwrsw_tx_tsu
component xwr_tx_tsu
generic (
g_num_ports : integer;
g_interface_mode : t_wishbone_interface_mode;
......
......@@ -37,7 +37,7 @@ use ieee.STD_LOGIC_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.endpoint_pkg.all;
......@@ -160,7 +160,7 @@ package wrsw_top_pkg is
tm_time_valid_o : out std_logic);
end component;
component xwrsw_tx_tsu
component xwr_tx_tsu
generic (
g_num_ports : integer;
g_interface_mode : t_wishbone_interface_mode;
......
......@@ -42,7 +42,7 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
......
......@@ -42,7 +42,7 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
......
......@@ -42,7 +42,7 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
......
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