Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit Switch - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
12
Issues
12
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
White Rabbit Switch - Gateware
Commits
a05ee6da
Commit
a05ee6da
authored
Jan 08, 2021
by
Maciej Lipinski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
bug caught in RX PCS
parent
05089204
Expand all
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
17482 additions
and
7129 deletions
+17482
-7129
xswc_output_block_new.vhd
modules/wrsw_swcore/xswc_output_block_new.vhd
+1
-1
main.sv
testbench/scb_top/main.sv
+47
-18
scb_top_sim_svwrap.svh
testbench/scb_top/scb_top_sim_svwrap.svh
+29
-16
wave.do
testbench/scb_top/wave.do
+17405
-7094
No files found.
modules/wrsw_swcore/xswc_output_block_new.vhd
View file @
a05ee6da
...
@@ -355,7 +355,7 @@ begin -- behavoural
...
@@ -355,7 +355,7 @@ begin -- behavoural
cycle_frozen
<=
'0'
;
cycle_frozen
<=
'0'
;
else
else
cycle_frozen_cnt
<=
cycle_frozen_cnt
+
1
;
cycle_frozen_cnt
<=
cycle_frozen_cnt
+
1
;
if
(
cycle_frozen_cnt
=
to_unsigned
(
765
,
10
))
then
-- waits max frame size... not good
if
(
cycle_frozen_cnt
=
to_unsigned
(
400
,
10
))
then
-- waits max frame size... not good
cycle_frozen
<=
'1'
;
cycle_frozen
<=
'1'
;
end
if
;
end
if
;
end
if
;
end
if
;
...
...
testbench/scb_top/main.sv
View file @
a05ee6da
...
@@ -309,28 +309,26 @@ module main;
...
@@ -309,28 +309,26 @@ module main;
portUnderTest
=
18'b000000000000000001
;
portUnderTest
=
18'b000000000000000001
;
// tx ,rx ,opt
// tx ,rx ,opt
trans_paths
[
0
]
=
'
{
0
,
1
,
1
};
trans_paths
[
0
]
=
'
{
0
,
1
,
1
};
trans_paths
[
1
]
=
'
{
1
,
0
,
1
};
//
trans_paths[1] = '{1 ,0 , 1 };
repeat_number
=
10000
;
repeat_number
=
10000
;
tries_number
=
1
;
tries_number
=
1
;
g_enable_pck_gaps
=
1
;
g_enable_pck_gaps
=
1
;
g_min_pck_gap
=
214
;
g_min_pck_gap
=
214
;
g_max_pck_gap
=
214
;
// to make it 250kHz
g_max_pck_gap
=
214
;
//=[500-(64+8)]/2 to make it 250kHz
g_force_payload_size
=
64
-
18
;
// header = 14 bytes | CRC = 4 bytes
g_force_payload_size
=
64
-
22
;
// header = 14 bytes | QTAG = 4 bytes | CRC = 4 bytes
sim_vlan_tab
[
0
]
=
'
{
'
{
32'hFFFFFFFF
,
8'h0
,
3'h0
,
1'b0
,
1'b0
,
1'b0
},
0
,
1'b1
};
sim_vlan_tab
[
0
]
=
'
{
'
{
32'hFFFFFFFF
,
8'h0
,
3'h0
,
1'b0
,
1'b0
,
1'b0
},
0
,
1'b1
};
// sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
g_do_vlan_config
=
0
;
// no VLANs
g_do_vlan_config
=
2
;
// snake EP configuration (tagging proper VLANs on ports
rx_forward_on_fmatch_full
=
1
;
rx_forward_on_fmatch_full
=
1
;
mac_br
=
1
;
mac_br
=
1
;
mac_single
=
1
;
mac_single
=
1
;
g_is_qvlan
=
0
;
g_is_qvlan
=
1
;
//QTAG with VID=0
g_do_vlan_config
=
0
;
// snake EP configuration (tagging proper VLANs on ports
g_set_untagging
=
3
;
// untagging all
g_set_untagging
=
2
;
// untagging
g_failure_scenario
=
15
;
g_failure_scenario
=
14
;
g_ignore_rx_test_check
=
1
;
g_ignore_rx_test_check
=
1
;
// ep_failure_type = 'h00; // failure on the link (break on fiber)
ep_failure_type
=
'h11
;
// reset tx EP (on simulation side)
end
end
//*/
//*/
...
@@ -1025,7 +1023,7 @@ module main;
...
@@ -1025,7 +1023,7 @@ module main;
$
display
(
""
)
;
$
display
(
""
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
""
)
;
$
display
(
""
)
;
end
end
// if(g_failure_scenario == x)
if
(
g_failure_scenario
==
13
)
// btrain problem - break link with respect to INPUT BLOCK state machine
if
(
g_failure_scenario
==
13
)
// btrain problem - break link with respect to INPUT BLOCK state machine
begin
begin
automatic
int
cnt_ld
=
0
;
automatic
int
cnt_ld
=
0
;
...
@@ -1053,8 +1051,8 @@ module main;
...
@@ -1053,8 +1051,8 @@ module main;
wait_cycles
(
10
)
;
wait_cycles
(
10
)
;
end
end
end
end
// if(g_failure_scenario == x)
if
(
g_failure_scenario
==
14
)
// btrain problem - break link
with respect to rx frame
if
(
g_failure_scenario
==
14
)
// btrain problem - break link
on which tx-ing frame (break "on fiber")
begin
begin
automatic
int
cnt_ld
=
0
;
automatic
int
cnt_ld
=
0
;
automatic
int
timeout
=
2000
;
automatic
int
timeout
=
2000
;
...
@@ -1082,7 +1080,38 @@ module main;
...
@@ -1082,7 +1080,38 @@ module main;
wait_cycles
(
200
)
;
wait_cycles
(
200
)
;
end
end
end
// if(g_failure_scenario == x)
if
(
g_failure_scenario
==
15
)
// btrain problem - break link on which tx-ing frame (break by tx EP_sim reset)
begin
automatic
int
cnt_ld
=
0
;
automatic
int
timeout
=
2000
;
automatic
integer
i
;
for
(
cnt_ld
=
1
;
cnt_ld
<
100
;
cnt_ld
++
)
begin
wait_cycles
(
300
)
;
$
display
(
"test with delay %d cycles
\n
"
,
cnt_ld
)
;
for
(
i
=
0
;
i
<
timeout
;
i
=
i
+
1
)
begin
if
(
DUT
.
U_Top
.
U_Wrapped_SCBCore
.
gen_network_stuff
.
gen_endpoints_and_phys
[
0
]
.
U_Endpoint_X
.
phy_rx_data_i
==
16'hFFFF
)
break
;
@
(
posedge
clk_sys
)
;
end
wait_cycles
(
cnt_ld
)
;
ep_ctrl
[
0
]
=
'b0
;
$
display
(
""
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> put in reset EP_0<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
""
)
;
wait_cycles
(
500
)
;
ep_ctrl
[
0
]
=
'b1
;
$
display
(
""
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Stop reset and initialize<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
""
)
;
wait_cycles
(
300
)
;
end
end
end
// if(g_failure_scenario == x)
end
end
join_none
;
//
join_none
;
//
...
...
testbench/scb_top/scb_top_sim_svwrap.svh
View file @
a05ee6da
...
@@ -55,6 +55,8 @@ module scb_top_sim_svwrap
...
@@ -55,6 +55,8 @@ module scb_top_sim_svwrap
reg
[
15
:
0
]
tx_data_invalid
[
g_num_ports
]
;
reg
[
15
:
0
]
tx_data_invalid
[
g_num_ports
]
;
reg
[
1
:
0
]
tx_k_invalid
[
g_num_ports
]
;
reg
[
1
:
0
]
tx_k_invalid
[
g_num_ports
]
;
wire
[
g_num_ports
-
1
:
0
]
rst_n_break
;
input
clk_sys_i
,
clk_ref_i
,
rst_n_i
,
clk_swc_mpm_core_i
;
input
clk_sys_i
,
clk_ref_i
,
rst_n_i
,
clk_swc_mpm_core_i
;
input
bit
[
g_num_ports
-
1
:
0
]
ep_ctrl_i
;
input
bit
[
g_num_ports
-
1
:
0
]
ep_ctrl_i
;
output
cpu_irq
;
output
cpu_irq
;
...
@@ -126,6 +128,8 @@ module scb_top_sim_svwrap
...
@@ -126,6 +128,8 @@ module scb_top_sim_svwrap
IWishboneMaster
#(
2
,
16
)
U_ep_src
(
clk_sys_i
,
rst_n_i
)
;
IWishboneMaster
#(
2
,
16
)
U_ep_src
(
clk_sys_i
,
rst_n_i
)
;
IWishboneSlave
#(
2
,
16
)
U_ep_snk
(
clk_sys_i
,
rst_n_i
)
;
IWishboneSlave
#(
2
,
16
)
U_ep_snk
(
clk_sys_i
,
rst_n_i
)
;
assign
rst_n_break
[
i
]
=
(
ep_ctrl_i
[
i
]
==
0
&&
ep_failure_type
==
'h11
)
?
1'b0
:
rst_n_i
;
wr_endpoint
wr_endpoint
#(
#(
.
g_simulation
(
1
)
,
.
g_simulation
(
1
)
,
...
@@ -140,11 +144,12 @@ module scb_top_sim_svwrap
...
@@ -140,11 +144,12 @@ module scb_top_sim_svwrap
.
clk_ref_i
(
clk_ref_phys
[
i
])
,
.
clk_ref_i
(
clk_ref_phys
[
i
])
,
.
clk_sys_i
(
clk_sys_i
)
,
.
clk_sys_i
(
clk_sys_i
)
,
.
clk_dmtd_i
(
clk_ref_i
)
,
.
clk_dmtd_i
(
clk_ref_i
)
,
.
rst_sys_n_i
(
rst_n_i
)
,
.
rst_sys_n_i
(
rst_n_break
[
i
])
,
.
rst_ref_n_i
(
rst_n_i
)
,
.
rst_ref_n_i
(
rst_n_break
[
i
])
,
.
rst_dmtd_n_i
(
rst_n_i
)
,
.
rst_dmtd_n_i
(
rst_n_break
[
i
])
,
.
rst_txclk_n_i
(
rst_n_i
)
,
.
rst_txclk_n_i
(
rst_n_break
[
i
])
,
.
rst_rxclk_n_i
(
rst_n_i
)
,
.
rst_rxclk_n_i
(
rst_n_break
[
i
])
,
.
pps_csync_p1_i
(
1'b0
)
,
.
pps_csync_p1_i
(
1'b0
)
,
.
phy_rst_o
(
phys_out
[
i
]
.
rst
)
,
.
phy_rst_o
(
phys_out
[
i
]
.
rst
)
,
...
@@ -243,8 +248,13 @@ module scb_top_sim_svwrap
...
@@ -243,8 +248,13 @@ module scb_top_sim_svwrap
from_port
[
i
]
=
new
(
U_ep_snk
.
get_accessor
())
;
from_port
[
i
]
=
new
(
U_ep_snk
.
get_accessor
())
;
to_port
[
i
]
=
new
(
U_ep_src
.
get_accessor
())
;
to_port
[
i
]
=
new
(
U_ep_src
.
get_accessor
())
;
while
(
1
)
begin
@
(
ep_ctrl_i
[
i
]
==
0
&&
ep_failure_type
==
'h11
)
;
@
(
posedge
clk_sys_i
)
;
@
(
posedge
ep_ctrl_i
[
i
])
repeat
(
50
)
@
(
posedge
clk_sys_i
)
;
ep_drv
.
init
(
0
)
;
end
end
end
end
// for (i=0; i<g_num_ports; i++)
end
// for (i=0; i<g_num_ports; i++)
endgenerate
endgenerate
...
@@ -258,20 +268,24 @@ module scb_top_sim_svwrap
...
@@ -258,20 +268,24 @@ module scb_top_sim_svwrap
///////////////// nasty hack by Maciej /////////////////
///////////////// nasty hack by Maciej /////////////////
// causing sync error in the Switch
// causing sync error in the Switch
// assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : 'h00BC;
// assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : tx_data_invalid[j];
// assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : 2'b01;
// assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : tx_k_invalid[j];
assign
td
[
18
*
j
+
15
:
18
*
j
]
=
ep_ctrl_i
[
j
]
?
phys_out
[
j
]
.
tx_data
:
tx_data_invalid
[
j
]
;
assign
td
[
18
*
j
+
17
:
18
*
j
+
16
]
=
ep_ctrl_i
[
j
]
?
phys_out
[
j
]
.
tx_k
:
tx_k_invalid
[
j
]
;
// link works when
// ep_ctrl_i = 1 -> this means we want it to work
// ep_failure_type > 10 -> for ep_failure_type greater/equal 10... filure is done differently, so the link should work
assign
td
[
18
*
j
+
15
:
18
*
j
]
=
(
ep_ctrl_i
[
j
]
==
1
||
ep_failure_type
>
'h10
)
?
phys_out
[
j
]
.
tx_data
:
tx_data_invalid
[
j
]
;
assign
td
[
18
*
j
+
17
:
18
*
j
+
16
]
=
(
ep_ctrl_i
[
j
]
==
1
||
ep_failure_type
>
'h10
)
?
phys_out
[
j
]
.
tx_k
:
tx_k_invalid
[
j
]
;
// causing transmission error in the driving simulation
// causing transmission error in the driving simulation
assign
phys_in
[
j
]
.
tx_enc_err
=
~
ep_ctrl_i
[
j
]
;
assign
phys_in
[
j
]
.
tx_enc_err
=
(
ep_ctrl_i
[
j
]
==
1
||
ep_failure_type
>
'h10
)
?
1'b0
:
1'b1
;
//
~ep_ctrl_i[j];
///////////////////////////////////////////////////////
///////////////////////////////////////////////////////
assign
phys_in
[
j
]
.
ref_clk
=
clk_ref_phys
[
j
]
;
assign
phys_in
[
j
]
.
ref_clk
=
clk_ref_phys
[
j
]
;
assign
phys_in
[
j
]
.
rx_data
=
rd
[
18
*
j
+
15
:
18
*
j
]
;
assign
phys_in
[
j
]
.
rx_data
=
rd
[
18
*
j
+
15
:
18
*
j
]
;
assign
phys_in
[
j
]
.
rx_k
=
rd
[
18
*
j
+
17
:
18
*
j
+
16
]
;
assign
phys_in
[
j
]
.
rx_k
=
rd
[
18
*
j
+
17
:
18
*
j
+
16
]
;
assign
phys_in
[
j
]
.
rx_clk
=
clk_ref_i
;
assign
phys_in
[
j
]
.
rx_clk
=
clk_ref_i
;
// assign phys_in[j].tx_enc_err = 0;
assign
phys_in
[
j
]
.
rx_enc_err
=
0
;
assign
phys_in
[
j
]
.
rx_enc_err
=
0
;
...
@@ -286,7 +300,6 @@ module scb_top_sim_svwrap
...
@@ -286,7 +300,6 @@ module scb_top_sim_svwrap
phys_out
[
j
]
.
tx_data
)
;
phys_out
[
j
]
.
tx_data
)
;
end
end
always
@
(
posedge
clk_sys_i
)
begin
always
@
(
posedge
clk_sys_i
)
begin
integer
jj
;
integer
jj
;
if
(
ep_ctrl_i
[
j
]
==
1
)
begin
if
(
ep_ctrl_i
[
j
]
==
1
)
begin
...
...
testbench/scb_top/wave.do
View file @
a05ee6da
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment