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White Rabbit Switch - Gateware
Commits
a72c35b0
Commit
a72c35b0
authored
Sep 13, 2016
by
Grzegorz Daniluk
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swcore: add wishbone register to enable dropping traffic in OB if HP frames are queued
parent
e94dffe1
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9 changed files
with
57 additions
and
36 deletions
+57
-36
swc_core.vhd
modules/wrsw_swcore/swc_core.vhd
+2
-10
swc_swcore_pkg.vhd
modules/wrsw_swcore/swc_swcore_pkg.vhd
+4
-8
swc_wbgen2_pkg.vhd
modules/wrsw_swcore/swc_wbgen2_pkg.vhd
+4
-2
swc_wishbone_slave.vhd
modules/wrsw_swcore/swc_wishbone_slave.vhd
+32
-8
wrsw_swcore.wb
modules/wrsw_swcore/wrsw_swcore.wb
+13
-0
xswc_core.vhd
modules/wrsw_swcore/xswc_core.vhd
+2
-4
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+0
-2
wrsw_components_pkg.vhd
top/bare_top/wrsw_components_pkg.vhd
+0
-1
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+0
-1
No files found.
modules/wrsw_swcore/swc_core.vhd
View file @
a72c35b0
...
...
@@ -131,14 +131,8 @@ entity swc_core is
-------------------------------------------------------------------------------
pp_req_i
:
in
std_logic_vector
(
g_num_ports
-
1
downto
0
);
pp_quanta_i
:
in
std_logic_vector
(
g_num_ports
*
16
-
1
downto
0
);
pp_classes_i
:
in
std_logic_vector
(
g_num_ports
*
8
-
1
downto
0
);
------------------------------------------------------------------------------
-- I/F misc
-------------------------------------------------------------------------------
shaper_drop_at_hp_ena_i
:
in
std_logic
);
pp_classes_i
:
in
std_logic_vector
(
g_num_ports
*
8
-
1
downto
0
)
);
end
swc_core
;
architecture
rtl
of
swc_core
is
...
...
@@ -189,8 +183,6 @@ architecture rtl of swc_core is
src_i
=>
src_i
,
src_o
=>
src_o
,
shaper_drop_at_hp_ena_i
=>
shaper_drop_at_hp_ena_i
,
global_pause_i
=>
global_pause_i
,
perport_pause_i
=>
perport_pause_i
,
...
...
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @
a72c35b0
...
...
@@ -709,9 +709,7 @@ component swc_multiport_pck_pg_free_module is
rtu_rsp_i
:
in
t_rtu_response_array
(
g_num_ports
-
1
downto
0
);
rtu_ack_o
:
out
std_logic_vector
(
g_num_ports
-
1
downto
0
);
nomem_o
:
out
std_logic
;
shaper_drop_at_hp_ena_i
:
in
std_logic
nomem_o
:
out
std_logic
);
end
component
;
...
...
@@ -777,10 +775,8 @@ component swc_multiport_pck_pg_free_module is
pp_req_i
:
in
std_logic_vector
(
g_num_ports
-
1
downto
0
);
pp_quanta_i
:
in
std_logic_vector
(
g_num_ports
*
16
-
1
downto
0
);
pp_classes_i
:
in
std_logic_vector
(
g_num_ports
*
8
-
1
downto
0
);
shaper_drop_at_hp_ena_i
:
in
std_logic
);
pp_classes_i
:
in
std_logic_vector
(
g_num_ports
*
8
-
1
downto
0
)
);
end
component
;
component
swc_ll_read_data_validation
is
...
...
@@ -874,7 +870,7 @@ component swc_multiport_pck_pg_free_module is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
modules/wrsw_swcore/swc_wbgen2_pkg.vhd
View file @
a72c35b0
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : swc_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrsw_swcore.wb
-- Created :
Wed Aug 10 12:03:23
2016
-- Created :
Tue Sep 13 14:08:37
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_swcore.wb
...
...
@@ -43,12 +43,14 @@ package swc_wbgen2_pkg is
csr_new_stat_o
:
std_logic
;
afull_thr_o
:
std_logic_vector
(
31
downto
0
);
afull_thr_load_o
:
std_logic
;
hp_ob_drop_mask_o
:
std_logic_vector
(
18
downto
0
);
end
record
;
constant
c_swc_out_registers_init_value
:
t_swc_out_registers
:
=
(
csr_new_stat_o
=>
'0'
,
afull_thr_o
=>
(
others
=>
'0'
),
afull_thr_load_o
=>
'0'
afull_thr_load_o
=>
'0'
,
hp_ob_drop_mask_o
=>
(
others
=>
'0'
)
);
function
"or"
(
left
,
right
:
t_swc_in_registers
)
return
t_swc_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
...
...
modules/wrsw_swcore/swc_wishbone_slave.vhd
View file @
a72c35b0
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : swc_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wrsw_swcore.wb
-- Created :
Wed Aug 10 12:03:23
2016
-- Created :
Tue Sep 13 14:08:37
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_swcore.wb
...
...
@@ -21,7 +21,7 @@ entity swc_wishbone_slave is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
@@ -39,11 +39,12 @@ architecture syn of swc_wishbone_slave is
signal
swc_csr_new_stat_dly0
:
std_logic
;
signal
swc_csr_new_stat_int
:
std_logic
;
signal
swc_hp_ob_drop_mask_int
:
std_logic_vector
(
18
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
...
...
@@ -68,6 +69,7 @@ begin
rddata_reg
<=
"00000000000000000000000000000000"
;
swc_csr_new_stat_int
<=
'0'
;
regs_o
.
afull_thr_load_o
<=
'0'
;
swc_hp_ob_drop_mask_int
<=
"0000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -82,8 +84,8 @@ begin
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
case
rwaddr_reg
(
2
downto
0
)
is
when
"00
0
"
=>
if
(
wb_we_i
=
'1'
)
then
swc_csr_new_stat_int
<=
wrdata_reg
(
0
);
end
if
;
...
...
@@ -121,26 +123,46 @@ begin
rddata_reg
(
29
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
when
"0
0
1"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
15
downto
0
)
<=
regs_i
.
stat_min_fpg_i
;
rddata_reg
(
31
downto
16
)
<=
regs_i
.
stat_max_fpg_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
when
"
0
10"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
cur_fpg_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11"
=>
when
"
0
11"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
afull_thr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
afull_thr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
swc_hp_ob_drop_mask_int
<=
wrdata_reg
(
18
downto
0
);
end
if
;
rddata_reg
(
18
downto
0
)
<=
swc_hp_ob_drop_mask_int
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
...
...
@@ -174,6 +196,8 @@ begin
-- pages
-- pages
regs_o
.
afull_thr_o
<=
wrdata_reg
(
31
downto
0
);
-- Port mask
regs_o
.
hp_ob_drop_mask_o
<=
swc_hp_ob_drop_mask_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
modules/wrsw_swcore/wrsw_swcore.wb
View file @
a72c35b0
...
...
@@ -106,5 +106,18 @@ peripheral {
};
};
reg {
name = "HP OB register";
description = "Enables dropping regular traffic at the output of swcore ports when HP traffic is queued.";
prefix = "HP_OB";
field {
name = "Port mask";
prefix = "DROP_MASK";
size = 19;
type = SLV;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
};
modules/wrsw_swcore/xswc_core.vhd
View file @
a72c35b0
...
...
@@ -109,8 +109,6 @@ entity xswc_core is
global_pause_i
:
in
t_global_pause_request_array
(
g_num_global_pause
-1
downto
0
);
shaper_drop_at_hp_ena_i
:
in
std_logic
:
=
'0'
;
-------------------------------------------------------------------------------
-- I/F with Tx PAUSE triggers (i.e. Endpoints)
-------------------------------------------------------------------------------
...
...
@@ -420,7 +418,7 @@ architecture rtl of xswc_core is
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_i
,
wb_adr_i
=>
wb_in
.
adr
(
1
downto
0
),
wb_adr_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_dat_i
=>
wb_in
.
dat
,
wb_dat_o
=>
wb_out
.
dat
,
wb_cyc_i
=>
wb_in
.
cyc
,
...
...
@@ -678,7 +676,7 @@ architecture rtl of xswc_core is
--: output traffic shaper (PAUSE + time-aware-shaper)
-------------------------------------------------------------------------------
ots_output_mask_i
=>
ots2ob_output_masks
(
i
),
ots_output_drop_at_rx_hp_i
=>
shaper_drop_at_hp_ena_i
,
ots_output_drop_at_rx_hp_i
=>
regs_fromwb
.
hp_ob_drop_mask_o
(
i
)
,
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
...
...
top/bare_top/scb_top_bare.vhd
View file @
a72c35b0
...
...
@@ -831,8 +831,6 @@ begin
snk_i
=>
swc_snk_in
,
snk_o
=>
swc_snk_out
,
shaper_drop_at_hp_ena_i
=>
shaper_drop_at_hp_ena
,
-- pause stuff
global_pause_i
=>
global_pause
,
perport_pause_i
=>
fc_rx_pause
,
...
...
top/bare_top/wrsw_components_pkg.vhd
View file @
a72c35b0
...
...
@@ -301,7 +301,6 @@ package wrsw_components_pkg is
global_pause_i
:
in
t_global_pause_request_array
(
g_num_global_pause
-1
downto
0
);
perport_pause_i
:
in
t_pause_request_array
(
g_num_ports
-1
downto
0
);
shaper_drop_at_hp_ena_i
:
in
std_logic
:
=
'0'
;
rtu_rsp_i
:
in
t_rtu_response_array
(
g_num_ports
-
1
downto
0
);
rtu_ack_o
:
out
std_logic_vector
(
g_num_ports
-
1
downto
0
);
rtu_abort_o
:
out
std_logic_vector
(
g_num_ports
-
1
downto
0
);
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
a72c35b0
...
...
@@ -360,7 +360,6 @@ package wrsw_top_pkg is
global_pause_i
:
in
t_global_pause_request_array
(
g_num_global_pause
-1
downto
0
);
perport_pause_i
:
in
t_pause_request_array
(
g_num_ports
-1
downto
0
);
shaper_drop_at_hp_ena_i
:
in
std_logic
:
=
'0'
;
dbg_o
:
out
std_logic_vector
(
g_num_dbg_vector_width
-
1
downto
0
);
rtu_rsp_i
:
in
t_rtu_response_array
(
g_num_ports
-
1
downto
0
);
rtu_ack_o
:
out
std_logic_vector
(
g_num_ports
-
1
downto
0
);
...
...
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