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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
a9faef63
Commit
a9faef63
authored
Apr 09, 2014
by
Grzegorz Daniluk
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add and correct licensing headers
parent
b8643bb4
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98 changed files
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1044 additions
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146 deletions
+1044
-146
wrsw_hwdu.vhd
modules/wrsw_hwdu/wrsw_hwdu.vhd
+20
-2
xwrsw_hwdu.vhd
modules/wrsw_hwdu/xwrsw_hwdu.vhd
+20
-2
hwinfo_pkg.vhd
modules/wrsw_hwiu/hwinfo_pkg.vhd
+33
-0
wrsw_hwiu.vhd
modules/wrsw_hwiu/wrsw_hwiu.vhd
+20
-2
xwrsw_hwiu.vhd
modules/wrsw_hwiu/xwrsw_hwiu.vhd
+20
-2
nic_buffer.vhd
modules/wrsw_nic/nic_buffer.vhd
+19
-1
nic_constants_pkg.vhd
modules/wrsw_nic/nic_constants_pkg.vhd
+19
-1
nic_descriptor_manager.vhd
modules/wrsw_nic/nic_descriptor_manager.vhd
+19
-1
nic_descriptors_pkg.vhd
modules/wrsw_nic/nic_descriptors_pkg.vhd
+20
-2
nic_elastic_buffer.vhd
modules/wrsw_nic/nic_elastic_buffer.vhd
+33
-0
nic_rx_fsm.vhd
modules/wrsw_nic/nic_rx_fsm.vhd
+19
-1
nic_tx_fsm.vhd
modules/wrsw_nic/nic_tx_fsm.vhd
+19
-1
wrsw_nic.vhd
modules/wrsw_nic/wrsw_nic.vhd
+37
-0
xwrsw_nic.vhd
modules/wrsw_nic/xwrsw_nic.vhd
+44
-0
irq_ram.vhd
modules/wrsw_pstats/irq_ram.vhd
+19
-1
port_cntr.vhd
modules/wrsw_pstats/port_cntr.vhd
+19
-1
wrsw_pstats.vhd
modules/wrsw_pstats/wrsw_pstats.vhd
+19
-1
xwrsw_pstats.vhd
modules/wrsw_pstats/xwrsw_pstats.vhd
+19
-1
wrsw_rt_subsystem.vhd
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+34
-1
rtu_components_pkg.vhd
modules/wrsw_rtu/rtu_components_pkg.vhd
+3
-3
rtu_crc.vhd
modules/wrsw_rtu/rtu_crc.vhd
+2
-2
rtu_crc_pkg.vhd
modules/wrsw_rtu/rtu_crc_pkg.vhd
+2
-2
rtu_fast_match.vhd
modules/wrsw_rtu/rtu_fast_match.vhd
+2
-2
rtu_lookup_engine.vhd
modules/wrsw_rtu/rtu_lookup_engine.vhd
+1
-1
rtu_match.vhd
modules/wrsw_rtu/rtu_match.vhd
+2
-2
rtu_port.vhd
modules/wrsw_rtu/rtu_port.vhd
+1
-1
rtu_port_new.vhd
modules/wrsw_rtu/rtu_port_new.vhd
+1
-1
rtu_private_pkg.vhd
modules/wrsw_rtu/rtu_private_pkg.vhd
+1
-1
rtu_rr_arbiter.vhd
modules/wrsw_rtu/rtu_rr_arbiter.vhd
+1
-1
wrsw_rtu.vhd
modules/wrsw_rtu/wrsw_rtu.vhd
+1
-1
xwrsw_rtu.vhd
modules/wrsw_rtu/xwrsw_rtu.vhd
+1
-1
xwrsw_rtu_new.vhd
modules/wrsw_rtu/xwrsw_rtu_new.vhd
+1
-1
wrsw_shared_types_pkg.vhd
modules/wrsw_shared_types_pkg.vhd
+33
-0
mpm_async_fifo.vhd
modules/wrsw_swcore/mpm/mpm_async_fifo.vhd
+1
-1
mpm_async_fifo_ctrl.vhd
modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
+2
-2
mpm_async_grow_fifo.vhd
modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd
+2
-2
mpm_async_shrink_fifo.vhd
modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd
+2
-2
mpm_fifo_mem_cell.vhd
modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd
+2
-2
mpm_pipelined_mux.vhd
modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd
+2
-2
mpm_pkg.vhd
modules/wrsw_swcore/mpm/mpm_pkg.vhd
+2
-2
mpm_private_pkg.vhd
modules/wrsw_swcore/mpm/mpm_private_pkg.vhd
+2
-2
mpm_read_path.vhd
modules/wrsw_swcore/mpm/mpm_read_path.vhd
+33
-0
mpm_rpath_core_block.vhd
modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd
+33
-0
mpm_rpath_io_block.vhd
modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
+33
-0
mpm_top.vhd
modules/wrsw_swcore/mpm/mpm_top.vhd
+35
-0
mpm_write_path.vhd
modules/wrsw_swcore/mpm/mpm_write_path.vhd
+2
-2
swc_multiport_page_allocator.vhd
...rsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
+14
-14
swc_page_alloc.vhd
modules/wrsw_swcore/new_allocator/swc_page_alloc.vhd
+1
-1
swc_page_alloc_ram_bug.vhd
modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
+2
-2
swc_multiport_page_allocator.vhd
...rsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
+2
-2
swc_page_alloc_old.vhd
modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
+2
-2
swc_multiport_page_allocator.vhd
.../optimized_new_allocator/swc_multiport_page_allocator.vhd
+2
-2
swc_page_alloc.vhd
...es/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd
+1
-1
swc_page_alloc_ram_bug.vhd
...swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
+2
-2
swc_rd_wr_ram.vhd
modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd
+33
-0
swc_alloc_resource_manager.vhd
modules/wrsw_swcore/swc_alloc_resource_manager.vhd
+1
-1
swc_core.vhd
modules/wrsw_swcore/swc_core.vhd
+1
-1
swc_ll_read_data_validation.vhd
modules/wrsw_swcore/swc_ll_read_data_validation.vhd
+2
-2
swc_multiport_linked_list.vhd
modules/wrsw_swcore/swc_multiport_linked_list.vhd
+1
-1
swc_multiport_lost_pck_dealloc.vhd
modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd
+1
-1
swc_multiport_pck_pg_free_module.vhd
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
+1
-1
swc_ob_prio_queue.vhd
modules/wrsw_swcore/swc_ob_prio_queue.vhd
+2
-2
swc_output_queue_scheduler.vhd
modules/wrsw_swcore/swc_output_queue_scheduler.vhd
+2
-2
swc_output_traffic_shaper.vhd
modules/wrsw_swcore/swc_output_traffic_shaper.vhd
+1
-1
swc_pck_pg_free_module.vhd
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
+1
-1
swc_pck_transfer_arbiter.vhd
modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
+1
-1
swc_pck_transfer_input.vhd
modules/wrsw_swcore/swc_pck_transfer_input.vhd
+2
-2
swc_pck_transfer_output.vhd
modules/wrsw_swcore/swc_pck_transfer_output.vhd
+2
-2
swc_prio_encoder.vhd
modules/wrsw_swcore/swc_prio_encoder.vhd
+1
-1
swc_rr_arbiter.vhd
modules/wrsw_swcore/swc_rr_arbiter.vhd
+2
-2
swc_swcore_pkg.vhd
modules/wrsw_swcore/swc_swcore_pkg.vhd
+2
-2
xswc_core.vhd
modules/wrsw_swcore/xswc_core.vhd
+2
-2
xswc_input_block.vhd
modules/wrsw_swcore/xswc_input_block.vhd
+2
-2
xswc_output_block.vhd
modules/wrsw_swcore/xswc_output_block.vhd
+2
-2
xswc_output_block_new.vhd
modules/wrsw_swcore/xswc_output_block_new.vhd
+2
-2
wrsw_tatsu_pkg.vhd
modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd
+2
-2
xwrsw_tatsu.vhd
modules/wrsw_tatsu/xwrsw_tatsu.vhd
+2
-2
tru_endpoint.vhd
modules/wrsw_tru/tru_endpoint.vhd
+2
-2
tru_port.vhd
modules/wrsw_tru/tru_port.vhd
+2
-2
tru_port_wrapper.vhd
modules/wrsw_tru/tru_port_wrapper.vhd
+1
-1
tru_reconfig_rt_port_handler.vhd
modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd
+2
-2
tru_sub_vlan_pattern.vhd
modules/wrsw_tru/tru_sub_vlan_pattern.vhd
+2
-2
tru_trans_lacp_colect.vhd
modules/wrsw_tru/tru_trans_lacp_colect.vhd
+3
-3
tru_trans_lacp_dist.vhd
modules/wrsw_tru/tru_trans_lacp_dist.vhd
+1
-1
tru_trans_marker_trig.vhd
modules/wrsw_tru/tru_trans_marker_trig.vhd
+2
-2
tru_transition.vhd
modules/wrsw_tru/tru_transition.vhd
+2
-2
wrsw_tru.vhd
modules/wrsw_tru/wrsw_tru.vhd
+3
-3
wrsw_tru_pkg.vhd
modules/wrsw_tru/wrsw_tru_pkg.vhd
+2
-2
wrsw_tru_wb.vhd
modules/wrsw_tru/wrsw_tru_wb.vhd
+2
-2
xwrsw_tru.vhd
modules/wrsw_tru/xwrsw_tru.vhd
+2
-2
xwrsw_txtsu.vhd
modules/wrsw_txtsu/xwrsw_txtsu.vhd
+19
-1
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+35
-2
scb_top_sim.vhd
top/bare_top/scb_top_sim.vhd
+37
-0
wrsw_components_pkg.vhd
top/bare_top/wrsw_components_pkg.vhd
+36
-0
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+34
-0
scb_top_synthesis.vhd
top/scb_15ports/scb_top_synthesis.vhd
+36
-0
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+36
-0
scb_top_synthesis.vhd
top/scb_8ports/scb_top_synthesis.vhd
+36
-0
No files found.
modules/wrsw_hwdu/wrsw_hwdu.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2013-03-26
-- Last update: 2013-
03-26
-- Last update: 2013-
11-12
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -14,7 +14,25 @@
-- Debugging module, allows reading the content of selected registers inside
-- WR Switch GW through Wishbone interface.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_hwdu/xwrsw_hwdu.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,32 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2013-03-26
-- Last update: 2013-
03-26
-- Last update: 2013-
11-12
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Record-based wrapper for wrsw_hwdu module.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_hwiu/hwinfo_pkg.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Hardware Info Unit package
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : hwinfo_pkg.vhd
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2013-03-26
-- Last update: 2014-02-05
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
...
...
modules/wrsw_hwiu/wrsw_hwiu.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,32 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2013-03-26
-- Last update: 201
3-06
-05
-- Last update: 201
4-02
-05
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- std-logic-based wrapper for xwrsw_hwiu module.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_hwiu/xwrsw_hwiu.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2013-03-26
-- Last update: 201
3-06
-05
-- Last update: 201
4-02
-05
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -14,7 +14,25 @@
-- Debugging module, allows reading the content of selected registers inside
-- WR Switch GW through Wishbone interface.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/nic_buffer.vhd
View file @
a9faef63
...
...
@@ -12,7 +12,25 @@
-------------------------------------------------------------------------------
-- Description: RAM-based packet buffer for the NIC
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 - 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/nic_constants_pkg.vhd
View file @
a9faef63
...
...
@@ -12,7 +12,25 @@
-------------------------------------------------------------------------------
-- Description: Package with global NIC constants
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/nic_descriptor_manager.vhd
View file @
a9faef63
...
...
@@ -12,7 +12,25 @@
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 - 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/nic_descriptors_pkg.vhd
View file @
a9faef63
...
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-- File : nic_descriptors_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-C
o
-HT
-- Company : CERN BE-C
O
-HT
-- Created : 2010-11-24
-- Last update: 2012-03-16
-- Platform : FPGA-generic
...
...
@@ -13,7 +13,25 @@
-- Description: Package declares RX/TX descriptor data types and functions for
-- marshalling/unmarshalling the descriptors to/from SLVs
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 - 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/nic_elastic_buffer.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR NIC - Elastic Buffer
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : nic_elastic_buffer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-19
-- Last update: 2013-10-23
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
NUMERIC_STD
.
all
;
...
...
modules/wrsw_nic/nic_rx_fsm.vhd
View file @
a9faef63
...
...
@@ -14,7 +14,25 @@
-- the WRF sink, requests RX descriptors from RX descriptor manager and writes
-- the packet data and OOB into at specified addresses in the buffer.
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 - 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/nic_tx_fsm.vhd
View file @
a9faef63
...
...
@@ -12,7 +12,25 @@
-------------------------------------------------------------------------------
-- Description: The NIC transmit FSM
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 - 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_nic/wrsw_nic.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Network Interface Controller
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_nic.vhd
-- Author : Tomasz Wlostowski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-01-19
-- Last update: 2014-02-14
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- std-logic-based wrapper for xwrsw_nic module
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wrsw_nic/xwrsw_nic.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Network Interface Controller
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : xwrsw_nic.vhd
-- Author : Tomasz Wlostowski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-01-19
-- Last update: 2014-02-14
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Module responsible for passing Ethernet frames between the Linux running on
-- main ARM processor and 18 ports of the WR Switch. It contains a frame
-- buffer and two RAM blocks (TX descriptors memory, RX descriptors memory)
-- storing descriptors for frames received and frames to be sent. Frame buffer
-- stores all frames received from physical ports of the WR Switch (addressed to
-- the main processor) and frames that main processor wants to send to the ports
-- of WR Switch. Each frame has an associated descriptor which contains various
-- information about its structure.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wrsw_pstats/irq_ram.vhd
View file @
a9faef63
...
...
@@ -17,7 +17,25 @@
-- comming from each port are first aligned so that each port's flags start
-- from a new word in memory to simplify reading FSM in top module.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_pstats/port_cntr.vhd
View file @
a9faef63
...
...
@@ -15,7 +15,25 @@
-- events and increments counters stored in Block-RAM. Each word of RAM stores
-- g_cnt_pw counters so that they can be incremented all at once.
-------------------------------------------------------------------------------
-- Copyright (c) 2012, 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_pstats/wrsw_pstats.vhd
View file @
a9faef63
...
...
@@ -21,7 +21,25 @@
-- provides the information to the software saying which counters have
-- overflowed.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_pstats/xwrsw_pstats.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,25 @@
-- Description:
-- Record-based wrapper for wrsw_pstats module.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Grzegorz Daniluk / CERN
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch Real-Time Subsystem module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_rt_subsystem.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2014-02-06
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- LM32 + SoftPLL + some memory + debug UART
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wrsw_rtu/rtu_components_pkg.vhd
View file @
a9faef63
...
...
@@ -4,18 +4,18 @@
-------------------------------------------------------------------------------
-- File : wrsw_rtu_components_pkg.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-C
o
-HT
-- Company : CERN BE-C
O
-HT
-- Created : 2010-05-09
-- Last update: 2012-01-25
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Routing Table Unit components
--
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_crc.vhd
View file @
a9faef63
...
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-- File : wrsw_rtu_crc.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-C
o
-HT
-- Company : CERN BE-C
O
-HT
-- Created : 2010-05-12
-- Last update: 2012-06-22
-- Platform : FPGA-generic
...
...
@@ -15,7 +15,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_crc_pkg.vhd
View file @
a9faef63
...
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-- File : wrsw_rtu_crc_pkg.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-C
o
-HT
-- Company : CERN BE-C
O
-HT
-- Created : 2010-05-12
-- Last update: 2012-06-22
-- Platform : FPGA-generic
...
...
@@ -23,7 +23,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_fast_match.vhd
View file @
a9faef63
...
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-- File : rtu_fast_match.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-C
o
-HT
-- Company : CERN BE-C
O
-HT
-- Created : 2012-10-30
-- Last update: 2012-11-06
-- Platform : FPGA-generic
...
...
@@ -32,7 +32,7 @@
-- The request (valid up of the input rtu_req) shall be a strobe
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_lookup_engine.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Looks for MAC entry in CAM (BRAM)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_match.vhd
View file @
a9faef63
...
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-- File : rtu_match.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-C
o
-HT
-- Company : CERN BE-C
O
-HT
-- Created : 2010-05-08
-- Last update: 2012-07-17
-- Platform : FPGA-generic
...
...
@@ -17,7 +17,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
z Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_port.vhd
View file @
a9faef63
...
...
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_port_new.vhd
View file @
a9faef63
...
...
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_private_pkg.vhd
View file @
a9faef63
...
...
@@ -15,7 +15,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/rtu_rr_arbiter.vhd
View file @
a9faef63
...
...
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/wrsw_rtu.vhd
View file @
a9faef63
...
...
@@ -79,7 +79,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/xwrsw_rtu.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description: With usable interface
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Tomasz Wlostowski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_rtu/xwrsw_rtu_new.vhd
View file @
a9faef63
...
...
@@ -90,7 +90,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Tomasz Wlostowski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_shared_types_pkg.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch - shared types package
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_shared_types_pkg.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-22
-- Last update: 2013-11-14
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
...
...
modules/wrsw_swcore/mpm/mpm_async_fifo.vhd
View file @
a9faef63
...
...
@@ -15,7 +15,7 @@
-- output have same widths).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
-- Copyright (c) 2012 CERN
/ BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 201
2-01-30
-- Last update : 201
4-02-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies : genram_pkg
...
...
@@ -16,7 +16,7 @@
-- P. Alfke & Generic FIFO project by Rudolf Usselmann.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
CERN
-- Copyright (c) 2012
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd
View file @
a9faef63
...
...
@@ -7,7 +7,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 201
2-01-30
-- Last update : 201
4-02-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies : swc_fifo_mem_cell, swc_async_fifo_ctrl, genram_pkg
...
...
@@ -18,7 +18,7 @@
-- sideband channel (side_i/side_o) is provided for passing auxillary data.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
CERN
-- Copyright (c) 2012
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 201
2-01-30
-- Last update : 201
4-02-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies : mpm_fifo_mem_cell, mpm_async_fifo_ctrl, genram_pkg
...
...
@@ -17,7 +17,7 @@
-- An additional sideband channel (side_i/side_o) is provided for passing auxillary data.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
CERN
-- Copyright (c) 2012
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-0
1-30
-- Last update : 2012-0
7-17
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies : genram_pkg
...
...
@@ -14,7 +14,7 @@
-- Description: Small RAM block inferrable as Distributed RAM.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
-- Copyright (c) 2012 CERN
/ BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-0
1-30
-- Last update : 2012-0
7-17
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies :
...
...
@@ -15,7 +15,7 @@
-- encoded sel_i signal. Introduces (d_i, sel_i -> q_o) delay of 2 clk_i cycles.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
-- Copyright (c) 2012 CERN
/ BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_pkg.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,14 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-14
-- Last update: 2012-02-
14
-- Last update: 2012-02-
25
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_private_pkg.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-0
1-30
-- Last update : 2012-0
3-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies : genram_pkg
...
...
@@ -14,7 +14,7 @@
-- Description: Commonly used private components and functions.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
-- Copyright (c) 2012 CERN
/ BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/mpm/mpm_read_path.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Multiport Memory - Read Path
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : mpm_read_path.vhd
-- Author : Tomasz Włostowski, Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-02-12
-- Last update : 2013-11-07
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Multiport Memory - Read Path Core
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : mpm_rpath_core_block.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-02-12
-- Last update : 2012-02-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Multiport Memory - Read Path IO Block
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : mpm_rpath_io_block.vhd
-- Author : Tomasz Włostowski, Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-02-12
-- Last update : 2013-08-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wrsw_swcore/mpm/mpm_top.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : Multiport Memory, top level
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : mpm_top.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-02-12
-- Last update : 2013-03-27
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Simple, gray-encoded dual clock symmetric FIFO (input and
-- output have same widths).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wrsw_swcore/mpm/mpm_write_path.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 201
2-01-30
-- Last update : 201
3-11-07
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Dependencies : genram_pkg, gencores_pkg, mpm_async_grow_fifo, mpm_pipelined_mux,
...
...
@@ -15,7 +15,7 @@
-- Description: N-port MPM write path.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
View file @
a9faef63
...
...
@@ -6,29 +6,29 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
2-03-15
-- Last update: 201
4-02-04
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
...
...
modules/wrsw_swcore/new_allocator/swc_page_alloc.vhd
View file @
a9faef63
...
...
@@ -24,7 +24,7 @@
-- the input blocks.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2012-03-
18
-- Last update: 2012-03-
29
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -30,7 +30,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,14 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
2-03-19
-- Last update: 201
3-10-27
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
2-03-18
-- Last update: 201
3-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -66,7 +66,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
2-03-15
-- Last update: 201
4-03-14
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -32,7 +32,7 @@
-- max_time= 2*num_ports + 2 (time needed for handling by core) + 1 (arbitration)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd
View file @
a9faef63
...
...
@@ -24,7 +24,7 @@
-- the input blocks.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
3-10-23
-- Last update: 201
4-03-14
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -43,7 +43,7 @@
-- done_o _ _ _ _|-|_ _ _ _
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : SWCore - RAM model read-after-write
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_rd_wr_ram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-03-18
-- Last update: 2012-03-18
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wrsw_swcore/swc_alloc_resource_manager.vhd
View file @
a9faef63
...
...
@@ -76,7 +76,7 @@
-- we allocate now will be used for the next frame... -> it works, it seems
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
, Maciej Lipinski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_core.vhd
View file @
a9faef63
...
...
@@ -16,7 +16,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_ll_read_data_validation.vhd
View file @
a9faef63
...
...
@@ -23,7 +23,7 @@
-- can overtake the writting process.
-------------------------------------------------------------------------------
--
-- Copyright (c) 201
0 Maciej Lipinski / CERN
-- Copyright (c) 201
2 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -165,4 +165,4 @@ begin
read_req_i
;
-- no request, no answer :)
read_req_o
<=
mask_read_req
and
read_req_i
;
end
syn
;
\ No newline at end of file
end
syn
;
modules/wrsw_swcore/swc_multiport_linked_list.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description: this modules free pages of read/dropped modules
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_ob_prio_queue.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -124,4 +124,4 @@ begin -- behavoural
not_empty_o
<=
not_empty
;
end
behavoural
;
\ No newline at end of file
end
behavoural
;
modules/wrsw_swcore/swc_output_queue_scheduler.vhd
View file @
a9faef63
...
...
@@ -40,7 +40,7 @@
-- > that for dropping we use also strict scheduling but reverse order compared to the sending <
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -154,4 +154,4 @@ begin
onehot_o
=>
drop_queue_onehot_o
,
out_o
=>
drop_queue_index_o
);
end
syn
;
\ No newline at end of file
end
syn
;
modules/wrsw_swcore/swc_output_traffic_shaper.vhd
View file @
a9faef63
...
...
@@ -16,7 +16,7 @@
-- * time-aware-shaping (allow only chosen output queues for given time)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013
Maciej Lipinski / CERN
-- Copyright (c) 2013
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @
a9faef63
...
...
@@ -15,7 +15,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_pck_transfer_input.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -191,4 +191,4 @@ begin --arch
ib_busy_o
<=
'0'
when
(
pto_output_mask
=
zeros
)
else
'1'
;
end
syn
;
-- arch
\ No newline at end of file
end
syn
;
-- arch
modules/wrsw_swcore/swc_pck_transfer_output.vhd
View file @
a9faef63
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -144,4 +144,4 @@ begin --arch
-- ob_pck_size_o <= ob_pck_size;
ob_hp_o
<=
ob_hp
;
end
syn
;
-- arch
\ No newline at end of file
end
syn
;
-- arch
modules/wrsw_swcore/swc_prio_encoder.vhd
View file @
a9faef63
...
...
@@ -15,7 +15,7 @@
-- * output block as a queue scheduler (strick priority policy)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_rr_arbiter.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,14 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
0-04-08
-- Last update: 201
2-02-07
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,14 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 201
2-06-25
-- Last update: 201
3-11-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Tomasz Wlostowski, Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/xswc_core.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-29
-- Last update: 201
2-03-18
-- Last update: 201
3-11-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -16,7 +16,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/xswc_input_block.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-28
-- Last update: 201
2-03-16
-- Last update: 201
3-11-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -48,7 +48,7 @@
-- when already receving new pck (to prevent stalling)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/xswc_output_block.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,14 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
-- Last update: 201
2-03-16
-- Last update: 201
3-03-07
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_swcore/xswc_output_block_new.vhd
View file @
a9faef63
...
...
@@ -6,14 +6,14 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
-- Last update: 201
2-03-16
-- Last update: 201
4-02-18
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010
Maciej Lipinski / CERN
-- Copyright (c) 2010
- 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2013-03-01
-- Last update: 201
2-03-01
-- Last update: 201
3-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013
Maciej Lipinski / CERN
-- Copyright (c) 2013
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tatsu/xwrsw_tatsu.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2013-02-28
-- Last update: 201
2-02-28
-- Last update: 201
3-03-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -48,7 +48,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013
Maciej Lipinski / CERN
-- Copyright (c) 2013
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_endpoint.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 201
2-08-13
-- Last update: 201
3-02-06
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -19,7 +19,7 @@
-- e.g. bad connection) from affecting TRU.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_port.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 201
2-09-13
-- Last update: 201
3-08-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -16,7 +16,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_port_wrapper.vhd
View file @
a9faef63
...
...
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 201
2-09-13
-- Last update: 201
3-02-06
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -21,7 +21,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_sub_vlan_pattern.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 201
2-09-13
-- Last update: 201
3-03-14
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -18,7 +18,7 @@
-- make the forwarding decision (combination of more info can be used)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_trans_lacp_colect.vhd
View file @
a9faef63
...
...
@@ -2,11 +2,11 @@
-- Title : Topology Resolution Unit: Link Aggregation protocol, marker, distribution
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : tru_trans_lacp_
dis
t.vhd
-- File : tru_trans_lacp_
colec
t.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-09-10
-- Last update: 201
2-09-13
-- Last update: 201
3-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_trans_lacp_dist.vhd
View file @
a9faef63
...
...
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_trans_marker_trig.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-09-05
-- Last update: 201
2-09-13
-- Last update: 201
3-08-01
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -52,7 +52,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/tru_transition.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-09-10
-- Last update: 201
2-09-13
-- Last update: 201
3-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/wrsw_tru.vhd
View file @
a9faef63
...
...
@@ -2,11 +2,11 @@
-- Title : Topology Resolution Unit (wrapper)
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File :
tru_port_wrapper
.vhd
-- File :
wrsw_tru
.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 2012-09-1
3
-- Last update: 2012-09-1
4
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -17,7 +17,7 @@
-- (currently not supported but can be useful)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/wrsw_tru_pkg.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 201
2-09-13
-- Last update: 201
3-11-14
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/wrsw_tru_wb.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-28
-- Last update: 201
2-09-13
-- Last update: 201
3-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -16,7 +16,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_tru/xwrsw_tru.vhd
View file @
a9faef63
...
...
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-08-20
-- Last update: 201
2-09-13
-- Last update: 201
3-05-09
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -39,7 +39,7 @@
-- Pipelined response is available in 2 cycles.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012
Maciej Lipinski / CERN
-- Copyright (c) 2012
- 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrsw_txtsu/xwrsw_txtsu.vhd
View file @
a9faef63
...
...
@@ -22,7 +22,25 @@
-- port and frame identifiers) and passes them to PTP daemon.
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
--
-- Copyright (c) 2010 - 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
top/bare_top/scb_top_bare.vhd
View file @
a9faef63
-- Bare switch top module, without GTX transceivers and CPU bridge. Used as a
-- simulation top module.
-------------------------------------------------------------------------------
-- Title : WR Switch bare top level
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_bare.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-03-17
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Bare switch top module, without GTX transceivers and CPU bridge.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
...
...
top/bare_top/scb_top_sim.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch bare top level for simulation
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_sim.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-05
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Bare switch top module, without GTX transceivers and CPU bridge. Used as a
-- simulation top module.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
...
...
top/bare_top/wrsw_components_pkg.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch components package
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_components_pkg.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-14
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Package with WR Switch components
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch top level package
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_top_pkg.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-14
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
...
...
top/scb_15ports/scb_top_synthesis.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch 15-ports top level
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_synthesis.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2012-04-25
-- Last update: 2013-05-09
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WR Switch 15-port version top synthesis level.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch 18-ports top level
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_synthesis.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-03-20
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WR Switch 18-port version top synthesis level.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
top/scb_8ports/scb_top_synthesis.vhd
View file @
a9faef63
-------------------------------------------------------------------------------
-- Title : WR Switch 8-ports top level
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_synthesis.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2014-03-20
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WR Switch 8-port version top synthesis level.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
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