Commit aa1a8ab3 authored by Maciej Lipinski's avatar Maciej Lipinski

Importing swcore's testbench to the new repo: adding swcore testbench files from…

Importing swcore's testbench to the new repo: adding swcore testbench files from the old repo (hopefully with the history) to the new repo
parents dddedff7 f12efbef
// Fabric TAP emulator example.
// usage: (as root)
// tunctl -t tap0
// ifconfig tap0 192.168.100.100
// arping -I tap0 192.168.100.101
// you should see some ARP requests coming
`timescale 1ns / 1ps
`include "fabric_emu.sv"
`include "fabric_emu_tap.sv"
module main;
const int c_clock_period = 8;
reg clk = 0;
reg rst_n = 0;
`WRF_WIRES(from_tap); // Data coming from tap0 interface
`WRF_WIRES(to_tap); // Data going to tap0 interface
// generate clock and reset signals
always #(c_clock_period/2) clk <= ~clk;
initial begin
repeat(3) @(posedge clk);
rst_n = 1;
end
// Two fabric emulators talking to each other
fabric_emu_tap U_tap
(
.clk_sys_i(clk),
.rst_n_i(rst_n),
`WRF_CONNECT_SOURCE(rx, from_tap), // connect fabric source/sinks
`WRF_CONNECT_SINK(tx, to_tap)
);
fabric_emu U_emu
(
.clk_i(clk),
.rst_n_i(rst_n),
`WRF_CONNECT_SOURCE(rx, to_tap),
`WRF_CONNECT_SINK(tx, from_tap)
);
// Check if there's anything received by the TAP emulator
always @(posedge clk) if (U_emu.poll())
begin
ether_frame_t frame;
$display("TAP Emulator received a frame!");
U_emu.receive(frame);
dump_frame_header("EmuB RX: ", frame);
frame.hdr.src = 'h010203040506; // modify the MAC address and send the frame back to tap interface
U_emu.send(frame.hdr, frame.payload, frame.size);
end
endmodule // main
This diff is collapsed.
`ifndef __FABRIC_EMU_DEFS_SV
`define __FABRIC_EMU_DEFS_SV
/* Ethernet frame header extended with WR-compliant OOB signalling */
typedef struct {
bit no_mac; // when 1, there's no valid source MAC present in the frame header and the SRC MAC field must be filled by the endpoint
bit [47:0] dst; // DST MAC
bit [47:0] src; // SRC MAC
bit [15:0] ethertype;
bit is_802_1q; // when 1, the frame has 802.1q header
bit [11:0] vid; // VLAN ID
bit [2:0] prio; // PCP priority tag
int oob_type; // OOB TYPE: OOB_TYPE_TXTS = TX frame ID (for TX timestamping), OOB_TYPE_RXTS = RX timestamp
bit[15:0] oob_fid; //
bit [27:0] timestamp_r;
bit [3:0] timestamp_f;
bit [4:0] port_id;
bit has_timestamp; // when 1, the TX/RX timestamp is valid
} ether_header_t;
/* Full ethernet frame */
typedef struct {
ether_header_t hdr;
int size;
int payload[2048];
bit[31:0] fcs;
bit error;
bit has_payload;
} ether_frame_t;
/* WR-compliant TX frame timestamp */
typedef struct {
bit[15:0] fid;
bit [4:0] pid;
bit [27:0] timestamp_r;
bit [3:0] timestamp_f;
} tx_timestamp_t;
`timescale 1ns/1ps
/* Bus widths definition, taken from global_defs.vhd */
`define c_wrsw_ctrl_size 4
`define c_wrsw_oob_frame_id_size 16
`define c_wrsw_timestamp_size_r 28
`define c_wrsw_timestamp_size_f 4
`define c_wrsw_mac_addr_width 48
`define c_wrsw_vid_width 12
`define c_wrsw_prio_width 3
`define c_wrsw_num_ports 11
/* ctrl bus codes */
`define c_wrsw_ctrl_none 4'h0
`define c_wrsw_ctrl_dst_mac 4'h1
`define c_wrsw_ctrl_src_mac 4'h2
`define c_wrsw_ctrl_ethertype 4'h3
`define c_wrsw_ctrl_vid_prio 4'h4
`define c_wrsw_ctrl_tx_oob 4'h5
`define c_wrsw_ctrl_rx_oob 4'h6
`define c_wrsw_ctrl_payload 4'h7
/* OOB types */
`define OOB_TYPE_TXTS 1
`define OOB_TYPE_RXTS 2
`define QUEUE_MAX_FRAMES 128
//
// WhiteRabbit Fabric Interface (WRF) Macros
//
// declares basic fabric interface (only the mandatory singals)
// sink port list in a verilog/SV module, prefixed with "prefix":
// for example `WRF_PORTS_SINK(test) will generate the following signals
// test_sof_p1_i, test_eof_p1_i, test_data_i, etc....
`define WRF_PORTS_SINK(prefix) \
input [15:0] prefix``_data_i,\
input [3:0] prefix``_ctrl_i,\
input prefix``_bytesel_i,\
input prefix``_sof_p1_i,\
input prefix``_eof_p1_i,\
output prefix``_dreq_o,\
input prefix``_valid_i,\
input prefix``_rerror_p1_i
// array version
/*
`define WRF_PORTS_SINK_ARRAY(prefix) \
input [11*15-1:0] prefix``_data_i,\
input [11* 3-1:0] prefix``_ctrl_i,\
input [10:0] prefix``_bytesel_i,\
input [10:0] prefix``_sof_p1_i,\
input [10:0] prefix``_eof_p1_i[size - 1 : 0],\
output[10:0] prefix``_dreq_o,\
input [10:0] prefix``_valid_i,\
input [10:0] prefix``_rerror_p1_i
*/
// same as above but with all WRF signals
`define WRF_FULL_PORTS_SINK(prefix) \
`WRF_PORTS_SINK(prefix),\
output prefix``_terror_p1_o,\
input prefix``_idle_i,\
input prefix``_tabort_p1_i,\
output prefix``_rabort_p1_o
// like the macro above, but for fabric source, mandatory signals only
`define WRF_PORTS_SOURCE(prefix) \
output [15:0] prefix``_data_o,\
output [3:0] prefix``_ctrl_o,\
output prefix``_bytesel_o,\
output prefix``_sof_p1_o,\
output prefix``_eof_p1_o,\
input prefix``_dreq_i,\
output prefix``_valid_o,\
output prefix``_rerror_p1_o
// same as above, but for full WRF
`define WRF_FULL_PORTS_SOURCE(prefix) \
`WRF_PORTS_SOURCE(prefix), \
input prefix``_terror_p1_i,\
output prefix``_idle_o,\
output prefix``_tabort_p1_o,\
input prefix``_rabort_p1_i
// declares a list of verilog/SV wires for a given fabric name
`define WRF_WIRES(prefix) \
wire [15:0] prefix``_data;\
wire [3 :0] prefix``_ctrl;\
wire prefix``_bytesel;\
wire prefix``_dreq;\
wire prefix``_valid;\
wire prefix``_sof_p1;\
wire prefix``_eof_p1;\
wire prefix``_rerror_p1;
// same as above, but for full WRF
`define WRF_FULL_WIRES(prefix) \
`WRF_SIGNALS(prefix)\
wire prefix``_terror_p1;\
wire prefix``_idle;\
wire prefix``_tabort_p1;\
wire prefix``_rabort_p1;
// Connects fabric sink ports prefixed with port_pfx to fabric wires prefixed with fab_pfx
`define _WRF_CONNECT_MANDATORY_SINK(port_pfx, fab_pfx) \
.port_pfx``_data_i(fab_pfx``_data),\
.port_pfx``_ctrl_i(fab_pfx``_ctrl),\
.port_pfx``_bytesel_i(fab_pfx``_bytesel),\
.port_pfx``_dreq_o(fab_pfx``_dreq),\
.port_pfx``_valid_i(fab_pfx``_valid),\
.port_pfx``_sof_p1_i(fab_pfx``_sof_p1),\
.port_pfx``_eof_p1_i(fab_pfx``_eof_p1),\
.port_pfx``_rerror_p1_i(fab_pfx``_rerror_p1)
`define _WRF_CONNECT_MANDATORY_SINK_ML(port_pfx, fab_pfx, port) \
.port_pfx``_data_i(fab_pfx``_data[(port + 1)*16 - 1 : port*16]),\
.port_pfx``_ctrl_i(fab_pfx``_ctrl[(port + 1)*4 - 1 : port*4 ]),\
.port_pfx``_bytesel_i(fab_pfx``_bytesel[port]),\
.port_pfx``_dreq_o(fab_pfx``_dreq[port]),\
.port_pfx``_valid_i(fab_pfx``_valid[port]),\
.port_pfx``_sof_p1_i(fab_pfx``_sof_p1[port]),\
.port_pfx``_eof_p1_i(fab_pfx``_eof_p1[port]),\
.port_pfx``_rerror_p1_i(fab_pfx``_rerror_p1[port])
// full fabric I/F version
`define WRF_FULL_CONNECT_SINK(port_pfx, fab_pfx) \
`_WRF_CONNECT_MANDATORY_SINK(port_pfx, fab_pfx), \
.port_pfx``_terror_p1_o(fab_pfx``_terror_p1),\
.port_pfx``_tabort_p1_i(fab_pfx``_tabort_p1),\
.port_pfx``_rabort_p1_o(fab_pfx``_rabort_p1),\
.port_pfx``_idle_i(fab_pfx``_idle)
`define WRF_FULL_CONNECT_SINK_ML(port_pfx, fab_pfx, port) \
`_WRF_CONNECT_MANDATORY_SINK_ML(port_pfx, fab_pfx, port), \
.port_pfx``_terror_p1_o(fab_pfx``_terror_p1[port]),\
// .port_pfx``_tabort_p1_i(fab_pfx``_tabort_p1[port]),\
.port_pfx``_rabort_p1_o(fab_pfx``_tabort_p1[port]),\
.port_pfx``_idle_i(fab_pfx``_idle[port])
// Connects fabric sink ports prefixed with port_pfx to fabric wires prefixed with fab_pfx
`define WRF_CONNECT_SINK(port_pfx, fab_pfx) \
`_WRF_CONNECT_MANDATORY_SINK(port_pfx, fab_pfx), \
.port_pfx``_terror_p1_o(),\
.port_pfx``_tabort_p1_i(1'b0),\
.port_pfx``_rabort_p1_o(),\
.port_pfx``_idle_i(1'b0)
`define WRF_CONNECT_SINK_ML(port_pfx, fab_pfx, port) \
`_WRF_CONNECT_MANDATORY_SINK_ML(port_pfx, fab_pfx, port), \
.port_pfx``_terror_p1_o(),\
.port_pfx``_tabort_p1_i(1'b0),\
.port_pfx``_rabort_p1_o(),\
.port_pfx``_idle_i(1'b0)
`define _WRF_CONNECT_MANDATORY_SOURCE(port_pfx, fab_pfx) \
.port_pfx``_data_o(fab_pfx``_data),\
.port_pfx``_ctrl_o(fab_pfx``_ctrl),\
.port_pfx``_bytesel_o(fab_pfx``_bytesel),\
.port_pfx``_dreq_i(fab_pfx``_dreq),\
.port_pfx``_valid_o(fab_pfx``_valid),\
.port_pfx``_sof_p1_o(fab_pfx``_sof_p1),\
.port_pfx``_eof_p1_o(fab_pfx``_eof_p1),\
.port_pfx``_rerror_p1_o(fab_pfx``_rerror_p1)
`define _WRF_CONNECT_MANDATORY_SOURCE_ML(port_pfx, fab_pfx, port) \
.port_pfx``_data_o(fab_pfx``_data[(port + 1)*16 - 1: port*16]),\
.port_pfx``_ctrl_o(fab_pfx``_ctrl[(port + 1)*4 - 1: port*4]),\
.port_pfx``_bytesel_o(fab_pfx``_bytesel[port]),\
.port_pfx``_dreq_i(fab_pfx``_dreq[port]),\
.port_pfx``_valid_o(fab_pfx``_valid[port]),\
.port_pfx``_sof_p1_o(fab_pfx``_sof_p1[port]),\
.port_pfx``_eof_p1_o(fab_pfx``_eof_p1[port]),\
.port_pfx``_rerror_p1_o(fab_pfx``_rerror_p1[port])
// same as above, but for source ports, full WRF version
`define WRF_FULL_CONNECT_SOURCE(port_pfx, fab_pfx) \
`_WRF_CONNECT_MANDATORY_SOURCE(port_pfx, fab_pfx),\
.port_pfx``_terror_p1_i(fab_pfx``_terror_p1),\
.port_pfx``_tabort_p1_o(fab_pfx``_tabort_p1),\
.port_pfx``_rabort_p1_i(fab_pfx``_rabort_p1),\
.port_pfx``_idle_o(fab_pfx``_idle)
`define WRF_FULL_CONNECT_SOURCE_ML(port_pfx, fab_pfx, port) \
`_WRF_CONNECT_MANDATORY_SOURCE_ML(port_pfx, fab_pfx, port),\
.port_pfx``_terror_p1_i(fab_pfx``_terror_p1[port]),\
.port_pfx``_tabort_p1_o(fab_pfx``_tabort_p1[port])
// .port_pfx``_rabort_p1_i(fab_pfx``_rabort_p1[port])
// .port_pfx``_idle_o(fab_pfx``_idle[port])
// same as above, but for source ports, basic WRF version
`define WRF_CONNECT_SOURCE(port_pfx, fab_pfx) \
`_WRF_CONNECT_MANDATORY_SOURCE(port_pfx, fab_pfx),\
.port_pfx``_terror_p1_i(1'b0),\
.port_pfx``_tabort_p1_o(),\
.port_pfx``_rabort_p1_i(1'b0),\
.port_pfx``_idle_o()
// same as above, but for source ports, basic WRF version
`define WRF_CONNECT_SOURCE_ML(port_pfx, fab_pfx, port) \
`_WRF_CONNECT_MANDATORY_SOURCE_ML(port_pfx, fab_pfx, port),\
.port_pfx``_terror_p1_i(1'b0),\
.port_pfx``_tabort_p1_o(),\
.port_pfx``_rabort_p1_i(1'b0),\
.port_pfx``_idle_o()
`endif
\ No newline at end of file
// Fabric emulator example, showing 2 fabric emulators connected together and exchanging packets.
`timescale 1ns / 1ps
`include "fabric_emu.sv"
module main;
const int c_clock_period = 8;
reg clk = 0;
reg rst_n = 0;
`WRF_WIRES(ab); // Emu A to B fabric
`WRF_WIRES(ba); // And the other way around
// generate clock and reset signals
always #(c_clock_period/2) clk <= ~clk;
initial begin
repeat(3) @(posedge clk);
rst_n = 1;
end
// Two fabric emulators talking to each other
fabric_emu U_emuA
(
.clk_i(clk),
.rst_n_i(rst_n),
`WRF_CONNECT_SOURCE(rx, ba), // connect fabric source/sinks
`WRF_CONNECT_SINK(tx, ab)
);
fabric_emu U_emuB
(
.clk_i(clk),
.rst_n_i(rst_n),
`WRF_CONNECT_SOURCE(rx, ab),
`WRF_CONNECT_SINK(tx, ba)
);
initial begin
ether_header_t hdr;
int buffer[1024];
int i;
wait(U_emuA.ready); // wait until both emulators are initialized
wait(U_emuB.ready);
hdr.src = 'h123456789abcdef;
hdr.dst = 'hcafeb1badeadbef;
hdr.ethertype = 1234;
hdr.is_802_1q = 0;
hdr.oob_type = `OOB_TYPE_RXTS;
hdr.timestamp_r = 10000;
hdr.timestamp_f = 4;
hdr.port_id = 5;
for(i=0;i<100;i++)
buffer[i] = i;
// simulate some flow throttling
U_emuA.simulate_rx_throttling(1, 50);
U_emuA.send(hdr, buffer, 100);
hdr.src = 'h0f0e0a0b0d00;
U_emuB.send(hdr, buffer, 50);
end
// Check if there's anything received by EMU B
always @(posedge clk) if (U_emuB.poll())
begin
ether_frame_t frame;
$display("Emulator B received a frame!");
U_emuB.receive(frame);
dump_frame_header("EmuB RX: ", frame);
end
// Check if there's anything received by EMU A
always @(posedge clk) if (U_emuA.poll())
begin
ether_frame_t frame;
$display("Emulator A received a frame!");
U_emuA.receive(frame);
dump_frame_header("EmuA RX: ", frame);
end
endmodule // main
`timescale 1ns/1ps
/* Ethernet FCS calculator class */
class CCRC32;
protected bit [31:0] crc;
protected bit [31:0] crc_tab[256];
function new();
reg [31:0] c, poly;
int i, j;
poly = 32'hEDB88320;
for (i = 0; i < 256; i++) begin
c = i;
for (j = 8; j > 0; j--) begin
if (c & 1)
c = (c >> 1) ^ poly;
else
c >>= 1;
end
crc_tab[i] = c;
end
crc = 32'hffffffff;
endfunction // new
function bit[31:0] bitrev(bit[31:0] x, int n);
reg [31:0] y= 0;
int i;
for(i=0;i<n;i++) if(x & (1<<i)) y|= 1<< (n-1-i);
bitrev=y;
endfunction
task update_int(bit[7:0] x);
crc = ((crc >> 8) & 32'h00FFFFFF) ^ crc_tab[(crc ^ bitrev(x,8)) & 32'hFF];
endtask
task update(input [15:0] x, int bytesel);
update_int(x[15:8]);
if(!bytesel)
update_int(x[7:0]);
endtask // update
function bit[31:0] get();
get = bitrev(crc ^ 32'hffffffff, 32);
endfunction // get
endclass
/* Simple packet queue */
class CPacketQueue;
protected int head, tail, count;
protected int size;
protected ether_frame_t d[];
function new (int _size);
size = _size;
head = 0;
tail = 0;
count = 0;
d = new [_size];
endfunction // new
task push(input ether_frame_t frame);
if(count == size) begin
$display("CPacketQueue::push(): queue overflow");
$stop();
end
d[head] = frame;
head++; if(head == size) head = 0;
count++;
endtask // push
task pop (output ether_frame_t frame);
if(count <= 0) begin
$display("CPacketQueue::pop(): queue empty");
$stop();
end
frame = d[tail];
tail++; if(tail == size) tail = 0;
count--;
endtask // pop
function int get_count();
return count;
endfunction // get_count
/* Looks for a packet with matching OOB frame identifier and updates it with the new timestamp value */
function int update_tx_timestamp(input [15:0] oob_fid,
input [4:0] port_id,
input [31:0] ts_value);
int i;
i = tail;
while(i != head)
begin
if(d[i].hdr.oob_type == `OOB_TYPE_TXTS && d[i].hdr.oob_fid == oob_fid) begin
d[i].hdr.timestamp_r = ts_value[27:0];
d[i].hdr.timestamp_f = ts_value[31:28];
d[i].hdr.has_timestamp = 1;
return 1;
end
i++;
if(i == count) i = 0;
end
return 0;
endfunction // update_tx_timestamp
endclass // CPacketQueue
// converts a nbytes-long number (hex) to hexadecimal string
function automatic string hex_2_str(input [47:0] hex, int nbytes);
int i;
string s = "";
string hexchars = "0123456789abcdef";
reg [47:0] t;
t = hex;
for(i=0; i<2*nbytes; i++) begin
s= {hexchars[t&'hf], s};
t=t>>4;
end
return s;
endfunction // hex_2_str
// formats an Ethernet frame header as a nice looking string
function automatic string format_ether_header(input ether_header_t hdr);
string s = {"DST: ", hex_2_str(hdr.dst, 6),
" SRC: ", hex_2_str(hdr.src, 6),
" Type: 0x",hex_2_str(hdr.ethertype, 2) };
if(hdr.is_802_1q) s = {s, " VLAN: 0x", hex_2_str({4'b0,hdr.vid}, 2), " PRIO: ", hex_2_str({5'b0, hdr.prio},1) };
return s;
endfunction // automatic
task dump_frame_header(string s, ether_frame_t frame);
if(frame.hdr.ethertype == frame.size)
$display("%s %s (size: %d, port_id: %4d) length = %d %s %s", s, format_ether_header(frame.hdr),frame.hdr.ethertype, frame.hdr.src >> 44, frame.size, frame.error?"ERROR":"OK", frame.hdr.has_timestamp?"TS":"NoTS");
else
begin
$display("%s %s (size: %d, port_id: %4d) length = %d %s %s =>> ERROR here", s, format_ether_header(frame.hdr),frame.hdr.ethertype, frame.hdr.src >> 44, frame.size, frame.error?"ERROR":"OK", frame.hdr.has_timestamp?"TS":"NoTS");
$fatal("dupa");
end
endtask // dump_frame_header
\ No newline at end of file
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
[0..31] : 4294967295;
END;
vlib work
vlog -sv fabric_emu_demo.sv
vsim work.main -voptargs="+acc"
radix -hexadecimal
do wave.do
run 300us
wave zoomfull
\ No newline at end of file
vlib work
#vcom ../../../platform/altera/generic_sync_fifo.vhd
#vcom ../../../platform/altera/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem.vhd
vcom ../../../modules/wrsw_swcore/swc_page_alloc.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_page_allocator.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_linked_list.vhd
vcom ../../../modules/wrsw_swcore/swc_input_block.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_write_pump.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_input.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_output.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_pg_free_module.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
vcom ../../../modules/wrsw_swcore/swc_ob_prio_queue.vhd
vcom ../../../modules/wrsw_swcore/swc_output_block.vhd
vcom ../../../sim/vhdl_stdio/PCK_FIO_1993.vhd
vcom ../../../sim/vhdl_stdio/PCK_FIO_1993_BODY.vhd
vcom ../../../modules/wrsw_swcore/swc_core.vhd
vlog -sv swc_core.v4.sv
#vlog -sv swc_core.sv
vsim work.main -voptargs="+acc"
radix -hexadecimal
do wave.do
run 300us
#wave zoomfull
vlib work
#vcom ../../../platform/altera/generic_sync_fifo.vhd
vcom ../../../platform/altera/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem.vhd
vcom ../../../modules/wrsw_swcore/swc_page_alloc.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_page_allocator.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_linked_list.vhd
vcom ../../../modules/wrsw_swcore/swc_input_block.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_write_pump.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_input.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_output.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_pg_free_module.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
vcom ../../../modules/wrsw_swcore/swc_ob_prio_queue.vhd
vcom ../../../modules/wrsw_swcore/swc_output_block.vhd
vcom ../../../modules/wrsw_swcore/swc_core_single_port.vhd
vlog -sv swc_core_single_port.sv
vsim work.main -voptargs="+acc"
radix -hexadecimal
do wave.do
run 30us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_input_block.vhd
vlog -sv swc_input_block.sv
vsim work.main -voptargs="+acc"
radix -hexadecimal
do wave.do
run 3us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vcom ../../../modules/wrsw_swcore/swc_rr_arbiter.vhd
vcom ../../../modules/wrsw_swcore/swc_page_alloc.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_page_allocator.vhd
vlog swc_multiport_allocator_tb.v
vsim work.main
radix -hexadecimal
add wave \
{sim:/main/pgaddr_alloc } \
{sim:/main/done_alloc } \
{sim:/main/done_free } \
{sim:/main/done_force_free } \
{sim:/main/done_set_usecnt }
add wave \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/alloc_i } \
{sim:/main/DUT/free_i } \
{sim:/main/DUT/force_free_i } \
{sim:/main/DUT/set_usecnt_i } \
{sim:/main/DUT/alloc_done_o } \
{sim:/main/DUT/free_done_o } \
{sim:/main/DUT/force_free_done_o } \
{sim:/main/DUT/set_usecnt_done_o } \
{sim:/main/DUT/pgaddr_free_i } \
{sim:/main/DUT/usecnt_i } \
{sim:/main/DUT/pgaddr_alloc_o } \
{sim:/main/DUT/nomem_o } \
{sim:/main/DUT/pg_alloc } \
{sim:/main/DUT/pg_free } \
{sim:/main/DUT/pg_force_free } \
{sim:/main/DUT/pg_set_usecnt } \
{sim:/main/DUT/pg_usecnt } \
{sim:/main/DUT/pg_addr_alloc } \
{sim:/main/DUT/pg_addr_free } \
{sim:/main/DUT/pg_addr_valid } \
{sim:/main/DUT/pg_idle } \
{sim:/main/DUT/pg_done } \
{sim:/main/DUT/pg_nomem } \
{sim:/main/DUT/request_vec } \
{sim:/main/DUT/request_grant } \
{sim:/main/DUT/request_next } \
{sim:/main/DUT/request_grant_valid } \
{sim:/main/DUT/in_sel } \
{sim:/main/DUT/alloc_done_feedback } \
{sim:/main/DUT/alloc_done } \
{sim:/main/DUT/free_done_feedback } \
{sim:/main/DUT/free_done } \
{sim:/main/DUT/force_free_done_feedback } \
{sim:/main/DUT/force_free_done } \
{sim:/main/DUT/set_usecnt_done_feedback } \
{sim:/main/DUT/set_usecnt_done }
do wave.do
run 500us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vcom ../../../modules/wrsw_swcore/swc_rr_arbiter.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_linked_list.vhd
vlog swc_multiport_linked_list_tb.v
vsim work.main
radix -hexadecimal
do wave.do
add wave \
{sim:/main/done_write } \
{sim:/main/done_free } \
{sim:/main/done_free_pck } \
{sim:/main/done_read } \
{sim:/main/data_out }
add wave \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/write_i } \
{sim:/main/DUT/free_i } \
{sim:/main/DUT/read_pump_read_i } \
{sim:/main/DUT/free_pck_read_i } \
{sim:/main/DUT/write_done_o } \
{sim:/main/DUT/free_done_o } \
{sim:/main/DUT/read_pump_read_done_o } \
{sim:/main/DUT/free_pck_read_done_o } \
{sim:/main/DUT/read_pump_addr_i } \
{sim:/main/DUT/free_pck_addr_i } \
{sim:/main/DUT/write_addr_i } \
{sim:/main/DUT/free_addr_i } \
{sim:/main/DUT/write_data_i } \
{sim:/main/DUT/data_o } \
{sim:/main/DUT/ll_write_enable } \
{sim:/main/DUT/ll_write_addr } \
{sim:/main/DUT/ll_free_addr } \
{sim:/main/DUT/ll_wr_addr } \
{sim:/main/DUT/ll_rd_addr } \
{sim:/main/DUT/ll_write_data } \
{sim:/main/DUT/ll_wr_data } \
{sim:/main/DUT/ll_read_data } \
{sim:/main/DUT/write_request_vec } \
{sim:/main/DUT/read_request_vec } \
{sim:/main/DUT/write_request_grant } \
{sim:/main/DUT/read_request_grant } \
{sim:/main/DUT/write_request_grant_valid } \
{sim:/main/DUT/read_request_grant_valid } \
{sim:/main/DUT/in_sel_write } \
{sim:/main/DUT/in_sel_read } \
{sim:/main/DUT/write_done_feedback } \
{sim:/main/DUT/write_done } \
{sim:/main/DUT/free_done_feedback } \
{sim:/main/DUT/free_done } \
{sim:/main/DUT/read_pump_read_done_feedback } \
{sim:/main/DUT/read_pump_read_done } \
{sim:/main/DUT/free_pck_read_done_feedback } \
{sim:/main/DUT/free_pck_read_done }
run 500us
wave zoomfull
\ No newline at end of file
vlib work
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../platform/altera/generic_async_fifo_2stage.vhd
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vcom ../../../modules/wrsw_swcore/swc_rr_arbiter.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd
vlog swc_multiport_lost_pck_dealloc_tb.v
vsim work.main
radix -hexadecimal
do wave.do
add wave \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/ib_force_free_i } \
{sim:/main/DUT/ib_force_free_done_o } \
{sim:/main/DUT/ib_pgaddr_free_i } \
{sim:/main/DUT/ob_force_free_i } \
{sim:/main/DUT/ob_force_free_done_o } \
{sim:/main/DUT/ob_pgaddr_free_i } \
{sim:/main/DUT/request_grant } \
{sim:/main/DUT/request_grant_valid } \
{sim:/main/DUT/in_sel } \
{sim:/main/DUT/force_free_done_feedback } \
{sim:/main/DUT/force_free_done } \
{sim:/main/DUT/ib_force_free_done } \
{sim:/main/DUT/fifo_full } \
{sim:/main/DUT/pgaddr } \
{sim:/main/DUT/request } \
{sim:/main/DUT/pg_addr_free }
run 500us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_ob_prio_queue.vhd
vlog -sv swc_ob_prio_quque_tb.v
#vsim work.main
#radix -hexadecimal
#do wave.do
#add wave \
#{sim:/main/DUT/clk_i } \
#{sim:/main/DUT/rst_n_i } \
#{sim:/main/DUT/write_i } \
#{sim:/main/DUT/read_i } \
#{sim:/main/DUT/wr_en_o } \
#{sim:/main/DUT/wr_addr_o } \
#{sim:/main/DUT/rd_addr_o } \
#{sim:/main/DUT/head } \
#{sim:/main/DUT/tail } \
#{sim:/main/DUT/not_full } \
#{sim:/main/DUT/not_empty }
restart
run 15us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vcom ../../../modules/wrsw_swcore/swc_ob_prio_queue.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_output_block.vhd
vlog -sv swc_output_block_tb.v
vsim work.main
radix -hexadecimal
do wave.do
add wave \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/pta_transfer_data_valid_i } \
{sim:/main/DUT/pta_pageaddr_i } \
{sim:/main/DUT/pta_prio_i } \
{sim:/main/DUT/pta_pck_size_i } \
{sim:/main/DUT/pta_transfer_data_ack_o } \
{sim:/main/DUT/mpm_pgreq_o } \
{sim:/main/DUT/mpm_pgaddr_o } \
{sim:/main/DUT/mpm_pckend_i } \
{sim:/main/DUT/mpm_pgend_i } \
{sim:/main/DUT/mpm_drdy_i } \
{sim:/main/DUT/mpm_dreq_o } \
{sim:/main/DUT/mpm_data_i } \
{sim:/main/DUT/mpm_ctrl_i } \
{sim:/main/DUT/rx_sof_p1_o } \
{sim:/main/DUT/rx_eof_p1_o } \
{sim:/main/DUT/rx_dreq_i } \
{sim:/main/DUT/rx_ctrl_o } \
{sim:/main/DUT/rx_data_o } \
{sim:/main/DUT/rx_valid_o } \
{sim:/main/DUT/rx_bytesel_o } \
{sim:/main/DUT/rx_idle_o } \
{sim:/main/DUT/rx_rerror_p1_o } \
{sim:/main/DUT/wr_addr } \
{sim:/main/DUT/rd_addr } \
{sim:/main/DUT/wr_prio } \
{sim:/main/DUT/rd_prio } \
{sim:/main/DUT/not_full_array } \
{sim:/main/DUT/not_empty_array } \
{sim:/main/DUT/read_array } \
{sim:/main/DUT/read } \
{sim:/main/DUT/write_array } \
{sim:/main/DUT/write } \
{sim:/main/DUT/wr_en } \
{sim:/main/DUT/rd_data_valid } \
{sim:/main/DUT/zeros } \
{sim:/main/DUT/wr_array } \
{sim:/main/DUT/rd_array } \
{sim:/main/DUT/state } \
{sim:/main/DUT/pgreq } \
{sim:/main/DUT/wr_data } \
{sim:/main/DUT/rd_data } \
{sim:/main/DUT/rd_pck_size } \
{sim:/main/DUT/current_pck_size } \
{sim:/main/DUT/cnt_pck_size } \
{sim:/main/DUT/rx_sof_p1 } \
{sim:/main/DUT/rx_eof_p1 } \
{sim:/main/DUT/rx_valid }
run 1us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_multiport_linked_list.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_write_pump.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem.vhd
vlog -sv swc_packet_mem_tb.v
vsim work.main
radix -hexadecimal
do wave.do
run 15us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vcom ../../../modules/wrsw_swcore/swc_page_alloc.vhd
vlog swc_page_alloc_tb.v
vsim work.main
radix -hexadecimal
do wave.do
add wave \
{sim:/main/idle } \
{sim:/main/nomem } \
{sim:/main/pgaddr_o } \
{sim:/main/pgaddr_valid }
add wave \
{sim:/main/dut/g_num_pages } \
{sim:/main/dut/g_page_addr_bits } \
{sim:/main/dut/g_use_count_bits } \
{sim:/main/dut/clk_i } \
{sim:/main/dut/rst_n_i } \
{sim:/main/dut/alloc_i } \
{sim:/main/dut/free_i } \
{sim:/main/dut/force_free_i } \
{sim:/main/dut/set_usecnt_i } \
{sim:/main/dut/usecnt_i } \
{sim:/main/dut/pgaddr_i } \
{sim:/main/dut/pgaddr_o } \
{sim:/main/dut/pgaddr_valid_o } \
{sim:/main/dut/idle_o } \
{sim:/main/dut/done_o } \
{sim:/main/dut/nomem_o } \
{sim:/main/dut/l1_bitmap } \
{sim:/main/dut/l1_first_free } \
{sim:/main/dut/l1_mask } \
{sim:/main/dut/l0_mask } \
{sim:/main/dut/l0_first_free } \
{sim:/main/dut/state } \
{sim:/main/dut/free_blocks } \
{sim:/main/dut/l0_wr_data } \
{sim:/main/dut/l0_rd_data } \
{sim:/main/dut/l0_wr_addr } \
{sim:/main/dut/l0_rd_addr } \
{sim:/main/dut/l0_wr } \
{sim:/main/dut/usecnt_mem_wraddr } \
{sim:/main/dut/usecnt_mem_rdaddr } \
{sim:/main/dut/usecnt_mem_wr } \
{sim:/main/dut/usecnt_mem_rddata } \
{sim:/main/dut/usecnt_mem_wrdata }
run 400us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_input.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_output.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
vlog -sv swc_pck_transfer_arbiter_tb.v
vsim work.main
radix -hexadecimal
do wave.do
add wave \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/ob_data_valid_o } \
{sim:/main/DUT/ob_ack_i } \
{sim:/main/DUT/ob_pageaddr_o } \
{sim:/main/DUT/ob_prio_o } \
{sim:/main/DUT/ib_transfer_pck_i } \
{sim:/main/DUT/ib_transfer_ack_o } \
{sim:/main/ib_busy } \
{sim:/main/DUT/ib_busy_o } \
{sim:/main/DUT/ib_pageaddr_i } \
{sim:/main/DUT/ib_mask_i } \
{sim:/main/DUT/ib_prio_i } \
{sim:/main/DUT/pto_pageaddr } \
{sim:/main/DUT/pto_output_mask } \
{sim:/main/DUT/pto_read_mask } \
{sim:/main/DUT/pto_prio } \
{sim:/main/DUT/pti_transfer_data_ack } \
{sim:/main/DUT/pti_transfer_data_valid } \
{sim:/main/DUT/pti_pageaddr } \
{sim:/main/DUT/pti_prio } \
{sim:/main/DUT/sync_sreg } \
{sim:/main/DUT/sync_cntr } \
{sim:/main/DUT/sync_cntr_ack }
add wave \
{sim:/main/DUT/gen_output(0)/transfer_output/ob_pageaddr_o } \
{sim:/main/DUT/gen_output(0)/transfer_output/ob_prio_o } \
{sim:/main/DUT/gen_output(0)/transfer_output/pti_pageaddr_i } \
{sim:/main/DUT/gen_output(0)/transfer_output/pti_prio_i } \
{sim:/main/DUT/gen_output(0)/transfer_output/pti_transfer_data_ack } \
{sim:/main/DUT/gen_output(0)/transfer_output/ob_transfer_data_valid } \
{sim:/main/DUT/gen_output(0)/transfer_output/ob_pageaddr } \
{sim:/main/DUT/gen_output(0)/transfer_output/ob_prio }
add wave \
{sim:/main/DUT/gen_input(0)/transfer_input/pto_pageaddr_o } \
{sim:/main/DUT/gen_input(0)/transfer_input/pto_output_mask_o } \
{sim:/main/DUT/gen_input(0)/transfer_input/pto_prio_o } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_pageaddr_i } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_mask_i } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_prio_i } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_transfer_ack } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_pageaddr } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_prio } \
{sim:/main/DUT/gen_input(0)/transfer_input/ib_mask } \
{sim:/main/DUT/gen_input(0)/transfer_input/pto_output_mask } \
{sim:/main/DUT/gen_input(0)/transfer_input/zeros }
add wave \
{sim:/main/DUT/gen_input(1)/transfer_input/pto_transfer_pck_o } \
{sim:/main/DUT/gen_input(1)/transfer_input/pto_pageaddr_o } \
{sim:/main/DUT/gen_input(1)/transfer_input/pto_output_mask_o } \
{sim:/main/DUT/gen_input(1)/transfer_input/pto_prio_o } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_pageaddr_i } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_mask_i } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_prio_i } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_transfer_ack } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_pageaddr } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_prio } \
{sim:/main/DUT/gen_input(1)/transfer_input/ib_mask } \
{sim:/main/DUT/gen_input(1)/transfer_input/pto_output_mask } \
{sim:/main/DUT/gen_input(1)/transfer_input/zeros }
add wave \
{sim:/main/DUT/gen_output(1)/transfer_output/ob_pageaddr_o } \
{sim:/main/DUT/gen_output(1)/transfer_output/ob_prio_o } \
{sim:/main/DUT/gen_output(1)/transfer_output/pti_pageaddr_i } \
{sim:/main/DUT/gen_output(1)/transfer_output/pti_prio_i } \
{sim:/main/DUT/gen_output(1)/transfer_output/pti_transfer_data_ack } \
{sim:/main/DUT/gen_output(1)/transfer_output/ob_transfer_data_valid } \
{sim:/main/DUT/gen_output(1)/transfer_output/ob_pageaddr } \
{sim:/main/DUT/gen_output(1)/transfer_output/ob_prio }
add wave \
{sim:/main/DUT/gen_output(2)/transfer_output/ob_pageaddr_o } \
{sim:/main/DUT/gen_output(2)/transfer_output/ob_prio_o } \
{sim:/main/DUT/gen_output(2)/transfer_output/pti_pageaddr_i } \
{sim:/main/DUT/gen_output(2)/transfer_output/pti_prio_i } \
{sim:/main/DUT/gen_output(2)/transfer_output/pti_transfer_data_ack } \
{sim:/main/DUT/gen_output(2)/transfer_output/ob_transfer_data_valid } \
{sim:/main/DUT/gen_output(2)/transfer_output/ob_pageaddr } \
{sim:/main/DUT/gen_output(2)/transfer_output/ob_prio }
add wave \
{sim:/main/DUT/gen_output(3)/transfer_output/ob_pageaddr_o } \
{sim:/main/DUT/gen_output(3)/transfer_output/ob_prio_o } \
{sim:/main/DUT/gen_output(3)/transfer_output/pti_pageaddr_i } \
{sim:/main/DUT/gen_output(3)/transfer_output/pti_prio_i } \
{sim:/main/DUT/gen_output(3)/transfer_output/pti_transfer_data_ack } \
{sim:/main/DUT/gen_output(3)/transfer_output/ob_transfer_data_valid } \
{sim:/main/DUT/gen_output(3)/transfer_output/ob_pageaddr } \
{sim:/main/DUT/gen_output(3)/transfer_output/ob_prio }
run 1500ns
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_pck_transfer_input.vhd
vlog -sv swc_pck_transfer_input_tb.v
vsim work.main
radix -hexadecimal
do wave.do
add wave \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/pto_transfer_pck_o } \
{sim:/main/DUT/pto_pageaddr_o } \
{sim:/main/DUT/pto_output_mask_o } \
{sim:/main/DUT/pto_read_mask_i } \
{sim:/main/DUT/pto_prio_o } \
{sim:/main/DUT/ib_transfer_pck_i } \
{sim:/main/DUT/ib_pageaddr_i } \
{sim:/main/DUT/ib_mask_i } \
{sim:/main/DUT/ib_prio_i } \
{sim:/main/DUT/ib_transfer_ack_o } \
{sim:/main/DUT/ib_transfer_ack } \
{sim:/main/DUT/ib_pageaddr } \
{sim:/main/DUT/ib_prio } \
{sim:/main/DUT/ib_mask } \
{sim:/main/DUT/pto_read_mask } \
{sim:/main/DUT/pto_output_mask } \
{sim:/main/DUT/zeros }
run 15us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vlog swc_prio_encoder_tb.v
vsim work.main
radix -hexadecimal
do wave.do
run 100us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
vlog swc_read_pump_tb.sv
vsim work.main
radix -hexadecimal
add wave \
{sim:/main/clk } \
{sim:/main/rst } \
{sim:/main/page_addr } \
{sim:/main/page_req } \
{sim:/main/pgend } \
{sim:/main/drdy } \
{sim:/main/dreq } \
{sim:/main/sync } \
{sim:/main/addr } \
{sim:/main/d } \
{sim:/main/q } \
{sim:/main/pckend } \
{sim:/main/current_page_addr } \
{sim:/main/next_page_addr } \
{sim:/main/read_req } \
{sim:/main/read_data_valid }
add wave \
{sim:/main/DUT/clk_i } \
{sim:/main/DUT/rst_n_i } \
{sim:/main/DUT/pgreq_i } \
{sim:/main/DUT/pgaddr_i } \
{sim:/main/DUT/pckend_o } \
{sim:/main/DUT/pgend_o } \
{sim:/main/DUT/drdy_o } \
{sim:/main/DUT/dreq_i } \
{sim:/main/DUT/sync_read_i } \
{sim:/main/DUT/ll_read_addr_o } \
{sim:/main/DUT/ll_read_data_i } \
{sim:/main/DUT/ll_read_req_o } \
{sim:/main/DUT/ll_read_valid_data_i } \
{sim:/main/DUT/d_o } \
{sim:/main/DUT/sync_i } \
{sim:/main/DUT/addr_o } \
{sim:/main/DUT/q_i } \
{sim:/main/DUT/out_reg } \
{sim:/main/DUT/cntr } \
{sim:/main/DUT/sync_d0 } \
{sim:/main/DUT/sync_d1 } \
{sim:/main/DUT/reg_not_empty } \
{sim:/main/DUT/cntr_full } \
{sim:/main/DUT/mem_addr } \
{sim:/main/DUT/allones } \
{sim:/main/DUT/zeros } \
{sim:/main/DUT/advance_addr } \
{sim:/main/DUT/load_out_reg } \
{sim:/main/DUT/pgend } \
{sim:/main/DUT/pckend } \
{sim:/main/DUT/current_page_addr } \
{sim:/main/DUT/next_page_addr }
do wave.do
run 3us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_prio_encoder.vhd
vcom ../../../modules/wrsw_swcore/swc_rr_arbiter.vhd
vlog swc_rr_arbiter_tb.v
vsim work.main
radix -hexadecimal
add wave \
{sim:/main/next } \
{sim:/main/grant } \
{sim:/main/grant_valid }
add wave \
{sim:/main/dut/g_num_ports } \
{sim:/main/dut/g_num_ports_log2 } \
{sim:/main/dut/rst_n_i } \
{sim:/main/dut/clk_i } \
{sim:/main/dut/next_i } \
{sim:/main/dut/request_i } \
{sim:/main/dut/grant_o } \
{sim:/main/dut/grant_valid_o } \
{sim:/main/dut/request_mask } \
{sim:/main/dut/request_vec_masked } \
{sim:/main/dut/rq_decoded } \
{sim:/main/dut/rq_decoded_mask } \
{sim:/main/dut/rq_zero } \
{sim:/main/dut/rq_wait_next }
do wave.do
run 1us
wave zoomfull
vlib work
vcom ../../../modules/wrsw_swcore/platform_specific.vhd
vcom ../../../modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd
vcom ../../../modules/wrsw_swcore/swc_swcore_pkg.vhd
vcom ../../../modules/wrsw_swcore/swc_packet_mem_write_pump.vhd
vlog swc_write_pump_tb.v
vsim work.main
radix -hexadecimal
do wave.do
run 30us
wave zoomfull
#include <stdio.h>
#define NUM_PAGES 2048
#define BITMAP_SIZE 2048/32
int use_count[NUM_PAGES];
int l0_bitmap[BITMAP_SIZE];
int l1_bitmap[BITMAP_SIZE];
int free_pages = NUM_PAGES;
int prio_enc(int *p, int count) {
int i;
for(i=0;i<count;i++)
if(p[i]) return i;
return -1;
}
int prio_enc_bin(int val, int bit_count) {
int i;
for(i=0;i<bit_count;i++)
if(val & (1<<i)) return i;
return -1;
}
int alloc_page(int ucnt)
{
if(!free_pages) return -1;
int l1_lookup = prio_enc(l1_bitmap, BITMAP_SIZE);
int l0_lookup = prio_enc_bin(l0_bitmap[l1_lookup], 32);
int newval = l0_bitmap[l1_lookup];
int pageaddr = l1_lookup * 32 + l0_lookup;
newval ^= (1<< l0_lookup); // clear the free page
l0_bitmap[l1_lookup] = newval;
if(!newval)
l1_bitmap[l1_lookup] = 0;
use_count[pageaddr] = ucnt;
printf("pageaddr: %d\n", pageaddr);
}
int free_page(int pageaddr)
{
if(use_count[pageaddr] > 1) {
use_count[pageaddr]--;
} else {
l0_bitmap[pageaddr >> 5] ^= (1 << (pageaddr & 0x1f));
l1_bitmap[pageaddr >> 5] = 1;
free_pages ++;
}
}
int alloc_init()
{
int i, j;
free_pages = NUM_PAGES;
for(i = 0; i< BITMAP_SIZE;i++)
{
l1_bitmap[i] = 1;
l0_bitmap[i] = 0xffffffff;
}
}
main()
{
alloc_init();
int i;
for (i=0;i<100;i++) alloc_page(1);
free_page(50);
alloc_page(1);
}
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
`timescale 1ns / 1ps
`define INPUT_SIZE 36
`define OUTPUT_BITS 6
module main;
reg [`INPUT_SIZE-1:0] a = 0;
wire [`OUTPUT_BITS-1:0] q ;
integer i, j;
integer fail = 0;
swc_prio_encoder #(
.g_num_inputs(`INPUT_SIZE),
.g_output_bits(`OUTPUT_BITS))
dut (
.in_i(a),
.out_o(q)
);
initial begin
for(i=0;i<`INPUT_SIZE;i=i+1) begin
a[i] = 1'b1;
if(i>0) for (j=0;j<=i-1;j=j+1) a[j] = 1'b0;
if(i<`INPUT_SIZE-1) for(j=i+1; j<`INPUT_SIZE; j=j+1) a[j] = $random;
#200;
if(i!=q) begin
$display(i,"!=",q);
fail = 1;
end
end
if(!fail)
$display("test passed");
else
$display("test failed");
end
endmodule // main
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment