Added compilation howto

b22883d8 · Tomasz Wlostowski · 853d25d8 · b22883d8
Commit b22883d8 authored Jul 30, 2012 by Tomasz Wlostowski
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+Building the WR Switch gateware
+-------------------------------
+
+Disclaimer: this readme assumes that you know the basic UNIX commands.
+						Otherwise, we recommend downloading the FPGA binaries from 
+            the 'Files' section of WR Switch HDL project.
+
+1. Environment setup:
+  1a. Make sure you have git & make installed.
+  1b. Make sure you have Xilinx ISE installed (64-bit version ONLY, version 14.1 or above). 
+  1c. Check ISE-related environment variables:
+    - Xilinx binaries (xst, map, par) must be in PATH environmental variable.
+    - XILINX environmental variable must be correctly set (for example: 
+      XILINX=/opt/Xilinx/14.1/ISE_DS for ISE suite installed in /opt/Xilinx)
+
+2. Install and build hdlmake ("isyp" branch)
+  2a. Download the sources and build hdlmake
+    $ git clone git://ohwr.org/misc/hdl-make.git
+    $ cd hdl-make
+    $ git checkout isyp
+    $ make
+  2b. Put hdlmake in a directory listed in PATH, for example:
+    $ sudo ln -sf `readlink -f hdlmake` /usr/bin/hdlmake
+
+3. Download WR Switch HDL sources
+  $ git clone --recursive git://ohwr.org/white-rabbit/wr-switch-hdl.git
+  $ cd wr-switch-hdl
+  $ git checkout wr-switch-sw-v3.0
+  $ git submodule update
+
+4. Build it
+  4a. Generate the Makefiles
+    $ cd syn/scb_18ports
+    $ hdlmake --ise-proj --make-ise
+  4b. Synthesize:
+    $ make
+
+5. Deploy the firmware
+  Copy the freshly build firmware to the switch filesystem:
+  scp scb_top_synthesis.bin root@<your_switch_ip_address>:/wr/lib/firmware/18ports_mb.bin.
+  Reboot the switch.
+
+6. Good luck!
+
+Frequently Asked Questions
+--------------------------
+
+Q: I'm getting PAR timing errors!
+A: If only this constraint is failing:
+   NET "clk_dmtd" MAXSKEW = 0.5 ns
+   It's acceptable (I used ridiculously low skew value to force PAR to put more effort on routing this signal).
+   For reasons yet unknown, ISE refuses to route this signal on a global clock net, resulting in larger skew.
+   Fortunately, the skew on clk_dmtd net is equal to port-to-port clock offset, which can be 
+   measured on a scope and compensated in delta_tx/delta_rx parameters in wrsw_hal.conf.
+
+Q: It takes so long to synthesize!
+A: The synthesis takes approx 2 hours on a Core i7-980x machine. If you don't need all 18 ports, you can
+   synthesize scb_8ports project instead (~30 mins on the same PC)
+
+Q: ISE appears to have frozen during MAP/PAR!
+A: Did you install a 64-bit version of ISE? It needs up to 4 GB of free RAM during mapping/routing the design.
+   32-bit version can't use more than 3 GBs and sometimes freezes instead of throwing an error.
+   
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