swcore: multiport LL, use 3 write ports

babcf5c0 · Grzegorz Daniluk · ce4988d9 · babcf5c0
Commit babcf5c0 authored Sep 12, 2016 by Grzegorz Daniluk
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swc_multiport_linked_list.vhd modules/wrsw_swcore/swc_multiport_linked_list.vhd +4 -3

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--- a/modules/wrsw_swcore/swc_multiport_linked_list.vhd
+++ b/modules/wrsw_swcore/swc_multiport_linked_list.vhd
@@ -118,7 +118,7 @@ end swc_multiport_linked_list;

 architecture syn of swc_multiport_linked_list is

-  constant c_MPRAM_WPORTS : integer := 2;
+  constant c_MPRAM_WPORTS : integer := 3;
  constant c_MPRAM_RPORTS : integer := 2;

  component mpram_lvt
@@ -303,8 +303,9 @@ begin
  -- we split IBs into write ports
  -- IB port ranges for each write port are hardcoded to have similar
  -- performance (IBs-per-write port) for 8 and 18 port version.
-  write_i_split(0) <= ll_split_writes(write_i, g_num_ports, 8, 0);
-  write_i_split(1) <= ll_split_writes(write_i, g_num_ports, g_num_ports-1, 9);
+  write_i_split(0) <= ll_split_writes(write_i, g_num_ports, 5, 0);
+  write_i_split(1) <= ll_split_writes(write_i, g_num_ports, 11, 6);
+  write_i_split(2) <= ll_split_writes(write_i, g_num_ports, g_num_ports-1, 12);

  -- combine together write_done signals from multiple MPRAM write ports
  write_done_ored(0) <= x_mpram_wdone(0);