Commit bbe909f5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk

top/scb_8ports: 8-port PoC firmware with deterministic V6 transceiver config

parent 93a74f10
......@@ -153,10 +153,11 @@ NET "clk_en_o" LOC="AD16";
NET "clk_sel_o" LOC="AK17";
### GTX PORTS - reversed to match MB port ordering ###
#NET "gtx0_3_clk_n_i" LOC="AK5";
#NET "gtx0_3_clk_p_i" LOC="AK6";
#NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx0_3_clk_n_i" LOC="AK5";
NET "gtx0_3_clk_p_i" LOC="AK6";
NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_n_i" LOC="AD5";
#NET "gtx4_7_clk_p_i" LOC="AD6";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
......@@ -180,10 +181,11 @@ NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[0]" LOC="AP6";
#NET "gtx_txp_o[0]" LOC="AP1";
#NET "gtx_txn_o[0]" LOC="AP2";
NET "gtx_rxp_i[7]" LOC="AP5"; # gtx0
NET "gtx_rxn_i[7]" LOC="AP6";
NET "gtx_txp_o[7]" LOC="AP1";
NET "gtx_txn_o[7]" LOC="AP2";
#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[1]" LOC="AM6";
#NET "gtx_txp_o[1]" LOC="AN3";
......@@ -220,11 +222,12 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxn_i[9]" LOC="W4";
#NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2";
NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4";
NET "gtx_txp_o[7]" LOC="T1";
NET "gtx_txn_o[7]" LOC="T2";
#NET "gtx_rxp_i[7]" LOC="U3";
#NET "gtx_rxn_i[7]" LOC="U4";
#NET "gtx_txp_o[7]" LOC="T1";
#NET "gtx_txn_o[7]" LOC="T2";
NET "gtx_rxp_i[6]" LOC="R3";
NET "gtx_rxn_i[6]" LOC="R4";
......@@ -398,3 +401,24 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
PIN "gen_phys_bufr[0].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys_bufr[1].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys_bufr[2].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys_bufr[3].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys[4].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys[5].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys[6].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_LastPHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
NET "dbg_samp_rx_p_i" LOC="AM33";
NET "dbg_samp_rx_n_i" LOC="AL33";
NET "dbg_samp_tx_p_i" LOC="AE28";
NET "dbg_samp_tx_n_i" LOC="AE29";
NET "dbg_dmtd_tx_clean_o" LOC="AN32";
NET "dbg_dmtd_rx_clean_o" LOC="AM32";
NET "dbg_dmtd_tx_raw_o" LOC="AP32";
NET "dbg_dmtd_rx_raw_o" LOC="AP33";
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2014-03-20
-- Last update: 2018-06-15
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -173,11 +173,11 @@ entity scb_top_synthesis is
-- GTX ports
---------------------------------------------------------------------------
--gtx0_3_clk_n_i : in std_logic;
--gtx0_3_clk_p_i : in std_logic;
gtx0_3_clk_n_i : in std_logic;
gtx0_3_clk_p_i : in std_logic;
--gtx4_7_clk_n_i : in std_logic;
--gtx4_7_clk_p_i : in std_logic;
-- gtx4_7_clk_n_i : in std_logic;
-- gtx4_7_clk_p_i : in std_logic;
gtx8_11_clk_n_i : in std_logic;
gtx8_11_clk_p_i : in std_logic;
......@@ -213,7 +213,21 @@ entity scb_top_synthesis is
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic
mb_fan2_pwm_o : out std_logic;
dbg_samp_rx_p_i : in std_logic;
dbg_samp_rx_n_i : in std_logic;
dbg_samp_tx_p_i : in std_logic;
dbg_samp_tx_n_i : in std_logic;
-- dbg_dmtd_rx_o : out std_logic;
-- dbg_dmtd_tx_o : out std_logic;
-- dbg_dmtd_tx_mask_o : out std_logic;
-- dbg_dmtd_rx_mask_o : out std_logic;
dbg_dmtd_tx_clean_o : out std_logic;
dbg_dmtd_rx_clean_o : out std_logic;
dbg_dmtd_tx_raw_o : out std_logic;
dbg_dmtd_rx_raw_o : out std_logic
);
end scb_top_synthesis;
......@@ -260,6 +274,7 @@ architecture Behavioral of scb_top_synthesis is
end f_bool2int;
-------------------------------------------------------------------------------
-- Clocks
-------------------------------------------------------------------------------
......@@ -437,51 +452,21 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal phy_rx_clk_vec: std_logic_vector(7 downto 0);
signal dbg_samp_tx, dbg_samp_rx : std_logic;
begin
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_25mhz,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--TRIG0(0) <= mbl_scl_b(0);
--TRIG0(1) <= mbl_sda_b(0);
--TRIG0(2) <= mbl_scl_b(1);
--TRIG0(3) <= mbl_sda_b(1);
--TRIG1 <= cpu_data_b;
--TRIG2(0) <= cpu_cs_n_i;
--TRIG2(1) <= cpu_rd_n_i;
--TRIG2(2) <= cpu_wr_n_i;
--TRIG2(3) <= sys_rst_n_i;
--U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx0_3,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx0_3_clk_p_i,
-- IB => gtx0_3_clk_n_i
-- );
--U_Clk_Buf_GTX4_7 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx4_7,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx4_7_clk_p_i,
-- IB => gtx4_7_clk_n_i
-- );
U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
port map
(
O => clk_gtx0_3,
ODIV2 => open,
CEB => '0',
I => gtx0_3_clk_p_i,
IB => gtx0_3_clk_n_i
);
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map
......@@ -531,6 +516,24 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_Ref2 : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => dbg_samp_tx,
I => dbg_samp_tx_p_i,
IB => dbg_samp_tx_n_i);
U_Buf_CLK_Ref3 : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => dbg_samp_rx,
I => dbg_samp_rx_p_i,
IB => dbg_samp_rx_n_i);
U_Buf_ljd_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
......@@ -722,21 +725,26 @@ begin
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => true)
g_use_bufr => false)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_rbclk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
debug_o => from_phys(i).debug,
debug_i => to_phys(i).debug,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
......@@ -747,7 +755,7 @@ begin
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-1 generate
gen_phys : for i in 4 to c_NUM_PHYS-2 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
......@@ -757,18 +765,22 @@ begin
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_rbclk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
debug_o => from_phys(i).debug,
debug_i => to_phys(i).debug,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
......@@ -778,6 +790,42 @@ begin
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
U_LastPHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => 0,
g_use_bufr => false)
port map (
clk_gtx_i => clk_gtx0_3,
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(c_NUM_PHYS-1).tx_data,
tx_k_i => to_phys(c_NUM_PHYS-1).tx_k,
tx_disparity_o => from_phys(c_NUM_PHYS-1).tx_disparity,
tx_enc_err_o => from_phys(c_NUM_PHYS-1).tx_enc_err,
rx_rbclk_o => from_phys(c_NUM_PHYS-1).rx_clk,
rx_rbclk_sampled_o =>from_phys(c_NUM_PHYS-1).rx_sampled_clk,
rx_data_o => from_phys(c_NUM_PHYS-1).rx_data,
rx_k_o => from_phys(c_NUM_PHYS-1).rx_k,
rx_enc_err_o => from_phys(c_NUM_PHYS-1).rx_enc_err,
rx_bitslide_o => from_phys(c_NUM_PHYS-1).rx_bitslide,
rst_i => to_phys(c_NUM_PHYS-1).rst,
loopen_i => to_phys(c_NUM_PHYS-1).loopen,
debug_o => from_phys(c_NUM_PHYS-1).debug,
debug_i => to_phys(c_NUM_PHYS-1).debug,
pad_txn_o => gtx_txn_o(7),
pad_txp_o => gtx_txp_o(7),
pad_rxn_i => gtx_rxn_i(7),
pad_rxp_i => gtx_rxp_i(7),
rdy_o => from_phys(c_NUM_PHYS-1).rdy,
tx_sampled_i => dbg_samp_tx,
rx_sampled_i => dbg_samp_rx
);
from_phys(c_NUM_PHYS-1).ref_clk <= clk_ref;
gen_terminate_unused_phys : for i in c_NUM_PORTS to c_NUM_PHYS-1 generate
to_phys(i).tx_data <= (others => '0');
to_phys(i).tx_k <= (others => '0');
......@@ -796,13 +844,13 @@ begin
generic map (
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
g_without_network => false,
g_without_network => true,
g_with_TRU => false,
g_with_TATSU => false,
g_with_HWIU => true,
g_with_PSTATS => true,
g_with_HWIU => false,
g_with_PSTATS => false,
g_with_muxed_CS => false,
g_with_watchdog => true,
g_with_watchdog => false,
g_inj_per_EP => "00" & x"0000"
)
port map (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment