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White Rabbit Switch - Gateware
Commit be2ea7f5 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'wrs-pts-v1.0' into proposed_master

parents d2c67ba6 fbf07e05
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syn/pts_scb/Manifest.py 0 → 100644
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target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_tool = "ise"
top_module = "pts_scb_top"
syn_device = "xc6vlx240t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "pts_scb_top"
syn_project = "pts_scb.xise"
modules = { "local" : [ "../../top/pts_scb",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores" ] }
syn/pts_scb/pts_scb.xise 0 → 100644
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top/pts_scb/Manifest.py 0 → 100644
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files = [
"pts_scb_top.ucf",
"pts_scb_top.vhd",
"swcore_pll.vhd",
"pts_scb_top_bare.vhd",
"pts_wb_cpu_bridge.vhd",
#"wb_cpu_bridge.vhd",
"scb_top_sim.vhd",
"wrsw_top_pkg.vhd",
"wrs_sdb_pkg.vhd",
"synthesis_descriptor.vhd",
"xwrsw_syst_mon.vhd",
"syst_mon.vhd",
"xwrsw_sandbox.vhd",
"freq_wbgen2_pkg.vhd",
"wb_freq_regs.vhd",
"xwrsw_freq_measure.vhd"
];
modules = { "local" : [ "../../" ] };
top/pts_scb/freq_wbgen2_pkg.vhd 0 → 100644
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS Frequency Measurement Result Registers
---------------------------------------------------------------------------------------
-- File : freq_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_freq_regs.wb
-- Created : Wed Feb 15 11:13:39 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_freq_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package freq_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_freq_in_registers is record
f_dmtd_clk_freq_i : std_logic_vector(27 downto 0);
f_clk10mhz_ext_freq_i : std_logic_vector(27 downto 0);
f_fpga_main_clk_freq_i : std_logic_vector(27 downto 0);
f_aux_clk_freq_i : std_logic_vector(27 downto 0);
f_serdes_clk_freq_i : std_logic_vector(27 downto 0);
f_ref_clk_freq_i : std_logic_vector(27 downto 0);
end record;
constant c_freq_in_registers_init_value: t_freq_in_registers := (
f_dmtd_clk_freq_i => (others => '0'),
f_clk10mhz_ext_freq_i => (others => '0'),
f_fpga_main_clk_freq_i => (others => '0'),
f_aux_clk_freq_i => (others => '0'),
f_serdes_clk_freq_i => (others => '0'),
f_ref_clk_freq_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_freq_out_registers is record
dummy : std_logic;
end record;
constant c_freq_out_registers_init_value: t_freq_out_registers := (
dummy => '0'
);
function "or" (left, right: t_freq_in_registers) return t_freq_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body freq_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_freq_in_registers) return t_freq_in_registers is
variable tmp: t_freq_in_registers;
begin
tmp.f_dmtd_clk_freq_i := f_x_to_zero(left.f_dmtd_clk_freq_i) or f_x_to_zero(right.f_dmtd_clk_freq_i);
tmp.f_clk10mhz_ext_freq_i := f_x_to_zero(left.f_clk10mhz_ext_freq_i) or f_x_to_zero(right.f_clk10mhz_ext_freq_i);
tmp.f_fpga_main_clk_freq_i := f_x_to_zero(left.f_fpga_main_clk_freq_i) or f_x_to_zero(right.f_fpga_main_clk_freq_i);
tmp.f_aux_clk_freq_i := f_x_to_zero(left.f_aux_clk_freq_i) or f_x_to_zero(right.f_aux_clk_freq_i);
tmp.f_serdes_clk_freq_i := f_x_to_zero(left.f_serdes_clk_freq_i) or f_x_to_zero(right.f_serdes_clk_freq_i);
tmp.f_ref_clk_freq_i := f_x_to_zero(left.f_ref_clk_freq_i) or f_x_to_zero(right.f_ref_clk_freq_i);
return tmp;
end function;
end package body;
top/pts_scb/gen_sdbsyn.py 0 → 100644
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#!/usr/bin/python
##-----------------------------------------------------------------------------
## Title : SDB Synthesis info autogen
## Project : White Rabbit Switch
##-----------------------------------------------------------------------------
## File : gen_sdbsyn.py
## Author : Grzegorz Daniluk
## Company : CERN BE-CO-HT
## Created : 2014-09-17
## Last update: 2014-09-17
## Platform : FPGA-generic
## Standard : VHDL
##-----------------------------------------------------------------------------
## Description:
## Script for auto-generation of VHDL package with t_sdb_synthesis and
## t_sdb_repo_url info. Should be called every time before the synthesis is done
##-----------------------------------------------------------------------------
##
## Copyright (c) 2014 CERN / BE-CO-HT
##
## This source file is free software; you can redistribute it
## and/or modify it under the terms of the GNU Lesser General
## Public License as published by the Free Software Foundation;
## either version 2.1 of the License, or (at your option) any
## later version.
##
## This source is distributed in the hope that it will be
## useful, but WITHOUT ANY WARRANTY; without even the implied
## warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
## PURPOSE. See the GNU Lesser General Public License for more
## details.
##
## You should have received a copy of the GNU Lesser General
## Public License along with this source; if not, download it
## from http://www.gnu.org/licenses/lgpl-2.1.html
##
##-----------------------------------------------------------------------------
import sys
import argparse
import subprocess
import datetime
#MODULE_NAME = "WRS 8p"
#TOOL_NAME = "ISE"
#TOOL_VERSION = "14.5"
PKG_FILE = "synthesis_descriptor.vhd"
PKG_HEADER = """-- package generated automatically by gen_sdbsyn.py script --
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is\n"""
PKG_TAIL = "\nend package;";
REPO_URL = "constant c_sdb_repo_url : t_sdb_repo_url := (\n"
MAIN_SYN = "top"
# from t_sdb_synthesis record
SDB_URL = "repo_url"
URL_LEN = 63
NAME_LEN = 16
COMMIT_LEN = 32
TOOL_LEN = 8
USER_LEN = 15
# git commands
GIT_DIRTY = "git describe --always --dirty=+"
# write t_sdb_synthesis record to opened file
def write_sdb_info(f, r_name, m_name, commit, dirty, tool, toolv, date, user):
# mark dirty if necessary
if len(m_name)<NAME_LEN and dirty:
m_name = m_name + '+'
elif len(m_name)>=NAME_LEN and dirty:
m_name = m_name[:NAME_LEN-1] + '+'
f.write("constant c_sdb_" + r_name.replace("-", "_") + "_syn_info : t_sdb_synthesis := (\n")
f.write("syn_module_name => \"" + m_name[:NAME_LEN].ljust(NAME_LEN) + "\",\n")
f.write("syn_commit_id => \"" + commit.ljust(COMMIT_LEN) + "\",\n")
f.write("syn_tool_name => \"" + tool[:TOOL_LEN].ljust(TOOL_LEN) + "\",\n")
f.write("syn_tool_version => x\""+ hex(toolv)[2:].zfill(8) + "\",\n")
f.write("syn_date => x\"" + hex(date)[2:].zfill(8) + "\",\n")
f.write("syn_username => \"" + user[:USER_LEN].ljust(USER_LEN) + "\");\n")
def git_username():
# gets username from git config
temp = subprocess.Popen("git config user.name", stdout=subprocess.PIPE, shell=True)
user = temp.stdout.read().split()
if len(user) == 1:
#is a single word, so we just use it
return user[0]
#otherwise use initials with last name
uname = ""
for n in user[:-1]:
uname = uname + n[0]
if len(user):
uname = uname + user[-1]
return uname
def main():
### runtime arguments
parser = argparse.ArgumentParser(description='Script for generating sdb metadata of HDL projects')
parser.add_argument('--user', default=git_username(), help='User who makes the synthesis')
parser.add_argument('--project', default="", required=True, help='Friendly project name')
parser.add_argument('--tool', default="ISE", help='Name of the synthesis tool')
parser.add_argument('--ver', default="14.5", help='Synthesis tool version')
parser.add_argument('-o', default=".", help='location of output file')
args = parser.parse_args()
if args.o[-1]!='/':
args.o = args.o + '/'
#######
temp = subprocess.Popen("git rev-parse --show-toplevel", stdout=subprocess.PIPE, shell=True)
toplevel = temp.stdout.read()[0:-1] #remove trailing \n
f = open(args.o + PKG_FILE, 'w')
f.write(PKG_HEADER)
### Make the first constant which is repo url
f.write(REPO_URL)
temp = subprocess.Popen("git config remote.origin.url", stdout=subprocess.PIPE, shell=True)
url = temp.stdout.read()[0:-1]
f.write(SDB_URL + " => \"" + url[:URL_LEN].ljust(URL_LEN) + "\");\n") #truncate or expand string
### Now generate synthesis info for main repository
# get commit id
temp = subprocess.Popen("git log --always --pretty=format:'%H' -n 1", stdout=subprocess.PIPE, shell=True)
commit_id = temp.stdout.read()[:8]
dirty = False
temp = subprocess.Popen(GIT_DIRTY, stdout=subprocess.PIPE, shell=True)
if temp.stdout.read()[-2] == '+':
dirty = True #commit_id = commit_id + '+'
# get date
day = datetime.datetime.today().day
mon = datetime.datetime.today().month
year = datetime.datetime.today().year
date = int(str(year*10000 + mon*100 + day), 16) # strange, I know, but I want to have something like x"20140917"
# convert version
ver = int(args.ver.translate(None, '.,'), 16)
# fill this all to the structure
write_sdb_info(f, MAIN_SYN, args.project, commit_id, dirty, args.tool, ver, date, args.user)
### Now generate synthesis info for each submodule
temp = subprocess.Popen("(cd "+toplevel+"; git submodule status)", stdout=subprocess.PIPE, shell=True)
submodules = temp.stdout.read()
submodules = submodules.split('\n')
for module in submodules[:-1]:
mod_splited = module.split()
name = mod_splited[1].split('/')[-1]
# if submodule is ahead of a set commit it displays additional _+_ at the
# beginning, get rid of that:
commit_id = mod_splited[0].translate(None, '+')[:8]
# check if dirty
dirty = False
temp = subprocess.Popen("(cd "+toplevel+"/"+mod_splited[1]+ ";" + GIT_DIRTY +")",
stdout=subprocess.PIPE, shell=True)
if temp.stdout.read()[-2] == '+':
dirty = True
write_sdb_info(f, name, name, commit_id, dirty, " ", 0, 0, " ")
f.write(PKG_TAIL)
f.close()
if __name__ == '__main__':
main()
top/pts_scb/pts_scb_top.ucf 0 → 100644
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top/pts_scb/pts_scb_top.vhd 0 → 100644
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top/pts_scb/pts_scb_top_bare.vhd 0 → 100644
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top/pts_scb/pts_wb_cpu_bridge.vhd 0 → 100644
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------------------------------------------------------------------------------
-- Title : Atmel EBI asynchronous bus <-> Wishbone bridge
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2017-02-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: An interface between AT91SAM9x-series ARM CPU External Bus Interface
-- and FPGA-internal Wishbone bus:
-- - does clock domain synchronisation
-- - provides configurable number of independent WB master ports at fixed base addresses
-- TODO:
-- - implement write queueing and read prefetching (for speed improvement)
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
-- 2017-02-08 1.1 INCAA Computers Added ACK timeout
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_cpu_bridge is
generic (
g_simulation : integer := 0;
g_cpu_addr_width : integer := 19;
g_wishbone_addr_width : integer := 19;
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port(
sys_rst_n_i : in std_logic; -- global reset
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
cpu_clk_i : in std_logic; -- clock (not used now)
-- async chip select, active LOW
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_addr_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone master I/F
-------------------------------------------------------------------------------
-- wishbone clock input (refclk/2)
wb_clk_i : in std_logic;
-- wishbone master address output (m->s, common for all slaves)
wb_addr_o : out std_logic_vector(g_wishbone_addr_width - 1 downto 0);
-- wishbone master data output (m->s, common for all slaves)
wb_data_o : out std_logic_vector(31 downto 0);
-- wishbone cycle strobe (m->s, common for all slaves)
wb_stb_o : out std_logic;
-- wishbone write enable (m->s, common for all slaves)
wb_we_o : out std_logic;
-- wishbone byte select output (m->s, common for all slaves)
wb_sel_o : out std_logic_vector(3 downto 0);
-- wishbone cycle select (m->s, individual)
wb_cyc_o : out std_logic;
-- wishbone master data input (s->m, individual)
wb_data_i : in std_logic_vector(31 downto 0);
-- wishbone ACK input (s->m, individual)
wb_ack_i : in std_logic
);
end wb_cpu_bridge;
architecture behavioral of wb_cpu_bridge is
signal rw_sel, cycle_in_progress, cs_synced, rd_pulse, wr_pulse : std_logic;
signal cpu_data_reg : std_logic_vector(31 downto 0);
signal ack_muxed : std_logic;
signal data_in_muxed : std_logic_vector(31 downto 0);
signal long_cycle : std_logic;
signal wb_cyc_int : std_logic;
signal wb_ack_timeout_cnt : unsigned(log2_ceil(g_ACK_TIMEOUT)-1 downto 0);
signal wb_ack_timeout : std_logic;
begin
gen_sync_chains_nosim : if(g_simulation = 0) generate
sync_ffs_cs : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map
(rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_cs_n_i,
synced_o => cs_synced,
npulse_o => open
);
sync_ffs_wr : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_wr_n_i,
synced_o => open,
npulse_o => wr_pulse
);
sync_ffs_rd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_rd_n_i,
synced_o => open,
npulse_o => rd_pulse
);
end generate gen_sync_chains_nosim;
gen_sim : if(g_simulation = 1) generate
wr_pulse <= not cpu_wr_n_i;
rd_pulse <= not cpu_rd_n_i;
cs_synced <= cpu_cs_n_i;
end generate gen_sim;
ack_muxed <= wb_ack_i;
data_in_muxed <= wb_data_i;
process(wb_clk_i)
begin
if(rising_edge(wb_clk_i)) then
if(sys_rst_n_i = '0') then
cpu_data_reg <= (others => '0');
cycle_in_progress <= '0';
rw_sel <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
wb_addr_o <= (others => '0');
wb_data_o <= (others => '0');
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
wb_cyc_int <= '0';
else
if(cs_synced = '0') then
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
if(cycle_in_progress = '1') then
if((ack_muxed = '1') or (wb_ack_timeout = '1')) then
if(rw_sel = '0') then
cpu_data_reg <= data_in_muxed;
end if;
cycle_in_progress <= '0';
wb_cyc_int <= '0';
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
else
cpu_nwait_o <= not long_cycle;
long_cycle <= '1';
end if;
elsif(rd_pulse = '1' or wr_pulse = '1') then
wb_we_o <= wr_pulse;
rw_sel <= wr_pulse;
wb_cyc_int <= '1';
wb_stb_o <= '1';
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
long_cycle <= '0';
if(wr_pulse = '1') then
wb_data_o <= cpu_data_b;
end if;
cycle_in_progress <= '1';
end if;
end if;
end if;
end if;
end process;
process(cpu_cs_n_i, cpu_rd_n_i, cpu_data_reg)
begin
if(cpu_cs_n_i = '0' and cpu_rd_n_i = '0') then
cpu_data_b <= cpu_data_reg;
else
cpu_data_b <= (others => 'Z');
end if;
end process;
wb_cyc_o <= wb_cyc_int;
-- ACK timeout
p_wb_ack_timeout_cnt : process (wb_clk_i, sys_rst_n_i)
begin
if rising_edge(wb_clk_i) then
if (sys_rst_n_i = '0') then
wb_ack_timeout_cnt <= (others => '1');
else
if (cycle_in_progress = '1') then
if wb_ack_timeout_cnt /= 0 then
wb_ack_timeout_cnt <= wb_ack_timeout_cnt - 1;
end if;
else
wb_ack_timeout_cnt <= (others => '1');
end if;
end if;
end if;
end process p_wb_ack_timeout_cnt;
p_ack_timeout : process (wb_clk_i, sys_rst_n_i)
begin
if rising_edge(wb_clk_i) then
if (sys_rst_n_i = '0') then
wb_ack_timeout <= '0';
else
if (wb_ack_timeout_cnt = 0) then
wb_ack_timeout <= '1';
else
wb_ack_timeout <= '0';
end if;
end if;
end if;
end process p_ack_timeout;
end behavioral;
top/pts_scb/scb_top_sim.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : WR Switch bare top level for simulation
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_sim.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-05
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Bare switch top module, without GTX transceivers and CPU bridge. Used as a
-- simulation top module.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
use work.wrsw_top_pkg.all;
use work.disparity_gen_pkg.all;
entity scb_top_sim is
generic(
g_num_ports : integer := 6;
g_with_TRU : boolean := true;
g_with_TATSU: boolean := true;
g_with_HWIU : boolean := true);
port (
sys_rst_n_i : in std_logic; -- global reset
-- Startup 25 MHz clock (from onboard 25 MHz oscillator)
clk_startup_i : in std_logic;
-- 125 MHz timing reference (from the AD9516 PLL output QDRII_CLK)
clk_ref_i : in std_logic;
-- 125+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
clk_dmtd_i : in std_logic;
-- 62.5 MHz system clock (from the AD9516 PLL output QDRII_200CLK)
-- clk_sys_i : in std_logic;
-- 200MHz clock to run the core of Multiport Memory in SWcore
clk_aux_i : in std_logic;
-------------------------------------------------------------------------------
-- Master wishbone bus (from the CPU bridge)
-------------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
-------------------------------------------------------------------------------
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
---------------------------------------------------------------------------
td_o : out std_logic_vector(18 * g_num_ports-1 downto 0);
rd_i : in std_logic_vector(18 * g_num_ports-1 downto 0);
rbclk_i : in std_logic_vector(g_num_ports-1 downto 0);
phys_rdy_i : in std_logic_vector(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
mbl_scl_b : inout std_logic_vector(1 downto 0);
mbl_sda_b : inout std_logic_vector(1 downto 0)
);
end scb_top_sim;
architecture rtl of scb_top_sim is
type t_8b10b_disparity_array is array (integer range <>) of t_8b10b_disparity;
signal cur_disp : t_8b10b_disparity_array(g_num_ports-1 downto 0);
signal cpu_wb_in : t_wishbone_slave_in;
signal cpu_wb_out : t_wishbone_slave_out;
signal phys_out : t_phyif_output_array(g_num_ports-1 downto 0);
signal phys_in : t_phyif_input_array(g_num_ports-1 downto 0);
signal cpu_irq_n : std_logic;
signal i2c_scl_oen : std_logic_vector(2 downto 0);
signal i2c_scl_out : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
signal i2c_sda_oen : std_logic_vector(2 downto 0);
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
begin -- rtl
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
cpu_wb_in.adr <= wb_adr_i;
cpu_wb_in.dat <= wb_dat_i;
cpu_wb_in.cyc <= wb_cyc_i;
cpu_wb_in.sel <= wb_sel_i;
cpu_wb_in.we <= wb_we_i;
cpu_wb_in.stb <= wb_stb_i;
wb_ack_o <= cpu_wb_out.ack;
wb_stall_o <= cpu_wb_out.stall;
wb_irq_o <= not cpu_irq_n;
wb_dat_o <= cpu_wb_out.dat;
U_Wrapped_SCBCore : scb_top_bare
generic map (
g_num_ports => g_num_ports,
g_simulation => true,
g_without_network => false,
g_with_TRU => g_with_TRU,
g_with_TATSU => g_with_TATSU,
g_with_HWIU => g_with_HWIU,
g_with_watchdog => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_startup_i,
clk_ref_i => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
-- clk_sys_i => clk_sys_i,
clk_aux_i => clk_aux_i,
clk_ext_mul_i => '0',
clk_ext_mul_locked_i=> '1',
cpu_wb_i => cpu_wb_in,
cpu_wb_o => cpu_wb_out,
cpu_irq_n_o => cpu_irq_n,
pps_i => pps_i,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
phys_o => phys_out,
phys_i => phys_in,
led_link_o => led_link_o,
led_act_o => led_act_o,
gpio_o => open,
gpio_i => (others => '0'),
i2c_scl_oen_o => i2c_scl_oen,
i2c_scl_o => i2c_scl_out,
i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in
);
gen_phys : for i in 0 to g_num_ports-1 generate
td_o(18 * i + 15 downto 18 * i) <= phys_out(i).tx_data;
td_o(18 * i + 17 downto 18 * i + 16) <= phys_out(i).tx_k;
phys_in(i).ref_clk <= clk_ref_i;
phys_in(i).rx_data <= rd_i(18 * i + 15 downto 18 * i);
phys_in(i).rx_k <= rd_i(18 * i + 17 downto 18 * i + 16);
phys_in(i).rx_clk <= rbclk_i(i);
phys_in(i).tx_enc_err <= '0';
phys_in(i).rx_enc_err <= '0';
phys_in(i).rdy <= phys_rdy_i(i);
p_gen_tx_disparity : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if phys_out(i).rst = '1' then
cur_disp(i) <= RD_MINUS;
else
cur_disp(i) <= f_next_8b10b_disparity16(cur_disp(i), phys_out(i).tx_k, phys_out(i).tx_data);
end if;
end if;
end process;
phys_in(i).tx_disparity <= to_std_logic(cur_disp(i));
end generate gen_phys;
end rtl;
top/pts_scb/swcore_pll.vhd 0 → 100644
View file @ be2ea7f5
-- file: swcore_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___187.500______0.000______50.0______266.979____459.961
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary____________62.5____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity swcore_pll is
port
(-- Clock in ports
clk_sys_i : in std_logic;
-- Clock out ports
clk_aux_o : out std_logic
);
end swcore_pll;
architecture xilinx of swcore_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "swcore_pll,clk_wiz_v4_1,{component_name=swcore_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=16.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : BUFG
port map
(O => clkin1,
I => clk_sys_i);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT_F => 63.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 5.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_unused,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => clk_aux_o,
I => clkout0);
end xilinx;
top/pts_scb/syst_mon.vhd 0 → 100644
View file @ be2ea7f5
-- file: syst_mon.vhd
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity syst_mon is
port (
DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
VAUXP0 : in STD_LOGIC; -- Auxiliary Channel 0
VAUXN0 : in STD_LOGIC;
VAUXP1 : in STD_LOGIC; -- Auxiliary Channel 1
VAUXN1 : in STD_LOGIC;
VAUXP2 : in STD_LOGIC; -- Auxiliary Channel 2
VAUXN2 : in STD_LOGIC;
VAUXP3 : in STD_LOGIC; -- Auxiliary Channel 3
VAUXN3 : in STD_LOGIC;
VAUXP4 : in STD_LOGIC; -- Auxiliary Channel 4
VAUXN4 : in STD_LOGIC;
VAUXP5 : in STD_LOGIC; -- Auxiliary Channel 5
VAUXN5 : in STD_LOGIC;
VAUXP6 : in STD_LOGIC; -- Auxiliary Channel 6
VAUXN6 : in STD_LOGIC;
VAUXP7 : in STD_LOGIC; -- Auxiliary Channel 7
VAUXN7 : in STD_LOGIC;
BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
EOS_OUT : out STD_LOGIC; -- End of Sequence Signal
VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
VN_IN : in STD_LOGIC
);
end syst_mon;
architecture xilinx of syst_mon is
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";
signal aux_channel_p : std_logic_vector (15 downto 0);
signal aux_channel_n : std_logic_vector (15 downto 0);
begin
aux_channel_p(0) <= VAUXP0;
aux_channel_n(0) <= VAUXN0;
aux_channel_p(1) <= VAUXP1;
aux_channel_n(1) <= VAUXN1;
aux_channel_p(2) <= VAUXP2;
aux_channel_n(2) <= VAUXN2;
aux_channel_p(3) <= VAUXP3;
aux_channel_n(3) <= VAUXN3;
aux_channel_p(4) <= VAUXP4;
aux_channel_n(4) <= VAUXN4;
aux_channel_p(5) <= VAUXP5;
aux_channel_n(5) <= VAUXN5;
aux_channel_p(6) <= VAUXP6;
aux_channel_n(6) <= VAUXN6;
aux_channel_p(7) <= VAUXP7;
aux_channel_n(7) <= VAUXN7;
aux_channel_p(8) <= '0';
aux_channel_n(8) <= '0';
aux_channel_p(9) <= '0';
aux_channel_n(9) <= '0';
aux_channel_p(10) <= '0';
aux_channel_n(10) <= '0';
aux_channel_p(11) <= '0';
aux_channel_n(11) <= '0';
aux_channel_p(12) <= '0';
aux_channel_n(12) <= '0';
aux_channel_p(13) <= '0';
aux_channel_n(13) <= '0';
aux_channel_p(14) <= '0';
aux_channel_n(14) <= '0';
aux_channel_p(15) <= '0';
aux_channel_n(15) <= '0';
SYSMON_INST : SYSMON
generic map(
INIT_40 => X"1000", -- config reg 0
INIT_41 => X"20ff", -- config reg 1
INIT_42 => X"0d00", -- config reg 2
INIT_48 => X"0701", -- Sequencer channel selection
INIT_49 => X"00ff", -- Sequencer channel selection
INIT_4A => X"0700", -- Sequencer Average selection
INIT_4B => X"00ff", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"b5ed", -- Temp alarm trigger
INIT_51 => X"5999", -- Vccint upper alarm limit
INIT_52 => X"e000", -- Vccaux upper alarm limit
INIT_53 => X"ca33", -- Temp alarm OT upper
INIT_54 => X"a93a", -- Temp alarm reset
INIT_55 => X"5111", -- Vccint lower alarm limit
INIT_56 => X"caaa", -- Vccaux lower alarm limit
INIT_57 => X"ae4e", -- Temp alarm OT reset
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => "design.txt"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR(6 downto 0) => DADDR_IN(6 downto 0),
DCLK => DCLK_IN,
DEN => DEN_IN,
DI(15 downto 0) => DI_IN(15 downto 0),
DWE => DWE_IN,
RESET => RESET_IN,
VAUXN(15 downto 0) => aux_channel_n(15 downto 0),
VAUXP(15 downto 0) => aux_channel_p(15 downto 0),
ALM(2) => open,
ALM(1) => open,
ALM(0) => open,
BUSY => BUSY_OUT,
CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),
DO(15 downto 0) => DO_OUT(15 downto 0),
DRDY => DRDY_OUT,
EOC => EOC_OUT,
EOS => EOS_OUT,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open,
OT => open,
VN => VP_IN,
VP => VN_IN
);
end xilinx;
top/pts_scb/wb_build.sh 0 → 100644
View file @ be2ea7f5
#!/bin/bash
wbgen2 -D ./wb_freq_regs.html -V wb_freq_regs.vhd --hstyle record -p freq_wbgen2_pkg.vhd wb_freq_regs.wb
top/pts_scb/wb_cpu_bridge.vhd 0 → 100644
View file @ be2ea7f5
------------------------------------------------------------------------------
-- Title : Atmel EBI asynchronous bus <-> Wishbone bridge
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-09-13
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: An interface between AT91SAM9x-series ARM CPU External Bus Interface
-- and FPGA-internal Wishbone bus:
-- - does clock domain synchronisation
-- - provides configurable number of independent WB master ports at fixed base addresses
-- TODO:
-- - implement write queueing and read prefetching (for speed improvement)
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_cpu_bridge is
generic (
g_simulation : integer := 0;
g_cpu_addr_width : integer := 19;
g_wishbone_addr_width : integer := 19
);
port(
sys_rst_n_i : in std_logic; -- global reset
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
cpu_clk_i : in std_logic; -- clock (not used now)
-- async chip select, active LOW
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_addr_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone master I/F
-------------------------------------------------------------------------------
-- wishbone clock input (refclk/2)
wb_clk_i : in std_logic;
-- wishbone master address output (m->s, common for all slaves)
wb_addr_o : out std_logic_vector(g_wishbone_addr_width - 1 downto 0);
-- wishbone master data output (m->s, common for all slaves)
wb_data_o : out std_logic_vector(31 downto 0);
-- wishbone cycle strobe (m->s, common for all slaves)
wb_stb_o : out std_logic;
-- wishbone write enable (m->s, common for all slaves)
wb_we_o : out std_logic;
-- wishbone byte select output (m->s, common for all slaves)
wb_sel_o : out std_logic_vector(3 downto 0);
-- wishbone cycle select (m->s, individual)
wb_cyc_o : out std_logic;
-- wishbone master data input (s->m, individual)
wb_data_i : in std_logic_vector(31 downto 0);
-- wishbone ACK input (s->m, individual)
wb_ack_i : in std_logic
);
end wb_cpu_bridge;
architecture behavioral of wb_cpu_bridge is
constant c_periph_addr_bits : integer := g_cpu_addr_width - g_wishbone_addr_width;
signal rw_sel, cycle_in_progress, cs_synced, rd_pulse, wr_pulse : std_logic;
signal cpu_data_reg : std_logic_vector(31 downto 0);
signal ack_muxed : std_logic;
signal data_in_muxed : std_logic_vector(31 downto 0);
signal long_cycle : std_logic;
signal wb_cyc_int : std_logic;
begin
gen_sync_chains_nosim : if(g_simulation = 0) generate
sync_ffs_cs : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map
(rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_cs_n_i,
synced_o => cs_synced,
npulse_o => open
);
sync_ffs_wr : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_wr_n_i,
synced_o => open,
npulse_o => wr_pulse
);
sync_ffs_rd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_rd_n_i,
synced_o => open,
npulse_o => rd_pulse
);
end generate gen_sync_chains_nosim;
gen_sim : if(g_simulation = 1) generate
wr_pulse <= not cpu_wr_n_i;
rd_pulse <= not cpu_rd_n_i;
cs_synced <= cpu_cs_n_i;
end generate gen_sim;
ack_muxed <= wb_ack_i;
data_in_muxed <= wb_data_i;
process(wb_clk_i)
begin
if(rising_edge(wb_clk_i)) then
if(sys_rst_n_i = '0') then
cpu_data_reg <= (others => '0');
cycle_in_progress <= '0';
rw_sel <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
wb_addr_o <= (others => '0');
wb_data_o <= (others => '0');
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
wb_cyc_int <= '0';
else
if(cs_synced = '0') then
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
if(cycle_in_progress = '1') then
if(ack_muxed = '1') then
if(rw_sel = '0') then
cpu_data_reg <= data_in_muxed;
end if;
cycle_in_progress <= '0';
wb_cyc_int <= '0';
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
else
cpu_nwait_o <= not long_cycle;
long_cycle <= '1';
end if;
elsif(rd_pulse = '1' or wr_pulse = '1') then
wb_we_o <= wr_pulse;
rw_sel <= wr_pulse;
wb_cyc_int <= '1';
wb_stb_o <= '1';
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
long_cycle <= '0';
-- periph_addr_reg <= cpu_addr_i (g_cpu_addr_width-1 downto g_wishbone_addr_width);
-- periph_sel_reg <= periph_sel;
if(wr_pulse = '1') then
wb_data_o <= cpu_data_b;
end if;
cycle_in_progress <= '1';
end if;
end if;
end if;
end if;
end process;
process(cpu_cs_n_i, cpu_rd_n_i, cpu_data_reg)
begin
if(cpu_cs_n_i = '0' and cpu_rd_n_i = '0') then
cpu_data_b <= cpu_data_reg;
else
cpu_data_b <= (others => 'Z');
end if;
end process;
wb_cyc_o <= wb_cyc_int;
end behavioral;
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top/pts_scb/wb_freq_regs.vhd 0 → 100644
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS Frequency Measurement Result Registers
---------------------------------------------------------------------------------------
-- File : wb_freq_regs.vhd
-- Author : auto-generated by wbgen2 from wb_freq_regs.wb
-- Created : Wed Feb 15 11:13:39 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_freq_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.freq_wbgen2_pkg.all;
entity wb_freq_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_freq_in_registers;
regs_o : out t_freq_out_registers
);
end wb_freq_regs;
architecture syn of wb_freq_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.f_dmtd_clk_freq_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.f_clk10mhz_ext_freq_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.f_fpga_main_clk_freq_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.f_aux_clk_freq_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.f_serdes_clk_freq_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.f_ref_clk_freq_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Clock Frequency
-- Clock Frequency
-- Clock Frequency
-- Clock Frequency
-- Clock Frequency
-- Clock Frequency
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
top/pts_scb/wb_freq_regs.wb 0 → 100644
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "PTS Frequency Measurement Result Registers";
hdl_entity = "wb_freq_regs";
prefix = "freq";
reg {
name = "DMTD Frequency";
prefix = "F";
field {
name = "Clock Frequency";
prefix = "DMTD_CLK_FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CLK10MHZ_EXT Frequency";
prefix = "F";
field {
name = "Clock Frequency";
prefix = "CLK10MHZ_EXT_FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FPGA_MAIN_CLK Frequency";
prefix = "F";
field {
name = "Clock Frequency";
prefix = "FPGA_MAIN_CLK_FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "AUX_CLK Frequency";
prefix = "F";
field {
name = "Clock Frequency";
prefix = "AUX_CLK_FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "SERDES_CLK Frequency";
prefix = "F";
field {
name = "Clock Frequency";
prefix = "SERDES_CLK_FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "REF_CLK Frequency";
prefix = "F";
field {
name = "Clock Frequency";
prefix = "REF_CLK_FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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