update gateware version to v6.0

d315bf7b · Grzegorz Daniluk · 8b7d73e6 · d315bf7b · d315bf7b
Commit d315bf7b authored Apr 03, 2020 by Grzegorz Daniluk
Hide whitespace changes
Inline Side-by-side

Showing with 5 additions and 5 deletions

gw_ver_pkg.vhd modules/wrsw_hwiu/gw_ver_pkg.vhd +4 -4

scb_top_bare.vhd top/bare_top/scb_top_bare.vhd +1 -1

No files found.
--- a/modules/wrsw_hwiu/gw_ver_pkg.vhd
+++ b/modules/wrsw_hwiu/gw_ver_pkg.vhd
@@ -2,8 +2,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 --generated automatically by gen_ver.py script--
 package hwver_pkg is
-constant c_build_date : std_logic_vector(31 downto 0) := x"13080f00";
+constant c_build_date : std_logic_vector(31 downto 0) := x"06041400";
-constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"0c49e847";
+constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"04e89257";
-constant c_gencores_ver : std_logic_vector(31 downto 0) := x"012c045e";
+constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3";
-constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"004583a9";
+constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65";
 end package;
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -1215,7 +1215,7 @@ begin
        g_interface_mode => PIPELINED,
        g_address_granularity => BYTE,
        g_ndbg_regs => c_DBG_N_REGS,
-        g_ver_major => 5,
+        g_ver_major => 6,
        g_ver_minor => 0,
        g_build     => 1)
      port map(