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White Rabbit Switch - Gateware
Commit e28c46f2 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrsw_nic: fix indentation in *.wb file

parent 09a80ee1
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modules/wrsw_nic/wr_nic.wb
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...@@ -44,191 +44,190 @@ top = peripheral { ...@@ -44,191 +44,190 @@ top = peripheral {
prefix = "nic"; prefix = "nic";
reg { reg {
name = "NIC Control Register"; name = "NIC Control Register";
prefix = "CR"; prefix = "CR";
field { field {
name = "Receive enable"; name = "Receive enable";
description = "Enables the NIC to receive data"; description = "Enables the NIC to receive data";
prefix = "rx_en"; prefix = "rx_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "Transmit enable"; name = "Transmit enable";
description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool"; description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool";
prefix = "tx_en"; prefix = "tx_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "Rx bandwidth throttling enable"; name = "Rx bandwidth throttling enable";
description = "Enables bandwidth throttling for received traffic. \ description = "Enables bandwidth throttling for received traffic. \
This is to prevent blocking ARM CPU with interrupts coming from NIC"; This is to prevent blocking ARM CPU with interrupts coming from NIC";
prefix = "rxthr_en"; prefix = "rxthr_en";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "Software Reset"; name = "Software Reset";
description = "write 1: reset the NIC, zero all registers and reset the state of the module \ description = "write 1: reset the NIC, zero all registers and reset the state of the module \
write 0: no effect"; write 0: no effect";
prefix = "sw_rst"; prefix = "sw_rst";
size = 1; size = 1;
align = 31; align = 31;
type = MONOSTABLE; type = MONOSTABLE;
}; };
}; };
reg { reg {
name = "NIC Status Register"; name = "NIC Status Register";
prefix = "SR"; prefix = "SR";
field { field {
name = "Buffer Not Available"; name = "Buffer Not Available";
prefix = "bna"; prefix = "bna";
description = "No buffers were available when receiving a packet."; description = "No buffers were available when receiving a packet.";
type = BIT; type = BIT;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
load = LOAD_EXT; load = LOAD_EXT;
}; };
field { field {
name = "Frame Received"; name = "Frame Received";
prefix = "rec"; prefix = "rec";
description = "One or more frames have been received.\ description = "One or more frames have been received.\
Cleared by writing a one to this bit"; Cleared by writing a one to this bit";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
field { field {
name = "Transmission done"; name = "Transmission done";
prefix = "tx_done"; prefix = "tx_done";
description = "read 1: All non-empty TX descriptors have been transmitted\ description = "read 1: All non-empty TX descriptors have been transmitted\
read 0: Transmission in progress\ read 0: Transmission in progress\
write 1: Clears the flag\ write 1: Clears the flag\
write 0: No effect"; write 0: No effect";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
field { field {
name = "Transmission error"; name = "Transmission error";
prefix = "tx_error"; prefix = "tx_error";
description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\ description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\
read 0: No TX error\ read 0: No TX error\
write 1: Clears the flag\ write 1: Clears the flag\
write 0: No effect"; write 0: No effect";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
field {
field { align = 8;
align = 8; name = "Current TX descriptor";
name = "Current TX descriptor"; size = 3;
size = 3; prefix = "cur_TX_Desc";
prefix = "cur_TX_Desc"; description = "Index of the currently handled TX descriptor";
description = "Index of the currently handled TX descriptor"; type = SLV;
type = SLV; access_bus = READ_ONLY;
access_bus = READ_ONLY; access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY; };
};
field {
field { align = 8;
align = 8; name = "Current RX descriptor";
name = "Current RX descriptor"; size = 3;
size = 3; prefix = "cur_RX_DESC";
prefix = "cur_RX_DESC"; description = "Index of the currently handled RX descriptor";
description = "Index of the currently handled RX descriptor"; type = SLV;
type = SLV; access_bus = READ_ONLY;
access_bus = READ_ONLY; access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY; };
};
}; };
reg { reg {
name = "NIC Current Rx Bandwidth Register"; name = "NIC Current Rx Bandwidth Register";
prefix = "RXBW"; prefix = "RXBW";
field { field {
name = "Bytes-per-second"; name = "Bytes-per-second";
type = SLV; type = SLV;
size = 32; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
load = LOAD_EXT; load = LOAD_EXT;
}; };
}; };
reg { reg {
name = "NIC Max Rx Bandwidth Register"; name = "NIC Max Rx Bandwidth Register";
prefix = "MAXRXBW"; prefix = "MAXRXBW";
field { field {
name = "KBytes-per-second"; name = "KBytes-per-second";
type = SLV; type = SLV;
size = 16; size = 16;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
}; };
irq { irq {
name = "Receive Complete"; name = "Receive Complete";
prefix = "rcomp"; prefix = "rcomp";
ack_line = true; ack_line = true;
description = "A frame has been stored in memory."; description = "A frame has been stored in memory.";
trigger = LEVEL_1; trigger = LEVEL_1;
}; };
irq { irq {
name = "Transmit Complete"; name = "Transmit Complete";
prefix = "tcomp"; prefix = "tcomp";
ack_line = true; ack_line = true;
mask_line = true; mask_line = true;
description = "Frame successfully transmitted"; description = "Frame successfully transmitted";
trigger = LEVEL_1; trigger = LEVEL_1;
}; };
irq { irq {
name = "Transmit Error"; name = "Transmit Error";
prefix = "txerr"; prefix = "txerr";
ack_line = true; ack_line = true;
mask_line = true; mask_line = true;
trigger = LEVEL_1; trigger = LEVEL_1;
}; };
ram { ram {
name = "TX descriptors mem"; name = "TX descriptors mem";
prefix = "dtx"; prefix = "dtx";
size = 32; size = 32;
width = 32; width = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
}; };
ram { ram {
name = "RX descriptors mem"; name = "RX descriptors mem";
prefix = "drx"; prefix = "drx";
size = 32; size = 32;
width = 32; width = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
}; };
-- ram { -- ram {
...@@ -245,258 +244,246 @@ top = peripheral { ...@@ -245,258 +244,246 @@ top = peripheral {
}; };
TX_desc_template = TX_desc_template = {
{ reg {
name = "TX Descriptor %d register 1";
reg { description = "1st part of TX descriptor header. ";
name = "TX Descriptor %d register 1"; prefix = "tx%d_d1";
description = "1st part of TX descriptor header. ";
prefix = "tx%d_d1";
align = 4;
field {
name = "Ready";
prefix = "ready";
description = "0 - The descriptor and buffer can be manipulated. \
1 - The device owns the descriptor and will set the bit to 0 after transmission";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg { align = 4;
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg { field {
name = "TX Descriptor %d register 3"; name = "Ready";
prefix = "tx%d_d3"; prefix = "ready";
field { description = "0 - The descriptor and buffer can be manipulated. \
prefix = "DPM"; 1 - The device owns the descriptor and will set the bit to 0 after transmission";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet."; type = BIT;
type = SLV; access_bus = READ_WRITE;
size = 32; access_dev = READ_WRITE;
access_bus = READ_WRITE; load = LOAD_EXT;
access_dev = READ_ONLY; };
};
}; field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 3";
prefix = "tx%d_d3";
field {
prefix = "DPM";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
}; };
RX_desc_template = { RX_desc_template = {
reg { reg {
align=4; align=4;
name = "RX Descriptor %d register 1"; name = "RX Descriptor %d register 1";
description = "Descriptor of an RX frame buffer"; description = "Descriptor of an RX frame buffer";
prefix = "rx%d_d1"; prefix = "rx%d_d1";
field { field {
name = "Empty"; name = "Empty";
prefix = "empty"; prefix = "empty";
description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \ description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \
1 - The buffer is ready to be filled in with data by the NIC"; 1 - The buffer is ready to be filled in with data by the NIC";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
field { field {
name = "Error"; name = "Error";
prefix = "error"; prefix = "error";
description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)"; description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)";
type = BIT; type = BIT;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field { field {
name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block."; name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block.";
prefix = "port"; prefix = "port";
type = SLV; type = SLV;
size = 6; size = 6;
align = 8; align = 8;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field { field {
name = "Got RX Timestamp"; name = "Got RX Timestamp";
prefix = "GOT_TS"; prefix = "GOT_TS";
description = "1 - there is a valid RX timestamp present in the TS field,\ description = "1 - there is a valid RX timestamp present in the TS field,\
0 - no RX timestamp"; 0 - no RX timestamp";
type = BIT; type = BIT;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field { field {
name = "RX Timestamp (possibly) incorrect"; name = "RX Timestamp (possibly) incorrect";
prefix = "TS_INCORRECT"; prefix = "TS_INCORRECT";
align = 15; align = 15;
description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\ description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
0 - RX timestamp OK."; 0 - RX timestamp OK.";
type = BIT; type = BIT;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
reg {
name = "RX Descriptor %d register 2";
reg { prefix = "rx%d_d2";
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2"; field {
name = "RX_TS_R";
field { prefix = "TS_R";
name = "RX_TS_R"; description = "Value of the RX timestamp (rising edge bits)";
prefix = "TS_R"; size = 28;
description = "Value of the RX timestamp (rising edge bits)"; type = SLV;
size = 28; access_bus = READ_ONLY;
type = SLV; access_dev = WRITE_ONLY;
access_bus = READ_ONLY; };
access_dev = WRITE_ONLY;
}; field {
name = "RX_TS_F";
field { prefix = "TS_F";
name = "RX_TS_F"; description = "Value of the RX timestamp (falling edge bits)";
prefix = "TS_F"; size = 4;
description = "Value of the RX timestamp (falling edge bits)"; type = SLV;
size = 4; access_bus = READ_ONLY;
type = SLV; access_dev = WRITE_ONLY;
access_bus = READ_ONLY; };
access_dev = WRITE_ONLY; };
};
}; reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
}; };
function generate_descriptors(n) function generate_descriptors(n)
local i; local i;
for i=1,n do for i=1,n do
local T=deepcopy(TX_desc_template); local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T); table_join(periph, T);
end end
for i=1,n do for i=1,n do
local T=deepcopy(RX_desc_template); local T=deepcopy(RX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
table_join(periph, T); foreach_reg({TYPE_REG}, function(r)
end r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
table_join(periph, T);
end
end end
--generate_descriptors(1); --generate_descriptors(1);
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