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White Rabbit Switch - Gateware
Commits
e8d3e8f3
Commit
e8d3e8f3
authored
Jul 05, 2013
by
Grzegorz Daniluk
Browse files
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Plain Diff
wrsw_nic: update wb slave interface
parent
a12e16b0
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Showing
3 changed files
with
274 additions
and
272 deletions
+274
-272
nic_wbgen2_pkg.vhd
modules/wrsw_nic/nic_wbgen2_pkg.vhd
+20
-7
nic_wishbone_slave.vhd
modules/wrsw_nic/nic_wishbone_slave.vhd
+241
-254
xwrsw_nic.vhd
modules/wrsw_nic/xwrsw_nic.vhd
+13
-11
No files found.
modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @
e8d3e8f3
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created :
Thu Jan 12 17:37:53 2012
-- Created :
Fri Jul 5 14:53:50 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
...
@@ -67,6 +67,7 @@ package nic_wbgen2_pkg is
);
function
"or"
(
left
,
right
:
t_nic_in_registers
)
return
t_nic_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
end
package
;
package
body
nic_wbgen2_pkg
is
...
...
@@ -78,15 +79,27 @@ else
return
x
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0'
;
else
tmp
(
i
):
=
x
(
i
);
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_nic_in_registers
)
return
t_nic_in_registers
is
variable
tmp
:
t_nic_in_registers
;
begin
tmp
.
sr_bna_i
:
=
left
.
sr_bna_i
or
right
.
sr_bna_i
;
tmp
.
sr_rec_i
:
=
left
.
sr_rec_i
or
right
.
sr_rec_i
;
tmp
.
sr_tx_done_i
:
=
left
.
sr_tx_done_i
or
right
.
sr_tx_done_i
;
tmp
.
sr_tx_error_i
:
=
left
.
sr_tx_error_i
or
right
.
sr_tx_error_i
;
tmp
.
sr_cur_tx_desc_i
:
=
left
.
sr_cur_tx_desc_i
or
right
.
sr_cur_tx_desc_i
;
tmp
.
sr_cur_rx_desc_i
:
=
left
.
sr_cur_rx_desc_i
or
right
.
sr_cur_rx_desc_i
;
tmp
.
sr_bna_i
:
=
f_x_to_zero
(
left
.
sr_bna_i
)
or
f_x_to_zero
(
right
.
sr_bna_i
)
;
tmp
.
sr_rec_i
:
=
f_x_to_zero
(
left
.
sr_rec_i
)
or
f_x_to_zero
(
right
.
sr_rec_i
)
;
tmp
.
sr_tx_done_i
:
=
f_x_to_zero
(
left
.
sr_tx_done_i
)
or
f_x_to_zero
(
right
.
sr_tx_done_i
)
;
tmp
.
sr_tx_error_i
:
=
f_x_to_zero
(
left
.
sr_tx_error_i
)
or
f_x_to_zero
(
right
.
sr_tx_error_i
)
;
tmp
.
sr_cur_tx_desc_i
:
=
f_x_to_zero
(
left
.
sr_cur_tx_desc_i
)
or
f_x_to_zero
(
right
.
sr_cur_tx_desc_i
)
;
tmp
.
sr_cur_rx_desc_i
:
=
f_x_to_zero
(
left
.
sr_cur_rx_desc_i
)
or
f_x_to_zero
(
right
.
sr_cur_rx_desc_i
)
;
return
tmp
;
end
function
;
end
package
body
;
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @
e8d3e8f3
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created :
Thu Jan 12 17:37:53 2012
-- Created :
Fri Jul 5 14:53:50 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
...
@@ -21,16 +21,17 @@ use work.nic_wbgen2_pkg.all;
entity
nic_wishbone_slave
is
port
(
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_ad
dr_i
:
in
std_logic_vector
(
6
downto
0
);
wb_dat
a_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a_o
:
out
std_logic_vector
(
31
downto
0
);
clk_sys_i
:
in
std_logic
;
wb_ad
r_i
:
in
std_logic_vector
(
6
downto
0
);
wb_dat
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_rcomp_i
:
in
std_logic
;
irq_rcomp_ack_o
:
out
std_logic
;
irq_tcomp_i
:
in
std_logic
;
...
...
@@ -92,22 +93,20 @@ signal rwaddr_reg : std_logic_vector(6 downto 0);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
bus_clock_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat
a
_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
-- bus_clock_int <= wb_clk_i;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
wb_clk
_i
,
rst_n_i
)
process
(
clk_sys
_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
...
...
@@ -122,7 +121,7 @@ begin
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
elsif
rising_edge
(
wb_clk
_i
)
then
elsif
rising_edge
(
clk_sys
_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
...
...
@@ -149,275 +148,262 @@ begin
case
rwaddr_reg
(
3
downto
0
)
is
when
"0000"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
nic_cr_rx_en_int
<=
wrdata_reg
(
0
);
rddata_reg
(
1
)
<=
'X'
;
nic_cr_tx_en_int
<=
wrdata_reg
(
1
);
else
rddata_reg
(
0
)
<=
nic_cr_rx_en_int
;
rddata_reg
(
1
)
<=
nic_cr_tx_en_int
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
nic_cr_rx_en_int
;
rddata_reg
(
1
)
<=
nic_cr_tx_en_int
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0001"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
regs_o
.
sr_rec_load_o
<=
'1'
;
rddata_reg
(
2
)
<=
'X'
;
regs_o
.
sr_tx_done_load_o
<=
'1'
;
rddata_reg
(
3
)
<=
'X'
;
regs_o
.
sr_tx_error_load_o
<=
'1'
;
else
rddata_reg
(
0
)
<=
regs_i
.
sr_bna_i
;
rddata_reg
(
1
)
<=
regs_i
.
sr_rec_i
;
rddata_reg
(
2
)
<=
regs_i
.
sr_tx_done_i
;
rddata_reg
(
3
)
<=
regs_i
.
sr_tx_error_i
;
rddata_reg
(
10
downto
8
)
<=
regs_i
.
sr_cur_tx_desc_i
;
rddata_reg
(
18
downto
16
)
<=
regs_i
.
sr_cur_rx_desc_i
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
regs_i
.
sr_bna_i
;
rddata_reg
(
1
)
<=
regs_i
.
sr_rec_i
;
rddata_reg
(
2
)
<=
regs_i
.
sr_tx_done_i
;
rddata_reg
(
3
)
<=
regs_i
.
sr_tx_error_i
;
rddata_reg
(
10
downto
8
)
<=
regs_i
.
sr_cur_tx_desc_i
;
rddata_reg
(
18
downto
16
)
<=
regs_i
.
sr_cur_rx_desc_i
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0010"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
reset_wr_o
<=
'1'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
if
(
wb_we_i
=
'1'
)
then
eic_idr_write_int
<=
'1'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1001"
=>
if
(
wb_we_i
=
'1'
)
then
eic_ier_write_int
<=
'1'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1010"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
2
downto
0
)
<=
eic_imr_int
(
2
downto
0
);
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
2
downto
0
)
<=
eic_imr_int
(
2
downto
0
);
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1011"
=>
if
(
wb_we_i
=
'1'
)
then
eic_isr_write_int
<=
'1'
;
else
rddata_reg
(
2
downto
0
)
<=
eic_isr_status_int
(
2
downto
0
);
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
2
downto
0
)
<=
eic_isr_status_int
(
2
downto
0
);
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
...
...
@@ -451,30 +437,30 @@ begin
-- Data output multiplexer process
process
(
rddata_reg
,
rwaddr_reg
,
nic_dtx_rddata_int
,
nic_drx_rddata_int
,
wb_ad
d
r_i
)
process
(
rddata_reg
,
rwaddr_reg
,
nic_dtx_rddata_int
,
nic_drx_rddata_int
,
wb_adr_i
)
begin
case
rwaddr_reg
(
6
downto
5
)
is
when
"01"
=>
wb_dat
a
_o
(
31
downto
0
)
<=
nic_dtx_rddata_int
;
wb_dat_o
(
31
downto
0
)
<=
nic_dtx_rddata_int
;
when
"10"
=>
wb_dat
a
_o
(
31
downto
0
)
<=
nic_drx_rddata_int
;
wb_dat_o
(
31
downto
0
)
<=
nic_drx_rddata_int
;
when
others
=>
wb_dat
a
_o
<=
rddata_reg
;
wb_dat_o
<=
rddata_reg
;
end
case
;
end
process
;
-- Read & write lines decoder for RAMs
process
(
wb_ad
d
r_i
,
rd_int
,
wr_int
)
process
(
wb_adr_i
,
rd_int
,
wr_int
)
begin
if
(
wb_ad
d
r_i
(
6
downto
5
)
=
"01"
)
then
if
(
wb_adr_i
(
6
downto
5
)
=
"01"
)
then
nic_dtx_rd_int
<=
rd_int
;
nic_dtx_wr_int
<=
wr_int
;
else
nic_dtx_wr_int
<=
'0'
;
nic_dtx_rd_int
<=
'0'
;
end
if
;
if
(
wb_ad
d
r_i
(
6
downto
5
)
=
"10"
)
then
if
(
wb_adr_i
(
6
downto
5
)
=
"10"
)
then
nic_drx_rd_int
<=
rd_int
;
nic_drx_wr_int
<=
wr_int
;
else
...
...
@@ -511,8 +497,8 @@ begin
g_use_bwsel
=>
false
)
port
map
(
clk_a_i
=>
wb_clk
_i
,
clk_b_i
=>
wb_clk
_i
,
clk_a_i
=>
clk_sys
_i
,
clk_b_i
=>
clk_sys
_i
,
addr_b_i
=>
nic_dtx_addr_i
,
addr_a_i
=>
rwaddr_reg
(
4
downto
0
),
data_b_o
=>
nic_dtx_data_o
,
...
...
@@ -538,8 +524,8 @@ begin
g_use_bwsel
=>
false
)
port
map
(
clk_a_i
=>
wb_clk
_i
,
clk_b_i
=>
wb_clk
_i
,
clk_a_i
=>
clk_sys
_i
,
clk_b_i
=>
clk_sys
_i
,
addr_b_i
=>
nic_drx_addr_i
,
addr_a_i
=>
rwaddr_reg
(
4
downto
0
),
data_b_o
=>
nic_drx_data_o
,
...
...
@@ -598,7 +584,7 @@ begin
g_irq1f_mode
=>
0
)
port
map
(
clk_i
=>
wb_clk
_i
,
clk_i
=>
clk_sys
_i
,
rst_n_i
=>
rst_n_i
,
irq_i
=>
irq_inputs_vector_int
,
irq_ack_o
=>
eic_irq_ack_int
,
...
...
@@ -610,7 +596,7 @@ begin
reg_isr_o
=>
eic_isr_status_int
,
reg_isr_i
=>
eic_isr_clear_int
,
reg_isr_wr_stb_i
=>
eic_isr_write_int
,
wb_irq_o
=>
wb_i
rq
_o
wb_irq_o
=>
wb_i
nt
_o
);
irq_inputs_vector_int
(
0
)
<=
irq_rcomp_i
;
...
...
@@ -621,7 +607,8 @@ begin
irq_inputs_vector_int
(
2
)
<=
irq_txerr_i
;
irq_txerr_ack_o
<=
eic_irq_ack_int
(
2
);
irq_txerr_mask_o
<=
eic_imr_int
(
2
);
rwaddr_reg
<=
wb_addr_i
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
modules/wrsw_nic/xwrsw_nic.vhd
View file @
e8d3e8f3
...
...
@@ -17,7 +17,7 @@ entity xwrsw_nic is
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -127,16 +127,17 @@ architecture rtl of xwrsw_nic is
component
nic_wishbone_slave
port
(
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_ad
d
r_i
:
in
std_logic_vector
(
6
downto
0
);
wb_dat
a
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a
_o
:
out
std_logic_vector
(
31
downto
0
);
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
6
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_rcomp_i
:
in
std_logic
;
irq_rcomp_ack_o
:
out
std_logic
;
irq_tcomp_i
:
in
std_logic
;
...
...
@@ -290,16 +291,17 @@ begin -- rtl
U_WB_SLAVE
:
nic_wishbone_slave
port
map
(
rst_n_i
=>
rst_n_i
,
wb_clk_i
=>
clk_sys_i
,
wb_ad
d
r_i
=>
wb_in
.
adr
(
6
downto
0
),
wb_dat
a
_i
=>
wb_in
.
dat
,
wb_dat
a
_o
=>
wb_rdata_slave
,
clk_sys_i
=>
clk_sys_i
,
wb_adr_i
=>
wb_in
.
adr
(
6
downto
0
),
wb_dat_i
=>
wb_in
.
dat
,
wb_dat_o
=>
wb_rdata_slave
,
wb_cyc_i
=>
wb_cyc_slave
,
wb_sel_i
=>
wb_in
.
sel
,
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_ack_slave
,
wb_irq_o
=>
wb_out
.
int
,
wb_stall_o
=>
wb_out
.
stall
,
wb_int_o
=>
wb_out
.
int
,
regs_o
=>
regs_fromwb
,
...
...
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