Commit ebe9d4c9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'greg-low-jitter' into proposed_master

parents 31787035 76eaac7d
Subproject commit f73f8239488db55089b83fd5a111cb550f03a5c1
Subproject commit 8478786f1ed97c507e2f5d04219a5ebc9a31e708
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd", "gen10_wishbone_slave.vhd"]
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd",
"gen10_wishbone_slave.vhd", "wrsw_ljd_detect.vhd"]
-------------------------------------------------------------------------------
-- Title : wrsw_ljd_detect
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_ljd_detect.vhd
-- Author : Mattia Rzzi
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- FSM to check the presence of the WRS Low jitter daughterboard
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2016 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_top_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity wrsw_ljd_detect is
generic (
g_pattern : std_logic_vector(63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
loopback_i : in std_logic;
loopback_o : out std_logic;
board_detected_o : out std_logic
);
end wrsw_ljd_detect;
architecture Behavioral of wrsw_ljd_detect is
signal clk_divider : integer range 0 to g_clk_divider-1;
signal clk_en : std_logic;
signal bit_position : integer range 0 to g_pattern'length-1;
signal error_detected : std_logic;
type fsm_states is (INIT, WRITE_BIT, READ_BIT, DONE);
signal fsm_state : fsm_states := INIT;
begin
clock_divider_inst : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
clk_divider <= clk_divider + 1;
if (clk_divider = g_clk_divider - 1) then
clk_divider <= 0;
clk_en <= '1';
else
clk_en <= '0';
end if;
end if;
end process;
FSM_INST : process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
board_detected_o <= '0';
fsm_state <= INIT;
else
case fsm_state is
when INIT =>
board_detected_o <= '0';
bit_position <= 0;
fsm_state <= WRITE_BIT;
error_detected <= '0';
when WRITE_BIT =>
loopback_o <= g_pattern(bit_position);
if (clk_en = '1') then
fsm_state <= READ_BIT;
end if;
when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then
fsm_state <= DONE;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
end if;
else
error_detected <= '1';
fsm_state <= DONE;
end if;
when DONE =>
board_detected_o <= not error_detected;
when others =>
fsm_state <= INIT;
end case;
end if;
end if;
end process;
end Behavioral;
......@@ -46,6 +46,7 @@ entity wrsw_rt_subsystem is
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port(
......@@ -54,8 +55,8 @@ entity wrsw_rt_subsystem is
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -124,6 +125,24 @@ entity wrsw_rt_subsystem is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
------------------------------------------------------
-- WRS Low jitter daughterboard
------------------------------------------------------
ljd_loopback_i : in std_logic := '0';
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'0');
-- LJD AD9516
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
......@@ -137,8 +156,8 @@ architecture rtl of wrsw_rt_subsystem is
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_num_exts : integer;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean;
g_ref_clock_rate : integer;
......@@ -155,8 +174,9 @@ architecture rtl of wrsw_rt_subsystem is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_rst_o : out std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -201,8 +221,8 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 8;
constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -215,7 +235,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -251,6 +271,9 @@ architecture rtl of wrsw_rt_subsystem is
end if;
end f_pick;
signal ljd_board_detected : std_logic;
signal ext_pll_locked : std_logic;
signal ext_pll_reset : std_logic;
begin -- rtl
......@@ -326,8 +349,8 @@ begin -- rtl
g_address_granularity => BYTE,
g_num_ref_inputs => g_num_rx_clocks,
g_num_outputs => 1,
g_num_exts => g_num_ext_clks,
g_reverse_dmtds => true,
g_with_ext_clock_input => true,
g_divide_input_by_2 => false,
g_with_debug_fifo => true,
g_ref_clock_rate => 62500000,
......@@ -342,9 +365,10 @@ begin -- rtl
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
pps_csync_p1_i => pps_csync,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => ext_pll_locked,
clk_ext_rst_o => ext_pll_reset,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
dac_dmtd_load_o => dac_dmtd_load,
......@@ -405,6 +429,25 @@ begin -- rtl
pad_mosi_o => pll_mosi_o,
pad_miso_i => pll_miso_i);
U_SPI_Master_external_board : xwb_spi
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_divider_len => 8,
g_max_char_len => 24,
g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open,
pad_cs_o(0) => ljd_pll_cs_n_o,
pad_sclk_o => ljd_pll_sck_o,
pad_mosi_o => ljd_pll_mosi_o,
pad_miso_i => ljd_pll_miso_i);
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
......@@ -456,6 +499,10 @@ begin -- rtl
pll_reset_n_o <= gpio_out(1);
cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
rst_n_o <= gpio_out(3);
gpio_in(4) <= ljd_board_detected;
gpio_in(7 downto 5) <= ljd_osc_freq_i;
U_Main_DAC : gc_serial_dac
generic map (
......@@ -491,5 +538,30 @@ begin -- rtl
dac_sclk_o => dac_helper_sclk_o,
dac_sdata_o => dac_helper_data_o);
------------------------------------------------------
-- WRS Low jitter daughterboard
------------------------------------------------------
ljd_clk1_en <= '1';
ljd_clk2_en <= '1';
ljd_pll_sync_n_o <= '1';
-- Detect the Low Jitter Daughterboard
ljd_detect_inst : entity work.wrsw_ljd_detect
generic map (
g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D")
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
loopback_i => ljd_loopback_i,
loopback_o => ljd_loopback_o,
board_detected_o => ljd_board_detected);
ljd_detected_o <= ljd_board_detected;
ext_pll_locked <= ljd_pll_locked_i when(ljd_board_detected = '1') else
clk_ext_mul_locked_i;
ljd_pll_reset_n_o <= not ext_pll_reset when(ljd_board_detected = '1') else
'1';
end rtl;
......@@ -79,6 +79,7 @@ port
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_100_to_62m;
......@@ -178,7 +179,7 @@ begin
LOCKED => locked_o,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
PWRDWN => powerdown_i,
RST => rst_a_i);
-- Output buffering
......
......@@ -79,6 +79,7 @@ port
clk_ext_100_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_100;
......@@ -178,7 +179,7 @@ begin
LOCKED => locked_o,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
PWRDWN => powerdown_i,
RST => rst_a_i);
-- Output buffering
......
This source diff could not be displayed because it is too large. You can view the blob instead.
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<DesignStrategy goal="Minimum Runtime" strategy="Runtime Reduction with Multi-Threading" version="12.1">
<Description>This strategy will minimize runtime. This strategy will not optimize for timing performance.</Description>
<DeviceList devices="virtex6"/>
<Properties>
<property name="Synthesize - XST:Read Cores" value="false"/>
<property name="Map:Placer Effort Level" value="High"/>
<property name="Map:Placer Extra Effort" value="Normal"/>
<property name="Map:Starting Placer Cost Table (1-100)" value="40"/>
<property name="Map:Timing Mode" value="Performance Evaluation"/>
<property name="Map:Pack I/O Registers/Latches into IOBs" value="For Outputs Only"/>
<property name="Map:LUT Combining" value="Auto"/>
<property name="Map:Power Reduction" value="Off"/>
<property name="Map:Enable Multi-Threading" value="2"/>
<property name="Place &amp; Route:Place &amp; Route Effort Level (Overall)" value="High"/>
<property name="Place &amp; Route:Timing Mode" value="Performance Evaluation"/>
<property name="Place &amp; Route:Enable Multi-Threading" value="4"/>
<property name="Generate Programming File:Create Bit File" value="true"/>
<property name="Generate Programming File:Create Binary Configuration File" value="true"/>
</Properties>
</DesignStrategy>
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -82,7 +82,7 @@ entity scb_top_bare is
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
......@@ -114,10 +114,9 @@ entity scb_top_bare is
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
......@@ -133,6 +132,28 @@ entity scb_top_bare is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- Low Jitter Daughterboard support
-------------------------------------------------------------------------------
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
-- LJD AD9516
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
-------------------------------------------------------------------------------
-- Misc pins
-------------------------------------------------------------------------------
......@@ -442,6 +463,11 @@ architecture rtl of scb_top_bare is
signal nic_rtu_rsp : t_rtu_response;
signal nic_rtu_ack : std_logic;
signal ljd_detected : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
begin
......@@ -576,6 +602,7 @@ begin
U_RT_Subsystem : wrsw_rt_subsystem
generic map (
g_num_rx_clocks => c_NUM_PORTS,
g_num_ext_clks => 2,
g_simulation => g_simulation)
port map (
clk_ref_i => clk_ref_i,
......@@ -583,8 +610,8 @@ begin
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
......@@ -599,9 +626,9 @@ begin
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
......@@ -628,6 +655,21 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ljd_loopback_i => ljd_loopback_i,
ljd_loopback_o => ljd_loopback_o,
ljd_clk1_en => ljd_clk1_en,
ljd_clk2_en => ljd_clk2_en,
ljd_detected_o => ljd_detected,
ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
ljd_pll_sck_o => ljd_pll_sck_o,
ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
ljd_pll_locked_i => ljd_pll_locked_i,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
......@@ -1269,5 +1311,31 @@ begin
T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
end generate;
-------------------------------------------------------------------------------
-- WRS Low jitter daughterboard
-------------------------------------------------------------------------------
ljd_detected_o <= ljd_detected;
-- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ljd_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ljd_dac_main_sync_n_o <= '0';
ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ljd_dac_main_sync_n_o <= dac_main_sync_n;
ljd_dac_main_sclk_o <= dac_main_sclk;
ljd_dac_main_data_o <= dac_main_data;
end if;
end process;
end rtl;
......@@ -237,7 +237,7 @@ package wrs_sdb_pkg is
name => "WRSW SWCORE ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -245,7 +245,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
......@@ -206,14 +206,16 @@ package wrsw_components_pkg is
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer);
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -243,13 +245,27 @@ package wrsw_components_pkg is
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic);
end component;
component chipscope_icon
......
......@@ -207,6 +207,7 @@ package wrsw_top_pkg is
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port (
clk_ref_i : in std_logic;
......@@ -214,7 +215,7 @@ package wrsw_top_pkg is
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -254,6 +255,19 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -292,8 +306,8 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -306,6 +320,22 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......
......@@ -16,6 +16,29 @@ NET "clk_aux_n_o" LOC=C19;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
NET "ext_clk_10mhz_p_i" LOC = AF30;
NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ljd_clk_62mhz_p_i" LOC = AN33;
NET "ljd_clk_62mhz_n_i" LOC = AN34;
NET "ljd_rev_id_i[0]" LOC = AE29;
NET "ljd_rev_id_i[1]" LOC = AE28;
NET "ljd_rev_id_i[2]" LOC = AM32;
NET "ljd_osc_freq_i[0]" LOC = AN32;
NET "ljd_osc_freq_i[1]" LOC = AP33;
NET "ljd_osc_freq_i[2]" LOC = AP32;
NET "ljd_clk1_en" LOC = AL31;
NET "ljd_clk2_en" LOC = AK31;
NET "ljd_loopback_i" LOC = AM31;
NET "ljd_loopback_o" LOC = AL30;
NET "ljd_pll_locked_i" LOC = AH33;
#EBI BUS
#NET "cpu_clk_i" LOC="";
......@@ -96,6 +119,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "ljd_dac_main_sync_n_o" LOC = AH32;
NET "ljd_dac_main_sclk_o" LOC = AK32;
NET "ljd_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
......@@ -105,6 +131,14 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ljd_pll_cs_n_o" LOC = AD27;
NET "ljd_pll_sck_o" LOC = AD26;
NET "ljd_pll_mosi_o" LOC = AE27;
NET "ljd_pll_miso_i" LOC = AF28;