Commit ebe9d4c9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'greg-low-jitter' into proposed_master

parents 31787035 76eaac7d
Subproject commit f73f8239488db55089b83fd5a111cb550f03a5c1
Subproject commit 8478786f1ed97c507e2f5d04219a5ebc9a31e708
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd", "gen10_wishbone_slave.vhd"]
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd",
"gen10_wishbone_slave.vhd", "wrsw_ljd_detect.vhd"]
-------------------------------------------------------------------------------
-- Title : wrsw_ljd_detect
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_ljd_detect.vhd
-- Author : Mattia Rzzi
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- FSM to check the presence of the WRS Low jitter daughterboard
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2016 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrsw_top_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity wrsw_ljd_detect is
generic (
g_pattern : std_logic_vector(63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
loopback_i : in std_logic;
loopback_o : out std_logic;
board_detected_o : out std_logic
);
end wrsw_ljd_detect;
architecture Behavioral of wrsw_ljd_detect is
signal clk_divider : integer range 0 to g_clk_divider-1;
signal clk_en : std_logic;
signal bit_position : integer range 0 to g_pattern'length-1;
signal error_detected : std_logic;
type fsm_states is (INIT, WRITE_BIT, READ_BIT, DONE);
signal fsm_state : fsm_states := INIT;
begin
clock_divider_inst : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
clk_divider <= clk_divider + 1;
if (clk_divider = g_clk_divider - 1) then
clk_divider <= 0;
clk_en <= '1';
else
clk_en <= '0';
end if;
end if;
end process;
FSM_INST : process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
board_detected_o <= '0';
fsm_state <= INIT;
else
case fsm_state is
when INIT =>
board_detected_o <= '0';
bit_position <= 0;
fsm_state <= WRITE_BIT;
error_detected <= '0';
when WRITE_BIT =>
loopback_o <= g_pattern(bit_position);
if (clk_en = '1') then
fsm_state <= READ_BIT;
end if;
when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then
fsm_state <= DONE;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
end if;
else
error_detected <= '1';
fsm_state <= DONE;
end if;
when DONE =>
board_detected_o <= not error_detected;
when others =>
fsm_state <= INIT;
end case;
end if;
end if;
end process;
end Behavioral;
......@@ -46,6 +46,7 @@ entity wrsw_rt_subsystem is
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port(
......@@ -54,7 +55,7 @@ entity wrsw_rt_subsystem is
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -125,6 +126,24 @@ entity wrsw_rt_subsystem is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
------------------------------------------------------
-- WRS Low jitter daughterboard
------------------------------------------------------
ljd_loopback_i : in std_logic := '0';
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'0');
-- LJD AD9516
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
);
......@@ -137,8 +156,8 @@ architecture rtl of wrsw_rt_subsystem is
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_num_exts : integer;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean;
g_ref_clock_rate : integer;
......@@ -155,8 +174,9 @@ architecture rtl of wrsw_rt_subsystem is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_rst_o : out std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -201,8 +221,8 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 8;
constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -215,7 +235,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -251,6 +271,9 @@ architecture rtl of wrsw_rt_subsystem is
end if;
end f_pick;
signal ljd_board_detected : std_logic;
signal ext_pll_locked : std_logic;
signal ext_pll_reset : std_logic;
begin -- rtl
......@@ -326,8 +349,8 @@ begin -- rtl
g_address_granularity => BYTE,
g_num_ref_inputs => g_num_rx_clocks,
g_num_outputs => 1,
g_num_exts => g_num_ext_clks,
g_reverse_dmtds => true,
g_with_ext_clock_input => true,
g_divide_input_by_2 => false,
g_with_debug_fifo => true,
g_ref_clock_rate => 62500000,
......@@ -343,7 +366,8 @@ begin -- rtl
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_mul_locked_i => ext_pll_locked,
clk_ext_rst_o => ext_pll_reset,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
......@@ -405,6 +429,25 @@ begin -- rtl
pad_mosi_o => pll_mosi_o,
pad_miso_i => pll_miso_i);
U_SPI_Master_external_board : xwb_spi
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_divider_len => 8,
g_max_char_len => 24,
g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open,
pad_cs_o(0) => ljd_pll_cs_n_o,
pad_sclk_o => ljd_pll_sck_o,
pad_mosi_o => ljd_pll_mosi_o,
pad_miso_i => ljd_pll_miso_i);
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
......@@ -457,6 +500,10 @@ begin -- rtl
cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
rst_n_o <= gpio_out(3);
gpio_in(4) <= ljd_board_detected;
gpio_in(7 downto 5) <= ljd_osc_freq_i;
U_Main_DAC : gc_serial_dac
generic map (
g_num_data_bits => 16,
......@@ -491,5 +538,30 @@ begin -- rtl
dac_sclk_o => dac_helper_sclk_o,
dac_sdata_o => dac_helper_data_o);
------------------------------------------------------
-- WRS Low jitter daughterboard
------------------------------------------------------
ljd_clk1_en <= '1';
ljd_clk2_en <= '1';
ljd_pll_sync_n_o <= '1';
-- Detect the Low Jitter Daughterboard
ljd_detect_inst : entity work.wrsw_ljd_detect
generic map (
g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D")
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
loopback_i => ljd_loopback_i,
loopback_o => ljd_loopback_o,
board_detected_o => ljd_board_detected);
ljd_detected_o <= ljd_board_detected;
ext_pll_locked <= ljd_pll_locked_i when(ljd_board_detected = '1') else
clk_ext_mul_locked_i;
ljd_pll_reset_n_o <= not ext_pll_reset when(ljd_board_detected = '1') else
'1';
end rtl;
......@@ -79,6 +79,7 @@ port
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_100_to_62m;
......@@ -178,7 +179,7 @@ begin
LOCKED => locked_o,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
PWRDWN => powerdown_i,
RST => rst_a_i);
-- Output buffering
......
......@@ -79,6 +79,7 @@ port
clk_ext_100_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_100;
......@@ -178,7 +179,7 @@ begin
LOCKED => locked_o,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
PWRDWN => powerdown_i,
RST => rst_a_i);
-- Output buffering
......
This source diff could not be displayed because it is too large. You can view the blob instead.
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<DesignStrategy goal="Minimum Runtime" strategy="Runtime Reduction with Multi-Threading" version="12.1">
<Description>This strategy will minimize runtime. This strategy will not optimize for timing performance.</Description>
<DeviceList devices="virtex6"/>
<Properties>
<property name="Synthesize - XST:Read Cores" value="false"/>
<property name="Map:Placer Effort Level" value="High"/>
<property name="Map:Placer Extra Effort" value="Normal"/>
<property name="Map:Starting Placer Cost Table (1-100)" value="40"/>
<property name="Map:Timing Mode" value="Performance Evaluation"/>
<property name="Map:Pack I/O Registers/Latches into IOBs" value="For Outputs Only"/>
<property name="Map:LUT Combining" value="Auto"/>
<property name="Map:Power Reduction" value="Off"/>
<property name="Map:Enable Multi-Threading" value="2"/>
<property name="Place &amp; Route:Place &amp; Route Effort Level (Overall)" value="High"/>
<property name="Place &amp; Route:Timing Mode" value="Performance Evaluation"/>
<property name="Place &amp; Route:Enable Multi-Threading" value="4"/>
<property name="Generate Programming File:Create Bit File" value="true"/>
<property name="Generate Programming File:Create Binary Configuration File" value="true"/>
</Properties>
</DesignStrategy>
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -82,7 +82,7 @@ entity scb_top_bare is
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
......@@ -114,7 +114,6 @@ entity scb_top_bare is
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
......@@ -133,6 +132,28 @@ entity scb_top_bare is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- Low Jitter Daughterboard support
-------------------------------------------------------------------------------
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
-- LJD AD9516
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
-------------------------------------------------------------------------------
-- Misc pins
-------------------------------------------------------------------------------
......@@ -443,6 +464,11 @@ architecture rtl of scb_top_bare is
signal nic_rtu_rsp : t_rtu_response;
signal nic_rtu_ack : std_logic;
signal ljd_detected : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
begin
......@@ -576,6 +602,7 @@ begin
U_RT_Subsystem : wrsw_rt_subsystem
generic map (
g_num_rx_clocks => c_NUM_PORTS,
g_num_ext_clks => 2,
g_simulation => g_simulation)
port map (
clk_ref_i => clk_ref_i,
......@@ -599,9 +626,9 @@ begin
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
......@@ -628,6 +655,21 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ljd_loopback_i => ljd_loopback_i,
ljd_loopback_o => ljd_loopback_o,
ljd_clk1_en => ljd_clk1_en,
ljd_clk2_en => ljd_clk2_en,
ljd_detected_o => ljd_detected,
ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
ljd_pll_sck_o => ljd_pll_sck_o,
ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
ljd_pll_locked_i => ljd_pll_locked_i,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
......@@ -1270,4 +1312,30 @@ begin
T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
end generate;
-------------------------------------------------------------------------------
-- WRS Low jitter daughterboard
-------------------------------------------------------------------------------
ljd_detected_o <= ljd_detected;
-- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ljd_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ljd_dac_main_sync_n_o <= '0';
ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ljd_dac_main_sync_n_o <= dac_main_sync_n;
ljd_dac_main_sclk_o <= dac_main_sclk;
ljd_dac_main_data_o <= dac_main_data;
end if;
end process;
end rtl;
......@@ -237,7 +237,7 @@ package wrs_sdb_pkg is
name => "WRSW SWCORE ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -245,7 +245,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
......@@ -206,14 +206,16 @@ package wrsw_components_pkg is
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer);
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -243,13 +245,27 @@ package wrsw_components_pkg is
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic);
end component;
component chipscope_icon
......
......@@ -207,6 +207,7 @@ package wrsw_top_pkg is
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port (
clk_ref_i : in std_logic;
......@@ -214,7 +215,7 @@ package wrsw_top_pkg is
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -254,6 +255,19 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -292,8 +306,8 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -306,6 +320,22 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......
......@@ -16,6 +16,29 @@ NET "clk_aux_n_o" LOC=C19;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
NET "ext_clk_10mhz_p_i" LOC = AF30;
NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ljd_clk_62mhz_p_i" LOC = AN33;
NET "ljd_clk_62mhz_n_i" LOC = AN34;
NET "ljd_rev_id_i[0]" LOC = AE29;
NET "ljd_rev_id_i[1]" LOC = AE28;
NET "ljd_rev_id_i[2]" LOC = AM32;
NET "ljd_osc_freq_i[0]" LOC = AN32;
NET "ljd_osc_freq_i[1]" LOC = AP33;
NET "ljd_osc_freq_i[2]" LOC = AP32;
NET "ljd_clk1_en" LOC = AL31;
NET "ljd_clk2_en" LOC = AK31;
NET "ljd_loopback_i" LOC = AM31;
NET "ljd_loopback_o" LOC = AL30;
NET "ljd_pll_locked_i" LOC = AH33;
#EBI BUS
#NET "cpu_clk_i" LOC="";
......@@ -96,6 +119,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "ljd_dac_main_sync_n_o" LOC = AH32;
NET "ljd_dac_main_sclk_o" LOC = AK32;
NET "ljd_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
......@@ -105,6 +131,14 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ljd_pll_cs_n_o" LOC = AD27;
NET "ljd_pll_sck_o" LOC = AD26;
NET "ljd_pll_mosi_o" LOC = AE27;
NET "ljd_pll_miso_i" LOC = AF28;
NET "ljd_pll_reset_n_o" LOC = AF29;
NET "ljd_pll_status_i" LOC = AD25;
NET "ljd_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11";
......@@ -301,6 +335,16 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i";
TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i";
TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
NET "from_phys[0]_rx_clk" TNM="phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM="phy_rx_clocks";
......@@ -344,6 +388,21 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
#INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
......@@ -628,6 +687,9 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
......
......@@ -129,6 +129,36 @@ entity scb_top_synthesis is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- WRS Low Jitter board
-------------------------------------------------------------------------------
ext_clk_10mhz_p_i : in std_logic;
ext_clk_10mhz_n_i : in std_logic;
ljd_clk_62mhz_p_i : in std_logic;
ljd_clk_62mhz_n_i : in std_logic;
ljd_pll_status_i : in std_logic;
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_rev_id_i : in std_logic_vector (2 downto 0);
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
......@@ -201,6 +231,7 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_i : in std_logic;
clk_ext_100_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -209,10 +240,10 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_100_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
constant c_NUM_PHYS : integer := 18;
constant c_NUM_PORTS : integer := 18;
......@@ -294,9 +325,14 @@ architecture Behavioral of scb_top_synthesis is
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_mul_vec : std_logic_vector(1 downto 0);
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ljd_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic;
component scb_top_bare
generic (
......@@ -316,10 +352,11 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -333,6 +370,22 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -386,7 +439,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
......@@ -479,6 +531,50 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_ljd_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ljd_clk_62mhz,
I => ljd_clk_62mhz_p_i,
IB => ljd_clk_62mhz_n_i);
U_Buf_ljd_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ljd_clk_62mhz,
O => ljd_clk_62mhz_bufr);
U_Buf_ext_clk10mhz : IBUFDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_10MHz,
I => ext_clk_10mhz_p_i,
IB => ext_clk_10mhz_n_i);
CLK_10MHZ_ext : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_10MHz,
O => ext_clk_10MHz_bufr);
BUFGMUX_inst : BUFGCTRL
port map (
IGNORE0 => '0',
IGNORE1 => '0',
CE0 => '1',
CE1 => '1',
O => clk_10mhz,
I0 => clk_ext,
I1 => ext_clk_10MHz_bufr,
S1 => ljd_detected,
S0 => NOT ljd_detected);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
DIFF_TERM => true,
......@@ -522,7 +618,6 @@ begin
CLKFBIN => pllout_clk_fb,
CLKIN => clk_25mhz);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
......@@ -534,6 +629,7 @@ begin
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
powerdown_i => ljd_detected,
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
......@@ -541,9 +637,12 @@ begin
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
powerdown_i => ljd_detected,
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
......@@ -710,7 +809,7 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_i => clk_ext_mul_vec,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -726,7 +825,25 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
-- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ljd_dac_main_sclk_o,
ljd_dac_main_data_o => ljd_dac_main_data_o,
ljd_loopback_i => ljd_loopback_i,
ljd_loopback_o => ljd_loopback_o,
ljd_clk1_en => ljd_clk1_en,
ljd_clk2_en => ljd_clk2_en,
ljd_detected_o => ljd_detected,
ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
ljd_pll_sck_o => ljd_pll_sck_o,
ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
ljd_pll_locked_i => ljd_pll_locked_i,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
......@@ -12,12 +12,34 @@ NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_aux_p_o" LOC=B20;
NET "clk_aux_n_o" LOC=C19;
NET "clk_500_o" LOC=AM33;
NET "clk_sys_dbg_o" LOC=AL33;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
NET "ext_clk_10mhz_p_i" LOC = AF30;
NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ljd_clk_62mhz_p_i" LOC = AN33;
NET "ljd_clk_62mhz_n_i" LOC = AN34;
NET "ljd_rev_id_i[0]" LOC = AE29;
NET "ljd_rev_id_i[1]" LOC = AE28;
NET "ljd_rev_id_i[2]" LOC = AM32;
NET "ljd_osc_freq_i[0]" LOC = AN32;
NET "ljd_osc_freq_i[1]" LOC = AP33;
NET "ljd_osc_freq_i[2]" LOC = AP32;
NET "ljd_clk1_en" LOC = AL31;
NET "ljd_clk2_en" LOC = AK31;
NET "ljd_loopback_i" LOC = AM31;
NET "ljd_loopback_o" LOC = AL30;
NET "ljd_pll_locked_i" LOC = AH33;
#NET "dbg_clk_ext_o" LOC=AM33;
#NET "spll_dbg_o<0>" LOC=AL33;
#NET "spll_dbg_o<1>" LOC=AE29;
......@@ -25,7 +47,6 @@ NET "sensors_sda_b" LOC=H14;
#NET "spll_dbg_o<3>" LOC=AM32;
#NET "spll_dbg_o<4>" LOC=AN32;
#NET "spll_dbg_o<5>" LOC=AP33;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
......@@ -105,6 +126,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "ljd_dac_main_sync_n_o" LOC = AH32;
NET "ljd_dac_main_sclk_o" LOC = AK32;
NET "ljd_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
......@@ -114,6 +138,14 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ljd_pll_cs_n_o" LOC = AD27;
NET "ljd_pll_sck_o" LOC = AD26;
NET "ljd_pll_mosi_o" LOC = AE27;
NET "ljd_pll_miso_i" LOC = AF28;
NET "ljd_pll_reset_n_o" LOC = AF29;
NET "ljd_pll_status_i" LOC = AD25;
NET "ljd_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11";
......@@ -123,16 +155,12 @@ NET "clk_sel_o" LOC="AK17";
### GTX PORTS - reversed to match MB port ordering ###
#NET "gtx0_3_clk_n_i" LOC="AK5";
#NET "gtx0_3_clk_p_i" LOC="AK6";
#NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_n_i" LOC="AD5";
#NET "gtx4_7_clk_p_i" LOC="AD6";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_n_i" LOC="V5";
NET "gtx8_11_clk_p_i" LOC="V6";
......@@ -154,64 +182,44 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[0]" LOC="AP6";
#NET "gtx_txp_o[0]" LOC="AP1";
#NET "gtx_txn_o[0]" LOC="AP2";
#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[1]" LOC="AM6";
#NET "gtx_txp_o[1]" LOC="AN3";
#NET "gtx_txn_o[1]" LOC="AN4";
#NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
#NET "gtx_rxn_i[2]" LOC="AL4";
#NET "gtx_txp_o[2]" LOC="AM1";
#NET "gtx_txn_o[2]" LOC="AM2";
#NET "gtx_rxp_i[3]" LOC="AJ3";
#NET "gtx_rxn_i[3]" LOC="AJ4";
#NET "gtx_txp_o[3]" LOC="AK1";
#NET "gtx_txn_o[3]" LOC="AK2";
#NET "gtx_rxp_i[4]" LOC="AG3";
#NET "gtx_rxn_i[4]" LOC="AG4";
#NET "gtx_txp_o[4]" LOC="AH1";
#NET "gtx_txn_o[4]" LOC="AH2";
#NET "gtx_rxp_i[5]" LOC="AF5";
#NET "gtx_rxn_i[5]" LOC="AF6";
#NET "gtx_txp_o[5]" LOC="AF1";
#NET "gtx_txn_o[5]" LOC="AF2";
#NET "gtx_rxp_i[6]" LOC="AE3";
#NET "gtx_rxn_i[6]" LOC="AE4";
#NET "gtx_txp_o[6]" LOC="AD1";
#NET "gtx_txn_o[6]" LOC="AD2";
#NET "gtx_rxp_i[7]" LOC="AC3";
#NET "gtx_rxn_i[7]" LOC="AC4";
#NET "gtx_txp_o[7]" LOC="AB1";
#NET "gtx_txn_o[7]" LOC="AB2";
#NET "gtx_rxp_i[8]" LOC="AA3";
#NET "gtx_rxn_i[8]" LOC="AA4";
#NET "gtx_txp_o[8]" LOC="Y1";
#NET "gtx_txn_o[8]" LOC="Y2";
#NET "gtx_rxp_i[9]" LOC="W3";
#NET "gtx_rxn_i[9]" LOC="W4";
#NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2";
NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4";
......@@ -298,8 +306,17 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i";
TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i";
TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
......@@ -308,7 +325,6 @@ TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
#TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
......@@ -343,12 +359,10 @@ TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_re
#TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[16].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
#TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
#NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
#TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%;
#NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i;
#TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%;
#NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i;
......@@ -366,6 +380,20 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
......
......@@ -74,8 +74,6 @@ entity scb_top_synthesis is
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -129,6 +127,33 @@ entity scb_top_synthesis is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low Jitter board
ext_clk_10mhz_p_i : in std_logic;
ext_clk_10mhz_n_i : in std_logic;
ljd_clk_62mhz_p_i : in std_logic;
ljd_clk_62mhz_n_i : in std_logic;
ljd_pll_status_i : in std_logic;
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_rev_id_i : in std_logic_vector (2 downto 0);
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -188,10 +213,7 @@ entity scb_top_synthesis is
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
dbg_clk_ext_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)
mb_fan2_pwm_o : out std_logic
);
end scb_top_synthesis;
......@@ -212,6 +234,7 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_i : in std_logic;
clk_ext_100_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -220,10 +243,10 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_100_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
constant c_NUM_PHYS : integer := 8;
constant c_NUM_PORTS : integer := 8;
......@@ -302,10 +325,15 @@ architecture Behavioral of scb_top_synthesis is
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_mul_vec : std_logic_vector(1 downto 0);
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ljd_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic;
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -324,7 +352,7 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -342,6 +370,22 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -395,8 +439,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
clk_sys_dbg_o <= clk_sys;
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
......@@ -489,7 +531,50 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_ljd_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ljd_clk_62mhz,
I => ljd_clk_62mhz_p_i,
IB => ljd_clk_62mhz_n_i);
U_Buf_ljd_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ljd_clk_62mhz,
O => ljd_clk_62mhz_bufr);
U_Buf_ext_clk10mhz : IBUFDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_10MHz,
I => ext_clk_10mhz_p_i,
IB => ext_clk_10mhz_n_i);
CLK_10MHZ_ext : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_10MHz,
O => ext_clk_10MHz_bufr);
BUFGMUX_inst : BUFGCTRL
port map (
IGNORE0 => '0',
IGNORE1 => '0',
CE0 => '1',
CE1 => '1',
O => clk_10mhz,
I0 => clk_ext,
I1 => ext_clk_10MHz_bufr,
S1 => ljd_detected,
S0 => NOT ljd_detected
);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
......@@ -534,7 +619,6 @@ begin
CLKFBIN => pllout_clk_fb,
CLKIN => clk_25mhz);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
......@@ -546,6 +630,7 @@ begin
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
powerdown_i => ljd_detected,
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
......@@ -553,10 +638,13 @@ begin
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
powerdown_i => ljd_detected,
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
dbg_clk_ext_o <= clk_ext_mul;
clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
--dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
......@@ -724,11 +812,11 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_i => clk_ext_mul_vec,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
-- clk_500_o => clk_500_o,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
......@@ -741,7 +829,25 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
-- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ljd_dac_main_sclk_o,
ljd_dac_main_data_o => ljd_dac_main_data_o,
ljd_loopback_i => ljd_loopback_i,
ljd_loopback_o => ljd_loopback_o,
ljd_clk1_en => ljd_clk1_en,
ljd_clk2_en => ljd_clk2_en,
ljd_detected_o => ljd_detected,
ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
ljd_pll_sck_o => ljd_pll_sck_o,
ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
ljd_pll_locked_i => ljd_pll_locked_i,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......@@ -766,8 +872,7 @@ begin
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => spll_dbg_o);
mb_fan2_pwm_o => mb_fan2_pwm_o);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
......
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