Commit f61f00f4 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

adding configurable 10MHz generation for wrs hw 3.4

parent d3814979
wr-cores @ a9cf9115
Subproject commit de3d1970e3904a034c9ee0471862242f1833ae65
Subproject commit a9cf9115e07f9707c1653ee4a6d2e0afb3f179ce
files = ["wrsw_rt_subsystem.vhd"]
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd", "gen10_wishbone_slave.vhd"]
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Switch aux clock generation module
---------------------------------------------------------------------------------------
-- File : gen10_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrsw_gen_10mhz.wb
-- Created : Wed Dec 3 13:36:18 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_gen_10mhz.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gen10_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_gen10_in_registers is record
psr_cur_val_i : std_logic_vector(4 downto 0);
psr_lck_i : std_logic;
end record;
constant c_gen10_in_registers_init_value: t_gen10_in_registers := (
psr_cur_val_i => (others => '0'),
psr_lck_i => '0'
);
-- Output registers (WB slave -> user design)
type t_gen10_out_registers is record
pr_hp_width_o : std_logic_vector(15 downto 0);
pr_hp_width_wr_o : std_logic;
dcr_low_width_o : std_logic_vector(15 downto 0);
dcr_low_width_wr_o : std_logic;
csr_o : std_logic_vector(15 downto 0);
csr_wr_o : std_logic;
psr_set_val_o : std_logic_vector(4 downto 0);
psr_set_val_wr_o : std_logic;
end record;
constant c_gen10_out_registers_init_value: t_gen10_out_registers := (
pr_hp_width_o => (others => '0'),
pr_hp_width_wr_o => '0',
dcr_low_width_o => (others => '0'),
dcr_low_width_wr_o => '0',
csr_o => (others => '0'),
csr_wr_o => '0',
psr_set_val_o => (others => '0'),
psr_set_val_wr_o => '0'
);
function "or" (left, right: t_gen10_in_registers) return t_gen10_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body gen10_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_gen10_in_registers) return t_gen10_in_registers is
variable tmp: t_gen10_in_registers;
begin
tmp.psr_cur_val_i := f_x_to_zero(left.psr_cur_val_i) or f_x_to_zero(right.psr_cur_val_i);
tmp.psr_lck_i := f_x_to_zero(left.psr_lck_i) or f_x_to_zero(right.psr_lck_i);
return tmp;
end function;
end package body;
This diff is collapsed.
-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit 10 MHz Clock Generation
-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
peripheral {
name = "WR Switch aux clock generation module";
decription = "The module allows gerating WR-aligned clock of a given \
frequency, duty cycle and phase. By default it is configured to generate 10MHz \
signal.";
hdl_entity = "gen10_wishbone_slave";
prefix = "gen10";
reg {
name = "Period Register";
prefix = "PR";
field {
name = "Half period width";
description = "Defined as a number of 2ns cycles.";
prefix = "HP_WIDTH";
size = 16;
type = PASS_THROUGH;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Duty Cycle Register";
prefix = "DCR";
field {
name = "Low state width";
description = "Defined as a number of 2ns cycles. \
Used together with PR register can be used to generate a square wave with a duty \
cycle different than 0,5.";
prefix = "LOW_WIDTH";
size = 16;
type = PASS_THROUGH;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Coarse Shift Register";
prefix = "CSR";
field {
name = "Coarse shift value in 2ns cycles.";
description = "MUST be not larger than the required clock period";
size = 16;
type = PASS_THROUGH;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Precise Shift Register";
prefix = "PSR";
field {
name = "Required precise shift value in taps fed to IODelay";
prefix = "SET_VAL";
size = 5;
type = PASS_THROUGH;
access_dev = READ_ONLY;
access_bus = WRITE_ONLY;
};
field {
name = "Current precise shift read from IODelay";
prefix = "CUR_VAL";
align = 16;
size = 5;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "IOdelay locked";
prefix = "LCK";
align = 31;
size = 1;
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
}
......@@ -55,6 +55,8 @@ entity wrsw_rt_subsystem is
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
......@@ -177,6 +179,20 @@ architecture rtl of wrsw_rt_subsystem is
tm_time_valid_o : out std_logic);
end component;
component xwrsw_gen_10mhz
generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
pps_i : in std_logic;
pps_valid_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component;
-- interconnect layout:
......@@ -188,7 +204,7 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 7;
constant c_NUM_WB_SLAVES : integer := 8;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -200,7 +216,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_GPIO : integer := 4;
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
......@@ -222,6 +238,7 @@ architecture rtl of wrsw_rt_subsystem is
signal clk_rx_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal pps_csync : std_logic;
signal pps_valid : std_logic;
function f_pick (
cond : boolean;
......@@ -355,12 +372,13 @@ begin -- rtl
pps_in_i => pps_ext_i,
pps_csync_o => pps_csync,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid_o,
pps_valid_o => pps_valid,
tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o);
pps_csync_o <= pps_csync;
pps_valid_o <= pps_valid;
cpu_irq_vec(0) <= cnx_master_in(2).int;
cpu_irq_vec(31 downto 1) <= (others => '0');
......@@ -400,8 +418,6 @@ begin -- rtl
gpio_in_i => gpio_in,
gpio_oen_o => open);
U_Timer : xwb_tics
generic map (
g_interface_mode => PIPELINED,
......@@ -413,6 +429,20 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_TIMER),
slave_o => cnx_master_in(c_SLAVE_TIMER),
desc_o => open);
U_GEN_10_MHZ: xwrsw_gen_10mhz
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
rst_n_i => rst_n_i,
clk_i => clk_ref_i,
pps_i => pps_csync,
pps_valid_i => pps_valid,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
slave_i => cnx_master_out(c_SLAVE_GEN10),
slave_o => cnx_master_in(c_SLAVE_GEN10));
sel_clk_sys_o <= gpio_out(0);
pll_reset_n_o <= gpio_out(1);
......
-------------------------------------------------------------------------------
-- Title : Auxiliary clock generation (10MHz by default)
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : xwrsw_gen_10mhz.vhd
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2014-12-01
-- Last update: 2014-12-01
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Module used to generate aux clock of configured frequency and phase. It can
-- be used with WRS hardware >= 3.4. The clk_aux_p/n_o is there wired to CLK2
-- SMC connector on the front panel. By default 10MHz signal is generated.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-12-01 1.0 greg.d Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gen10_wbgen2_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity xwrsw_gen_10mhz is
generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
pps_i : in std_logic;
pps_valid_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out);
attribute maxdelay : string;
attribute maxdelay of pps_i : signal is "500 ps";
end xwrsw_gen_10mhz;
architecture behav of xwrsw_gen_10mhz is
component gen10_wishbone_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_gen10_in_registers;
regs_o : out t_gen10_out_registers);
end component;
component pll_62_5_500mhz is
port(
clk_ref_i : in std_logic;
clk_500_o : out std_logic;
CLKFB_IN : in std_logic;
CLKFB_OUT : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic);
end component;
component oserdes_8_to_1 is
generic(
sys_w : integer := 1;
dev_w : integer := 8);
port(
DATA_OUT_FROM_DEVICE : in std_logic_vector(dev_w-1 downto 0);
DATA_OUT_TO_PINS_P : out std_logic_vector(sys_w-1 downto 0);
DATA_OUT_TO_PINS_N : out std_logic_vector(sys_w-1 downto 0);
DELAY_RESET : in std_logic;
DELAY_DATA_CE : in std_logic_vector(sys_w -1 downto 0);
DELAY_DATA_INC : in std_logic_vector(sys_w -1 downto 0);
DELAY_TAP_IN : in std_logic_vector(5*sys_w -1 downto 0);
DELAY_TAP_OUT : out std_logic_vector(5*sys_w -1 downto 0);
DELAY_LOCKED : out std_logic;
REF_CLOCK : in std_logic;
CLK_IN : in std_logic;
CLK_DIV_IN : in std_logic;
IO_RESET : in std_logic);
end component;
constant c_DATA_W : integer := 8; -- parallel data width going to serdes
constant c_HALF : integer := 25;-- default high/low width for 10MHz
signal clk_500 : std_logic;
signal clk_fb : std_logic;
signal clk_fb_buf : std_logic;
signal rst : std_logic;
signal pll_locked : std_logic;
signal sd_out_p : std_logic_vector(0 downto 0);
signal sd_out_n : std_logic_vector(0 downto 0);
signal sd_data : std_logic_vector(c_DATA_W-1 downto 0);
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal aux_half_high: unsigned(15 downto 0);
signal aux_half_low : unsigned(15 downto 0);
signal aux_shift : unsigned(15 downto 0);
signal pps_valid_d : std_logic;
signal clk_realign : std_logic;
signal new_freq : std_logic;
signal wb_regs_in : t_gen10_in_registers;
signal wb_regs_out : t_gen10_out_registers;
begin
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i => slave_i,
slave_o => slave_o,
master_i => wb_out,
master_o => wb_in);
U_WB_IF: gen10_wishbone_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_in.adr(1 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o=> wb_out.stall,
regs_i => wb_regs_in,
regs_o => wb_regs_out);
process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
aux_half_high <= to_unsigned(c_HALF, aux_half_high'length);
aux_half_low <= to_unsigned(c_HALF, aux_half_low'length);
aux_shift <= (others=>'0');
new_freq <= '0';
elsif wb_regs_out.pr_hp_width_wr_o = '1' then
aux_half_high <= unsigned(wb_regs_out.pr_hp_width_o);
aux_half_low <= unsigned(wb_regs_out.pr_hp_width_o);
new_freq <= '1';
elsif wb_regs_out.dcr_low_width_wr_o = '1' then
aux_half_low <= unsigned(wb_regs_out.dcr_low_width_o);
new_freq <= '1';
elsif wb_regs_out.csr_wr_o = '1' then
aux_shift <= unsigned(wb_regs_out.csr_o);
new_freq <= '1';
else
new_freq <= '0';
end if;
end if;
end process;
rst <= not rst_n_i;
U_PLL_500: pll_62_5_500mhz
port map (
clk_ref_i => clk_i,
clk_500_o => clk_500,
CLKFB_IN => clk_fb_buf,
CLKFB_OUT => clk_fb,
RESET => rst,
LOCKED => pll_locked);
U_BUFG: BUFG
port map(
O => clk_fb_buf,
I => clk_fb);
U_10MHZ_SERDES: oserdes_8_to_1
generic map(
dev_w => c_DATA_W)
port map(
DATA_OUT_FROM_DEVICE => sd_data,
DATA_OUT_TO_PINS_P => sd_out_p,
DATA_OUT_TO_PINS_N => sd_out_n,
DELAY_RESET => wb_regs_out.psr_set_val_wr_o,
DELAY_DATA_CE => (others=>'0'),
DELAY_DATA_INC => (others=>'0'),
DELAY_TAP_IN => wb_regs_out.psr_set_val_o,
DELAY_TAP_OUT => wb_regs_in.psr_cur_val_i,
DELAY_LOCKED => wb_regs_in.psr_lck_i,
REF_CLOCK => clk_i,
CLK_IN => clk_500,
CLK_DIV_IN => clk_i,
IO_RESET => rst);
clk_aux_p_o <= sd_out_p(0);
clk_aux_n_o <= sd_out_n(0);
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst = '1' or new_freq = '1' or pll_locked = '0') then -- if new_freq or pll lost lock,
-- force alignment to next PPS
pps_valid_d <= '0';
elsif(pps_i = '1') then
pps_valid_d <= pps_valid_i;
end if;
end if;
end process;
clk_realign <= (not pps_valid_d) and pps_valid_i and pps_i;
process(clk_i)
variable rest : integer range 0 to 65535;
variable v_bit : std_logic;
begin
if rising_edge(clk_i) then
if (rst='1' or pll_locked='0' or clk_realign='1') then
if(aux_shift <= aux_half_high) then
rest := to_integer(aux_half_high - aux_shift);
v_bit := '1';
else
rest := to_integer(aux_half_low + aux_half_high - aux_shift);
v_bit := '0';
end if;
else
for i in 0 to c_DATA_W-1 loop
if(rest /= 0) then
sd_data(i) <= v_bit;
rest := rest - 1;
elsif(v_bit = '1') then
sd_data(i) <= '0';
v_bit := '0';
rest := to_integer(aux_half_low-1); -- because here we already wrote first bit
-- from this group
elsif(v_bit = '0') then
sd_data(i) <= '1';
v_bit := '1';
rest := to_integer(aux_half_high-1);
end if;
end loop;
end if;
end if;
end process;
end behav;
files = ["pll200MhZ.vhd", "ext_pll_10_to_100.vhd", "ext_pll_100_to_62m.vhd"];
files = ["pll200MhZ.vhd", "ext_pll_10_to_100.vhd", "ext_pll_100_to_62m.vhd",
"pll_62_5_500mhz.vhd", "oserdes_8_to_1.vhd"];
This diff is collapsed.
-- file: pll_62_5_500mhz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___500.000______0.000______50.0______110.037____117.286
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________62.500____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll_62_5_500mhz is
port
(-- Clock in ports
clk_ref_i : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
clk_500_o : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll_62_5_500mhz;
architecture xilinx of pll_62_5_500mhz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll_62_5_500mhz,clk_wiz_v3_6,{component_name=pll_62_5_500mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=16.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= clk_ref_i;
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 2.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => CLKFB_IN,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
CLKFB_OUT <= clkfbout;
clk_500_o <= clkout0;
end xilinx;
......@@ -83,6 +83,9 @@ entity scb_top_bare is
clk_ext_mul_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
-- Muxed system clock
clk_sys_o : out std_logic;
......@@ -496,6 +499,8 @@ begin
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
rst_n_i => rst_n_sys,
rst_n_o => rst_n_periph,
wb_i => cnx_master_out(c_SLAVE_RT_SUBSYSTEM),
......@@ -1069,7 +1074,6 @@ begin
clk_dmtd_divsel_o <= '1'; -- choose 62.5 MHz DDMTD clock
clk_sys_o <= clk_sys;
gen_muxed_CS: if g_with_muxed_CS = true generate
CS_ICON : chipscope_icon
port map (
......
......@@ -188,16 +188,33 @@ package wrs_sdb_pkg is
date => x"20140916",
name => "WRSW HWIU ")));
constant c_xwrsw_gen_10mhz : t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7",
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"4765feb0", -- echo -n "xwrsw_gen_10mhz" | md5sum - | cut -c1-8
version => x"00000001",
date => x"20141120",
name => "WRSW GEN 10MHz ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(6 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
3 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010200"), --SPI
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"));--PPSgen
constant c_rtbar_sdb_address : t_wishbone_address := x"00010600";
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
......@@ -205,6 +205,8 @@ package wrsw_components_pkg is
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_aux_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
......
......@@ -207,6 +207,8 @@ package wrsw_top_pkg is
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
......
......@@ -13,6 +13,9 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_aux_p_o" LOC=B20;
NET "clk_aux_n_o" LOC=C19;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
......
......@@ -75,6 +75,10 @@ entity scb_top_synthesis is
fpga_clk_aux_p_i : in std_logic;
fpga_clk_aux_n_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
......@@ -135,7 +139,6 @@ entity scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
-- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
clk_dmtd_divsel_o : out std_logic;
......@@ -314,6 +317,8 @@ architecture Behavioral of scb_top_synthesis is
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -709,6 +714,8 @@ begin
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
......
......@@ -13,6 +13,9 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_aux_p_o" LOC=B20;
NET "clk_aux_n_o" LOC=C19;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
......
......@@ -75,6 +75,10 @@ entity scb_top_synthesis is
fpga_clk_aux_p_i : in std_logic;
fpga_clk_aux_n_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
......@@ -318,6 +322,8 @@ architecture Behavioral of scb_top_synthesis is
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -715,6 +721,8 @@ begin
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
......
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