Skip to content

W
White Rabbit Switch - Gateware
Commit f8127017 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

ljd: move daughterboard detection inside rt subsystem 

Less code duplication in scb_8ports and scb_18ports top hdl.
parent 0e2e8d7c
Hide whitespace changes
Inline Side-by-side
Showing with 160 additions and 147 deletions
Manifest.py
View file @ f8127017
modules = { "local" : [
"modules/wrsw_rt_subsystem",
"modules/wrsw_ext_board",
"modules/wrsw_swcore",
"modules/wrsw_rtu",
"modules/wrsw_tru",
......
modules/wrsw_ext_board/Manifest.py deleted 100644 → 0
View file @ 0e2e8d7c
files = [ "wrsw_ext_board_check.vhd" ];
modules/wrsw_rt_subsystem/Manifest.py
View file @ f8127017
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd", "gen10_wishbone_slave.vhd"]
files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd",
"gen10_wishbone_slave.vhd", "wrsw_ljd_detect.vhd"]
modules/wrsw_ext_board/wrsw_ext_board_check.vhd → modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd
View file @ f8127017
-------------------------------------------------------------------------------
-- Title : wrsw_ext_board_check
-- Title : wrsw_ljd_detect
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_ext_board_check.vhd
-- File : wrsw_ljd_detect.vhd
-- Author : Mattia Rzzi
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
......@@ -45,7 +45,7 @@ use work.wrsw_top_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity wrsw_ext_board_check is
entity wrsw_ljd_detect is
generic (
g_pattern : std_logic_vector(63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16);
......@@ -56,9 +56,9 @@ entity wrsw_ext_board_check is
loopback_o : out std_logic;
board_detected_o : out std_logic
);
end wrsw_ext_board_check;
end wrsw_ljd_detect;
architecture Behavioral of wrsw_ext_board_check is
architecture Behavioral of wrsw_ljd_detect is
signal clk_divider : integer range 0 to g_clk_divider-1;
signal clk_en : std_logic;
......
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ f8127017
......@@ -68,10 +68,6 @@ entity wrsw_rt_subsystem is
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
-- WRS Low jitter daughterboard
ext_board_detected_i : in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
......@@ -130,7 +126,17 @@ entity wrsw_rt_subsystem is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low jitter daughterboard AD9516
------------------------------------------------------
-- WRS Low jitter daughterboard
------------------------------------------------------
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
-- AD9516
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
......@@ -264,6 +270,7 @@ architecture rtl of wrsw_rt_subsystem is
end if;
end f_pick;
signal ljd_board_detected : std_logic;
begin -- rtl
......@@ -490,7 +497,7 @@ begin -- rtl
rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4);
gpio_in(5) <= ext_board_detected_i;
gpio_in(5) <= ljd_board_detected;
gpio_in(8 downto 6) <= ext_board_osc_freq_i;
......@@ -528,5 +535,26 @@ begin -- rtl
dac_sclk_o => dac_helper_sclk_o,
dac_sdata_o => dac_helper_data_o);
------------------------------------------------------
-- WRS Low jitter daughterboard
------------------------------------------------------
ext_board_clk1_en <= '1';
ext_board_clk2_en <= '1';
ext_pll_sync_n_o <= '1';
-- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst : entity work.wrsw_ljd_detect
generic map (
g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D")
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
loopback_i => ext_board_loopback_i,
loopback_o => ext_board_loopback_o,
board_detected_o => ljd_board_detected);
ext_board_detected_o <= ljd_board_detected;
end rtl;
top/bare_top/scb_top_bare.vhd
View file @ f8127017
......@@ -114,13 +114,20 @@ entity scb_top_bare is
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-- WRS Low jitter daughterboard (db) external clock
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
......@@ -453,6 +460,11 @@ architecture rtl of scb_top_bare is
signal nic_rtu_rsp : t_rtu_response;
signal nic_rtu_ack : std_logic;
signal ljd_detected : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
begin
......@@ -596,7 +608,6 @@ begin
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
ext_board_detected_i => ext_board_detected_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -612,9 +623,9 @@ begin
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
......@@ -642,13 +653,19 @@ begin
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_board_loopback_i => ext_board_loopback_i,
ext_board_loopback_o => ext_board_loopback_o,
ext_board_clk1_en => ext_board_clk1_en,
ext_board_clk2_en => ext_board_clk2_en,
ext_board_detected_o => ljd_detected,
ext_board_osc_freq_i => ext_board_osc_freq_i,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
ext_board_osc_freq_i => ext_board_osc_freq_i,
spll_dbg_o => spll_dbg_o);
......@@ -1291,5 +1308,31 @@ begin
T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
end generate;
-------------------------------------------------------------------------------
-- WRS Low jitter daughterboard
-------------------------------------------------------------------------------
ext_board_detected_o <= ljd_detected;
-- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ljd_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ljd_dac_main_sync_n_o <= '0';
ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ljd_dac_main_sync_n_o <= dac_main_sync_n;
ljd_dac_main_sclk_o <= dac_main_sclk;
ljd_dac_main_data_o <= dac_main_data;
end if;
end process;
end rtl;
top/bare_top/wrsw_components_pkg.vhd
View file @ f8127017
......@@ -246,7 +246,6 @@ package wrsw_components_pkg is
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
ext_board_detected_i: in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -254,6 +253,12 @@ package wrsw_components_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ f8127017
......@@ -255,6 +255,11 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
......@@ -262,7 +267,6 @@ package wrsw_top_pkg is
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_board_detected_i: in std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -303,7 +307,6 @@ package wrsw_top_pkg is
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
ext_board_detected_i: in std_logic := '0';
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -316,6 +319,15 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ f8127017
......@@ -244,18 +244,6 @@ architecture Behavioral of scb_top_synthesis is
locked_o : out std_logic);
end component;
component wrsw_ext_board_check is
generic (
g_pattern : std_logic_vector (63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
loopback_i : in std_logic;
loopback_o : out std_logic;
board_detected_o : out std_logic);
end component;
constant c_NUM_PHYS : integer := 18;
constant c_NUM_PORTS : integer := 18;
......@@ -345,10 +333,6 @@ architecture Behavioral of scb_top_synthesis is
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
component scb_top_bare
generic (
......@@ -386,6 +370,15 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -399,8 +392,6 @@ architecture Behavioral of scb_top_synthesis is
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......@@ -447,9 +438,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
ext_board_clk1_en <= '1';
ext_board_clk2_en <= '1';
ext_pll_sync_n_o <= '1';
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
......@@ -629,26 +617,6 @@ begin
CLKFBIN => pllout_clk_fb,
CLKIN => clk_25mhz);
-- Redirect DAC output if external board detetected
dac_redirection : process (dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ext_board_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ext_dac_main_sync_n_o <= '0';
ext_dac_main_sclk_o <= '0';
ext_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ext_dac_main_sync_n_o <= dac_main_sync_n;
ext_dac_main_sclk_o <= dac_main_sclk;
ext_dac_main_data_o <= dac_main_data;
end if;
end process;
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
......@@ -675,18 +643,6 @@ begin
clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ext_clk_62mhz_bufr;
-- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst : wrsw_ext_board_check
generic map (
g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D")
port map (
clk_sys_i => clk_sys,
rst_n_i => sys_rst_n_i,
loopback_i => ext_board_loopback_i,
loopback_o => ext_board_loopback_o,
board_detected_o => ext_board_detected);
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
......@@ -865,9 +821,20 @@ begin
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
-- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ext_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ext_dac_main_sclk_o,
ljd_dac_main_data_o => ext_dac_main_data_o,
ext_board_loopback_i => ext_board_loopback_i,
ext_board_loopback_o => ext_board_loopback_o,
ext_board_clk1_en => ext_board_clk1_en,
ext_board_clk2_en => ext_board_clk2_en,
ext_board_detected_o => ext_board_detected,
ext_board_osc_freq_i => ext_board_osc_freq_i,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
......@@ -881,8 +848,6 @@ begin
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
ext_board_osc_freq_i=> ext_board_osc_freq_i,
ext_board_detected_i=> ext_board_detected,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ f8127017
......@@ -246,19 +246,6 @@ architecture Behavioral of scb_top_synthesis is
locked_o : out std_logic);
end component;
component wrsw_ext_board_check is
generic (
g_pattern : std_logic_vector (63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
loopback_i : in std_logic;
loopback_o : out std_logic;
board_detected_o : out std_logic);
end component;
constant c_NUM_PHYS : integer := 8;
constant c_NUM_PORTS : integer := 8;
......@@ -345,9 +332,6 @@ architecture Behavioral of scb_top_synthesis is
signal ext_board_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
component scb_top_bare
generic (
......@@ -385,6 +369,15 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -398,8 +391,6 @@ architecture Behavioral of scb_top_synthesis is
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......@@ -446,10 +437,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
ext_board_clk1_en <= '1';
ext_board_clk2_en <= '1';
ext_pll_sync_n_o <= '1';
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
......@@ -630,40 +617,6 @@ begin
CLKFBIN => pllout_clk_fb,
CLKIN => clk_25mhz);
-- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst : wrsw_ext_board_check
generic map (
g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D")
port map (
clk_sys_i => clk_sys,
rst_n_i => sys_rst_n_i,
loopback_i => ext_board_loopback_i,
loopback_o => ext_board_loopback_o,
board_detected_o => ext_board_detected
);
-- Redirect DAC output if external board detetected
dac_redirection : process (dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ext_board_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ext_dac_main_sync_n_o <= '0';
ext_dac_main_sclk_o <= '0';
ext_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ext_dac_main_sync_n_o <= dac_main_sync_n;
ext_dac_main_sclk_o <= dac_main_sclk;
ext_dac_main_data_o <= dac_main_data;
end if;
end process;
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
......@@ -871,9 +824,20 @@ begin
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
-- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ext_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ext_dac_main_sclk_o,
ljd_dac_main_data_o => ext_dac_main_data_o,
ext_board_loopback_i => ext_board_loopback_i,
ext_board_loopback_o => ext_board_loopback_o,
ext_board_clk1_en => ext_board_clk1_en,
ext_board_clk2_en => ext_board_clk2_en,
ext_board_detected_o => ext_board_detected,
ext_board_osc_freq_i => ext_board_osc_freq_i,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
......@@ -887,8 +851,6 @@ begin
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
ext_board_osc_freq_i=> ext_board_osc_freq_i,
ext_board_detected_i=> ext_board_detected,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment