Commits · 78d3f242d8b1fb88d4d66872ae0496be57c3240e · Projects / White Rabbit Switch - Gateware · Open Hardware Repository

09 Aug, 2019 9 commits
- wrsw_ext_board: fix formatting, no technical change · 78d3f242
  Grzegorz Daniluk authored Aug 09, 2019
  
  78d3f242
- rt_subsystem: add generic for low jitter daughterboard support · a8d8867f
  Grzegorz Daniluk authored Aug 08, 2019
  
  a8d8867f
- Modified synthesis configuration for 18ports build · b5489272
  Mattia Rizzi authored Dec 20, 2016
  
  b5489272
- Modified constraints for low-jitter daughterboard · 7d9971a2
  Mattia Rizzi authored Aug 09, 2019
  
  7d9971a2
- Updated wr-cores for external board · 31d7252e
  Mattia Rizzi authored Dec 20, 2016
  
  31d7252e
- Modifed Manifests to build correctly the project file · fb524f59
  Mattia Rizzi authored Dec 20, 2016
  
  fb524f59
- Added support for the external board · 0b1aba5a
  Mattia Rizzi authored Dec 20, 2016
  
  0b1aba5a
- Added a powerdown line to shutdown the noisy MMCMs when external PLL is detected · 85dd1047
  Mattia Rizzi authored Dec 20, 2016
  
  85dd1047
- Added module to check the presence of the external board · 98089675
  Mattia Rizzi authored Dec 20, 2016
  
  98089675
05 Jun, 2019 1 commit
- add bit to control WRS 1-PPS in termination · 31787035
  Grzegorz Daniluk authored Sep 13, 2018
  
  31787035
13 May, 2019 1 commit
- Merge branch 'greg-mirroring' into proposed_master · 246f32a1
  Grzegorz Daniluk authored May 13, 2019
  
  246f32a1
10 May, 2019 2 commits
- add port mirroring for NIC/CPU originated traffic · 6935e96c
  Grzegorz Daniluk authored May 10, 2019
  
  6935e96c
- pass NIC originated RTU decisions through RTU module · b01a8ee9
  Grzegorz Daniluk authored May 10, 2019
  
  b01a8ee9
09 May, 2019 3 commits
- fix simulation for modern Modelsim versions · ac150620
  Grzegorz Daniluk authored May 09, 2019
  
  ac150620
- fix simulation after reset changes in wr-cores · 3073df19
  Grzegorz Daniluk authored May 09, 2019
  
  3073df19
- update wr-cores to fix simulation after nic and txtsu move · aa7aca2a
  Grzegorz Daniluk authored May 09, 2019
  
  aa7aca2a
08 May, 2019 1 commit
- update general-cores · 3c5be125
  Grzegorz Daniluk authored May 08, 2019
  
  3c5be125
11 Mar, 2019 1 commit
- move wrsw_txtsu to wr-cores repository · 9cbde414
  Grzegorz Daniluk authored Mar 11, 2019
  
  9cbde414
08 Mar, 2019 1 commit
- move wrsw_nic to wr-cores repository · 2973034b
  Grzegorz Daniluk authored Mar 06, 2019
  
  2973034b
06 Mar, 2019 1 commit
- wrsw_pstats: fix Manifest for more picky hdlmake · 30b0dea2
  Grzegorz Daniluk authored Mar 06, 2019
  
  30b0dea2
05 Mar, 2019 2 commits
- Merge branch 'wrs-pts-v1.0' into proposed_master · be2ea7f5
  Grzegorz Daniluk authored Mar 05, 2019
  
  be2ea7f5
- update submodules after ohwr migration · d2c67ba6
  Grzegorz Daniluk authored Mar 05, 2019
  
  d2c67ba6
20 Nov, 2018 1 commit
- update submodules to include preamble shrinkage support · 036cbead
  Grzegorz Daniluk authored Nov 18, 2018
  
  036cbead
08 Jun, 2018 1 commit
- Prepared for PTS build · fbf07e05
  Bert Gooijer authored May 29, 2017
  
  fbf07e05
25 Nov, 2016 1 commit
- update general-cores and wr-cores since sdb crossbar is now fixed for metadata · 1d500455
  Grzegorz Daniluk authored Nov 25, 2016
  
  1d500455
23 Nov, 2016 1 commit
- update simulation manifests to use new hdlmake · aef7d8ab
  Grzegorz Daniluk authored Nov 23, 2016
  
  aef7d8ab
22 Nov, 2016 3 commits
- update reported GW version to v5.0 · 388f812d
  Grzegorz Daniluk authored Nov 22, 2016
  
  388f812d
- update wr-cores for new release · 99170f6d
  Grzegorz Daniluk authored Nov 22, 2016
  
  99170f6d
- update general-cores to HEAD of master · 03b27a71
  Grzegorz Daniluk authored Nov 22, 2016
  
  03b27a71
21 Nov, 2016 2 commits
- update synthesis Manifests to use new hdlmake · 15b94c3a
  Grzegorz Daniluk authored Nov 21, 2016
  
  15b94c3a
- Merge branch 'greg-swcore' into proposed_master · 0f1a7547
  Grzegorz Daniluk authored Nov 21, 2016
  
  0f1a7547
18 Nov, 2016 9 commits
- swcore: fix output block frame dropping on HP (still not perfect) · 1a662f42
  Grzegorz Daniluk authored Nov 18, 2016
  
  1a662f42
- swcore: multiport LL, fix write ports split · 7a1b9191
  Grzegorz Daniluk authored Nov 18, 2016
  
  7a1b9191
- swcore: add wishbone register to enable dropping traffic in OB if HP frames are queued · a72c35b0
  Grzegorz Daniluk authored Sep 13, 2016
  
  a72c35b0
- swcore: use record-based interfaces for multiport linked list · e94dffe1
  Grzegorz Daniluk authored Sep 13, 2016
  
  e94dffe1
- swcore: multiport LL, use 3 write ports · babcf5c0
  Grzegorz Daniluk authored Sep 12, 2016
  
  babcf5c0
- swcore: multiport LL configurable number of write ports to MPRAM · ce4988d9
  Grzegorz Daniluk authored Sep 12, 2016
  
  ce4988d9
- swcore: multiport LL rewritten to use multiport RAM with 2 write ports · 8452ca3a
  Grzegorz Daniluk authored Sep 03, 2016
  
  8452ca3a
- swcore: swc_ll_read_data_validate supports generic number of write interfaces · 68dda3e8
  Grzegorz Daniluk authored Aug 31, 2016
  
  68dda3e8
- swcore: adding Switched-Multiported-RAM from github · cc4a9925
  Grzegorz Daniluk authored Aug 31, 2016
```
https://github.com/AmeerAbdelhadi/Switched-Multiported-RAM
Commit 2a460ed
```
  cc4a9925