White Rabbit Switch - Gateware:master commitshttps://ohwr.org/project/wr-switch-hdl/commits/master2023-12-12T10:20:32Zhttps://ohwr.org/project/wr-switch-hdl/commit/9990e46ed98938c85cdda10c94325e027ed58152Commit latest ISE project (not a good idea but a "tradition")2023-12-12T10:20:32ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/830402163f3e69f018b15f00763060f80d24f89cLJ: cosmetics: add constants for different values of lj_osc_freq and lj_perip...2023-12-12T10:16:30ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/163c4ffaa45478c17a2fb9f30e155a1063ea6a2eWRS-FL: Updated periph_id reservation for WRS-FL2023-12-09T22:38:01ZMaciej Lipinskimaciej.lipinski@cern.ch
It turned out that WRS-FL uses periph_id 0x7 for v1.0 and
0x6 for v1.5. Updated accordingly.https://ohwr.org/project/wr-switch-hdl/commit/643c39d1b55dd22ae6838807dd1c0e54065ea11eGW_VER: bump GW version and update date2023-12-05T10:00:35ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/0b048b1f9d8193277b30b7f7f6996a674ac308b0CI: gw_ver_pkg.vhd needs to exist before Makefile is run. Generate from YML2023-12-04T16:29:58ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/1ba2258d93f9732942499e8cca1f417282db373dDDMTD: disable reverse option, it needs to be coupled with relevant changes t...2023-12-04T14:58:42ZMaciej Lipinskimaciej.lipinski@cern.ch
Apparently, this is helpful for WRS-FL v1.5. Explanation from Hongming:
From: hongming
Sent: 30 November 2023 01:24
To: Maciej Marek Lipinski
Subject: 回复: Re:WRS-FL integration into next WRS firmware release
hi maciej
> we do not fully see/understand how changing g_reverse_dmtd to false
> could help in the problem you described. We need to discuss this change
> (which is quite serious) before proceeding
As you may see, we've changed the VCXO of helper PLL in new HW.
There are two search direction for PLL, corresponding to two frequency
relation between help clock and main/ext clock.
As far as I remember, if the frequency of help clock is higher than
main/ext clock, it should use help clock sampling main/ext clock, while
if if the frequency of help clock is lower than main/ext clock, it should
do the opposite.
In our actual test, the actual frequency of VCXO may be slower than the
claimed frequency. The help VCXO cannot reach the supposed value if we
require the frequency of help clock to be higher than main/ext clock.
What we observed it that in previous settings, the dac output of help
clock reaches to be 64000+ when the dac output of main clock is 30000.
After changing the g_reverse_dmtd and searching direction of help PLL,
the dac output of help clock reaches to be 16500+ when the dac output
of main clock is 30000.
When we look at the hardware implementation to find out the reason, we
have the following information:
- We choose VCXO with a pull range of +-100ppm, without considerating
the frequency statbility, making the actual APR to be only +-45ppm.
- What's worse is that the Supply Voltage of VCXO is 3.3V and our DAC's
maximun output is 2.5V.
In current WR implementation, N=16384, which means that we need a VCXO
with APR of 61ppm.https://ohwr.org/project/wr-switch-hdl/commit/bd0d0d31feb0ac2bfdc8b37dba26b12a6ea62da8CI: update Manifest.py and YML file2023-12-04T14:10:02ZMaciej Lipinskimaciej.lipinski@cern.ch
Manifest:
- Before syn: add execution of script to generate files with repo versions
- After syn: add generation of bin file
YML:
- synthesize 8 ports always
- synthesize 18 ports when called manually
- simulate when called manuallyhttps://ohwr.org/project/wr-switch-hdl/commit/a9b9ce21068a9db18604d44d0672a0b35d819e46LJ: improve/generalize Low-Jitter functionality detection/handling2023-12-04T14:01:42ZMaciej Lipinskimaciej.lipinski@cern.ch
- change signal names to more meaningful
lj_detected_o / lj_present_o to lj_ext_gm_pll_pres_o / lj_ext_gm_clk_diff_o
lj_rev_id_i to lj_periph_id_i
- added pull-ups to lj_periph_id_i to make sure its "111" when unused
- made the selection of LJ-related peripheral more generichttps://ohwr.org/project/wr-switch-hdl/commit/33a5c699d52efdd57f5c3bf7fb3ee7106e96f303LJ: Rename LJD to LJ, Low-Jitter functionality not specific only to the LJ Da...2023-12-04T14:00:49ZMaciej Lipinskimaciej.lipinski@cern.ch
The Low-Jitter functionality is now integrated on some versions of the
main board of the WRS. As such, we need to detect the LJ functionality
itself, not a board with it. Renamed from LJD to LJ for clarity.https://ohwr.org/project/wr-switch-hdl/commit/870484edbd43af182c85e390ce6e8d75289f8b36update the mechanism of detecting different WRS-FL versions and dac_sel2023-11-29T14:57:01ZMaciej Lipinskimaciej.lipinski@cern.ch
- updated the pin names to reflect the true functionality
- connect only the pin that is used, this is a HACK and will need to be
changed in the future.https://ohwr.org/project/wr-switch-hdl/commit/94e1abb0dbe997a329098bec576d4c20acff1329add dac_sel for new hardware and add some modifications from wrslj2023-11-29T13:00:46Zhmlihm.thu@foxmail.com
- dac_sel allows to support AD5683R additonally to AD5662 used so far
- other modificatins, mostly clean-ups
* change pll_status_i to clk_ext_i
* removed unused constraintshttps://ohwr.org/project/wr-switch-hdl/commit/5062b0082224d56a17c01074fffa88095444be8eAdd CI2023-11-15T00:38:44ZAdam Wujekdev_public@wujek.euhttps://ohwr.org/project/wr-switch-hdl/commit/17e8508c47a487730a145b92d299e3d551044d73Update wrsw_top_pkg.vhd2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/1d5f964d519cf513163511e3e86bfc1652cdd500Fixed a typo. $faltal() => $fatal()2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/4223d8072bf1075c8c4845a095f7f8313649ae66Update wrsw_top_pkg.vhd2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/2bc7c98279cdfd12a1da1a34eee81e129778cb81Update wrsw_top_pkg.vhd. changed the clk_ext_mul_i and clk_ext_mul_locked_i w...2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/082d3e6d4a2907c5a28026a71cca11b71a8b6e78Update run.do2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/93b93831a6b964b7c10e2558281a8d00c184e6abtop/bare_top/scb_top_sim: changed the given values of clk_ext_mul_i & clk_ext...2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/de8e6739aa994f230d9a3d1d4017aa5b416befb3Update scb_top_sim.vhd. given to the unused input ljd signals, '0' value for ...2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chUpdate scb_top_sim.vhd. given to the unused input ljd signals, '0' value for the simulator to not complainhttps://ohwr.org/project/wr-switch-hdl/commit/212fb8577633523e6828233365d2736e1ad915d1Update scb_top_sim.vhd so as to add missing and non-used port signals in order…2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chUpdate scb_top_sim.vhd so as to add missing and non-used port signals in order simulator doesn't complainhttps://ohwr.org/project/wr-switch-hdl/commit/f162799f17a1a6efb4af41ddb806c4d457dcfff9Update gen_sdbsyn.py2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/98dadab25acd67704d87a5b9b3ac4631210db126Update testbench/scb_top/Manifest.py2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/2a61062e391c6a35f611a55c8594b9a6ca9c483fUpdate syn/scb_8ports/Manifest.py2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/ca684658a7f57e4a944a0792c2966b8d3fb22bcfUpdate top/bare_top/Manifest.py2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/fba8f821391aea0a5b7de5d55610fad26b547fafUpdate testbench/scb_top_8p/Manifest.py2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/3df27866537486f4dd69c051d43d69d0541f1157Add .gitlab-ci.yml2023-11-15T00:35:35ZKonstantinos Blantoskblantos@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/0fea77b824ce316a04ff2c4abc8cc6f6c4db433eMerge branch 'hm_proposed_master' into 'proposed_master'2023-11-14T10:04:55ZMaciej Lipinskimaciej.lipinski@cern.ch
Hm proposed master
See merge request <a href="/project/wr-switch-hdl/merge_requests/1" data-original="project/wr-switch-hdl!1" data-link="false" data-link-reference="false" data-project="10729" data-merge-request="50" data-reference-type="merge_request" data-container="body" data-placement="bottom" title="Hm proposed master" class="gfm gfm-merge_request has-tooltip">!1</a>https://ohwr.org/project/wr-switch-hdl/commit/9a26b13e0651cac9b09014af17e0cef32bddd976lpdc: fix for jumbo frames2023-05-17T12:38:43ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/c2eb473431ccb41b2b728cccfdfcc5afadf548b010mhz_out: pushing forgotten simulations2021-12-20T07:40:04ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/4d68cb12b92d113ea1e50881bad4ee2388ab41b2 solve constraints error in top/scb_18ports/scb_top_synthesis.ucf2020-07-01T06:46:47Zhongminglihm.thu@foxmail.com
1. add pll_status_i clock period constraints
2. correct the TNM_NET name of rx_rec_clk_bufin.https://ohwr.org/project/wr-switch-hdl/commit/af932bbd16bb9684ee907a02ba91cb5905c8b403 change the clk_10m input source as currently WRSLJ uses single end signal2020-05-15T01:40:44Zhongminglihm.thu@foxmail.comrather than differential signal for 10M input.https://ohwr.org/project/wr-switch-hdl/commit/87f0227764ec49a325b627dae915f9cefc5398db add support for WRS-LJ.2020-05-14T07:57:22Zhongminglihm.thu@foxmail.com
There are three types of wrs: normal wrs(mark as wrs), wrs with LJD
(mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ).
lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ.
lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD.
lj_osc_freq_i=111 means WRSLJ.
lj_osc_freq_i=others means WRS-LJD.
lj_osc_freq_i[2 downto 0] need to be pulled up.https://ohwr.org/project/wr-switch-hdl/commit/d315bf7b3ef09aa2cfa3fae223f7943ab23bc199update gateware version to v6.02020-04-06T07:45:32ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/8b7d73e606f27b6426200e52b3c14cb69c050364lpdc: allow WRS shutting down the interface without breaking Tx LPDC2020-04-03T16:04:21ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/149742faf43e7cdb573e25555fe49ac71b7125cfupdate wr-cores to fix another LPDC bug2020-01-20T07:26:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/0f9aee8fb9fe3aaedacf4129e892a71053bfa1dfpstats: more registers to improve timing2020-01-07T08:49:37ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/350789e88220fb04893a1896d6c0a2aec38233bcadd project file for release2019-12-17T14:21:09ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/982b8362164d2f96140a0de481364680ae9bc162pstats: add registers to improve timing2019-12-17T14:21:09ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/3cc77ba736159ffb0c9dcc8d6c592aab5699c6bblpd: update wr-cores for chicken-bits and rx synchronizer2019-12-09T08:13:59ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-switch-hdl/commit/5d5f1a746a8bee04a81a8cb87e53ec10698377a5Merge branch 'greg-lpd-rebased' into proposed_master2019-08-30T13:49:39ZGrzegorz Danilukgrzegorz.daniluk@cern.ch