Data errors when RXCLK offset > 30 ppm
Problem: "Invalid code" RX errors under low and moderate traffic load.
WR Node <
fiber> WRS3-18 < UTP> LAN switch
Test software is communicating with WR Node through LAN and WR Switch.
Traffic rate is about 2000 packets per second bidirectionally.
Different LAN switches have been tested. Some worked without errors, some exposed 'invalid code' rx error and packets was dropped.
There's strong correlation between error rate and TX_CLK frequency offset on LAN switch port.
No errors with those switches that have TX_CLK frequency offset below 30 ppm, i.e. in range 124,996,250 - 125,003,750 Hz
Many errors with switches with TX_CLK offset greater than 75 ppm but still below 100 ppm defined by standard.
TX_CLK frequency offset of LAN switch port is measured with custom board with LSI ET1011C Gigabit Ethernet PHY chipset. It has RX_CLK pin (recovered clock) that is monitored by spectrum analyser with 1 ppm accuracy.
The results of clock offset in a series of commercial HP switches are very unexpected. Modern HP 3800 and 2910al have offset 80 ppm- 6 ppm. This is near the limit allowed by standard. I can't believe that it was a series of bad crystals with this large offset. It's systematic.
The measurement report in attachment.
The rx code error rate does not depend on transceiver type used. Same results with WDM (BX), GLC-LH-SM and copper GLC-T transceivers. There's no dependence on specific WR Switch or port. Multiple WR switches tested with same result. WRS ports 2-18 behave similarly. Port 1 (slave) was not used for tests.
For WR Switch to comply with IEEE 802.3 standard it should handle +- 100 ppm clock offsets.