The FMC provides only one clock frequency for the transceivers, we need two
if the goal is to test a hybrid solution with 1G&10G. Check if additional connections
to the transceivers QPLLs can be done via FMC or external cabling. If not, we
may need to rethink things.
For 1G-10G interoperability testing, it might be worth to put more SFPs on the FMC
(even if this means not following the size specification of FMC), can you check whether
this is possible and what is the max of SFPs that we could have on that FMC?
We found AFCZ board as a good platform to test WR, could you verify that the
FMC could be compatible with ZCU102/ZCU106 and AFCZ (at a schematics level)
https://github.com/elhep/AFCZ/
Si549 or Si 571: make the pcb in a way that both can be mounted. We already have
some experience with Si 571 so it can be a good alternative.
AD5541AARMZ : If not yet tested I would go for a buffered DAC