Mixing 1Gbit and 10Gbit on front panel SFPs
The current clocking scheme (revision 4) only supports one choice of internally generated clock for all front panel SFP links. As I understand it, we need 125MHz as a reference clock for 1Gbit Ethernet and will need 156.25MHz for 10Gbit Ethernet. If this is right, we will not be able to use 1Gbit and 10Gbit Ethernet together on the built-in connectors, unless a special second clock is made available through the extension connector J15.
Looking at the current clocking scheme, it seems that it should be easy enough to remedy this. At present all the GTH Quads (banks 224 to 231, sheet 17 of the schematic) are clocked (via IC22) from output CLKOUT8 of IC2 (sheet 5).
I observe that we have unused clock outputs SCLKOUT7 and SCLKOUT9, as well as four separate clocks (gathered as GTY_CLK0), and I am told that the GTH Quads can source clocks from adjacent Quads. The simplest solution might therefore be to add a copy of IC22, drive this from, let's say, IC2:CLKOUT7, and use the outputs from this device to drive Quads 225, 227, 229 (and maybe 231).