Commit 27917ddc authored by jgabriel's avatar jgabriel

The schematics changes performed on the V3.2 are the following:

1.- SCB_PLLs: C165 footprint changed to 0402 in order to remove this component and reduce boom.
2.- Connectors:CN1 Ethernet connector case connected to GND_SHIELD.
3.- CPU_100M_Ethernet:C206 changed from 470pF to 2,7nF in order to remove this component and reduce boom.Added R253 and R254 resistors (both 75R) between the Tr1 and C214.
L10 is not mounted now. It connects GND_SHIELD and GND_ETH.
4.- QDRII_mem and QDRII_power: All the components of the QDRII memories will be not mounted. 
parent 485030e4
ETH_100MHz=SHIELD,TX_P,TX_N,RX_P,RX_N,LED_LINK,LED_ACT
ETH_100MHz=TX_P,TX_N,RX_P,RX_N,LED_LINK,LED_ACT
CPU_JTAG=JNTRST,JTDI,JTMS,JTCK,JRTCK,JTDO,JNRST
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
CPU_USB=USB_HDP_N,USB_HDP_P,USB_DDP_N,USB_DDP_P
ETH_100MHz=LED_ACT,LED_LINK,RX_N,RX_P,TX_N,TX_P,SHIELD
ETH_100MHz=LED_ACT,LED_LINK,RX_N,RX_P,TX_N,TX_P
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDO,FPGA_TDI
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
......
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