Commit a0f56caf authored by Benoit Rat's avatar Benoit Rat

wrs3: update altium files for SCB v3.3 to v3.4

Schematics:
------------

* C165 value changed from 100nF to 220nF
* VCC_IN of CDCM61002 (IC13) connected to +3V3
* RSTN pin of IC13 conected to a 47nF capacitor, not to +3V3
* QDRII_200CLK moved to OUT3 (LVPECL) of AD9516.
* Added LVDS termination resistor to adapt OUT3 to LVDS format
* CLK_OUT (EXTREF125MHZOUT) connected to OUT9 (CMOS) of AD9516-4.
* CLK_OUT transformer changed by 1:1 (WBC1-1LB)
* R253 and R254 resistor (Ethernet sheet) changed to 0402 size in order
to reduce items.
* Changed EXTPPSIN input stage in order to add 50 R termination
selectable by the FPGA.
* Name of nets QDRII_CLK and QDRII_200CLK changed to REF_CLK and
AUX_CLK.
* Input EXTREF_125M removed.
* QDRII IC42 chip removed.
* Added ouput from FPGA latched by an AD9516 clock. This output uses
the EXTREF_125M SMC connector:
	* Added LVPECL latch
	* Added LVPECL to LVTTL translator at the output
	* CLK0 input of IC12 changed to OUT6 of AD9516
	* FPGA VCCO Bank 26 changed to +2V5 to use LVPECL and LVDS
* Removed the six 0R resistor at the inputs of the AD5662 DACs
* FPGA Banks 26, 36 and 25 moved to "PFGA_Peripherals_Control" sheet.
* Connected the 3 free buffers SN74LVT125DW to the EXTPPSOUT output
signal.

PCB:
------

* GTX_DIFF signals routed on 90um/160um in order to reduce space,
allowing to pass between vias
* Some vias were moved from pads of some components to avoid the solder
paste flooding by the vía.
* IVT3200 VCO was moved to separate it of NAND Flash IC
parent 80f860c2
SCB Changes from V3.3 to V3.4:
===============================
Schematics:
------------
* C165 value changed from 100nF to 220nF
* VCC_IN of CDCM61002 (IC13) connected to +3V3
* RSTN pin of IC13 conected to a 47nF capacitor, not to +3V3
* QDRII_200CLK moved to OUT3 (LVPECL) of AD9516.
* Added LVDS termination resistor to adapt OUT3 to LVDS format
* CLK_OUT (EXTREF125MHZOUT) connected to OUT9 (CMOS) of AD9516-4.
* CLK_OUT transformer changed by 1:1 (WBC1-1LB)
* R253 and R254 resistor (Ethernet sheet) changed to 0402 size in order to reduce items.
* Changed EXTPPSIN input stage in order to add 50 R termination selectable by the FPGA.
* Name of nets QDRII_CLK and QDRII_200CLK changed to REF_CLK and AUX_CLK.
* Input EXTREF_125M removed.
* QDRII IC42 chip removed.
* Added ouput from FPGA latched by an AD9516 clock. This output uses the EXTREF_125M SMC connector:
* Added LVPECL latch
* Added LVPECL to LVTTL translator at the output
* CLK0 input of IC12 changed to OUT6 of AD9516
* FPGA VCCO Bank 26 changed to +2V5 to use LVPECL and LVDS
* Removed the six 0R resistor at the inputs of the AD5662 DACs
* FPGA Banks 26, 36 and 25 moved to "PFGA_Peripherals_Control" sheet.
* Connected the 3 free buffers SN74LVT125DW to the EXTPPSOUT output signal.
PCB:
------
* GTX_DIFF signals routed on 90um/160um in order to reduce space, allowing to pass between vias
* Some vias were moved from pads of some components to avoid the solder paste flooding by the vía.
* IVT3200 VCO was moved to separate it of NAND Flash IC
Changes from SCBv3.2 to SCBv3.3
......
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N
qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
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MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL,CLK_EN
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
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