1. 28 Jan, 2019 1 commit
    • Nico Coesel's avatar
      Minibackplane v3.3.1 by OPNT · bbccf546
      Nico Coesel authored
      Only Bill of Materials was updated in version v3.3.1. No changed in PCB
      schematics were made.
      Instead of a P-channel MOSFETs we placed N-channel MOSFETs. The internal diode
      will always conduct so the fans are always on. The control remaining drive
      circuitry isn't placed.
      bbccf546
  2. 25 Jan, 2019 1 commit
  3. 07 Nov, 2016 3 commits
  4. 25 Sep, 2014 11 commits
    • Benoit Rat's avatar
      mechanics: update box files for SCB v3.4 · 936516f6
      Benoit Rat authored
      936516f6
    • Benoit Rat's avatar
      scb: add pdf file of schematics for v3.4 · 7c3334c8
      Benoit Rat authored
      7c3334c8
    • Benoit Rat's avatar
      scb: add partlist file 3.4.1 for SCB v3.4 · 9c481e67
      Benoit Rat authored
      9c481e67
    • Benoit Rat's avatar
      wrs3: update altium files for SCB v3.3 to v3.4 · a0f56caf
      Benoit Rat authored
      Schematics:
      ------------
      
      * C165 value changed from 100nF to 220nF
      * VCC_IN of CDCM61002 (IC13) connected to +3V3
      * RSTN pin of IC13 conected to a 47nF capacitor, not to +3V3
      * QDRII_200CLK moved to OUT3 (LVPECL) of AD9516.
      * Added LVDS termination resistor to adapt OUT3 to LVDS format
      * CLK_OUT (EXTREF125MHZOUT) connected to OUT9 (CMOS) of AD9516-4.
      * CLK_OUT transformer changed by 1:1 (WBC1-1LB)
      * R253 and R254 resistor (Ethernet sheet) changed to 0402 size in order
      to reduce items.
      * Changed EXTPPSIN input stage in order to add 50 R termination
      selectable by the FPGA.
      * Name of nets QDRII_CLK and QDRII_200CLK changed to REF_CLK and
      AUX_CLK.
      * Input EXTREF_125M removed.
      * QDRII IC42 chip removed.
      * Added ouput from FPGA latched by an AD9516 clock. This output uses
      the EXTREF_125M SMC connector:
      	* Added LVPECL latch
      	* Added LVPECL to LVTTL translator at the output
      	* CLK0 input of IC12 changed to OUT6 of AD9516
      	* FPGA VCCO Bank 26 changed to +2V5 to use LVPECL and LVDS
      * Removed the six 0R resistor at the inputs of the AD5662 DACs
      * FPGA Banks 26, 36 and 25 moved to "PFGA_Peripherals_Control" sheet.
      * Connected the 3 free buffers SN74LVT125DW to the EXTPPSOUT output
      signal.
      
      PCB:
      ------
      
      * GTX_DIFF signals routed on 90um/160um in order to reduce space,
      allowing to pass between vias
      * Some vias were moved from pads of some components to avoid the solder
      paste flooding by the vía.
      * IVT3200 VCO was moved to separate it of NAND Flash IC
      a0f56caf
    • Benoit Rat's avatar
      wrs3: improve license and README · 80f860c2
      Benoit Rat authored
      80f860c2
    • Benoit Rat's avatar
      misc: clean up schematics files · 74b1237c
      Benoit Rat authored
      74b1237c
    • Benoit Rat's avatar
      misc: clean up mini-backplane folders · 04348c93
      Benoit Rat authored
      Remove miniBackplane_SFP which was a copy of v3.2
      Rename miniBackplane_18Ports_SFP_V3.3/ to mini_backplane_18SFP/
      Rename miniBackplane_test/ to mini_backplane_test/
      04348c93
    • Benoit Rat's avatar
      SCB: clean part list files · 1939cf26
      Benoit Rat authored
      1939cf26
    • Benoit Rat's avatar
      SCB: clean changes list to CHANGES.txt · b65df4d0
      Benoit Rat authored
      b65df4d0
    • Benoit Rat's avatar
      misc: clean-up old and unused files · feb440ba
      Benoit Rat authored
      feb440ba
    • Benoit Rat's avatar
      ce4bb7e7
  5. 22 Jul, 2013 3 commits
  6. 21 Jan, 2013 2 commits
  7. 27 Nov, 2012 1 commit
  8. 13 Nov, 2012 1 commit
  9. 12 Nov, 2012 2 commits
  10. 09 Nov, 2012 1 commit
  11. 08 Nov, 2012 1 commit
  12. 06 Nov, 2012 3 commits
  13. 05 Nov, 2012 1 commit
  14. 31 Oct, 2012 3 commits
  15. 26 Oct, 2012 1 commit
  16. 25 Oct, 2012 1 commit
  17. 22 Oct, 2012 1 commit
  18. 19 Oct, 2012 1 commit
  19. 17 Oct, 2012 2 commits