Release v3.1 (SCB)
SCB_PLLs:
- R61 changed to o.c. The V3 works with 62,5MHz DMTD clock instead of the foreseen 125MHz).
- C188 not mounted by defect.
- AD9516 resistor changed to 100/330R in signals SDIO, SDO, LD and STATUS
Power Supply:
- R234 changed from 10K to 9K31 to increase +2V5 up to 2V6
CPU_JTAG_Power_PLL:
- R3 and R5 values swapped (ARM BMS pin).
- Pull-up R10 changed from JRTCK to JTCK
Connectors:
- USB connector CON1 not used.
- CN2 connector (for uTCA clocks) not used.
FPGA_Configuration:
- Q2 changed by a PMOSFET. Footprint error fixed.
CPU_EBI1_FPGA_Memory:
- SPI Flash changed from AT45DB642 to AT45DB321 (Atmel bug). Footprint changed to keep compatibility of two components.
- SPI Flash divisor on SO signal changed to 100/300R
- Added jumper to select/deselect boot memories. Added a GPIO jumper too (Alessandro requirement).
CPU_IO_Ports:
- Resistor for current limiting of LEDs changed to 330R to increase luminosity.
SMI_Link_7-12:
- Removed FPGA free global clock to J3 connector.
FPGA_System_Monitor:
- FPGA global clock connected to CLK10MHZ_EXT signal clock.
FPGA_Peripherals_Control:
- PLL_STAT signal connected to MRCC FPGA pin clock.
- FPGA_RS232_RXD divider changed to 100/330R
SCB_CLKs:
- IC11 and R38 power supply changed to +2V5
RS232_and_USB:
- RS232 R1out divider changed to 100/330R