-- -*- Mode: LUA; tab-width: 2 -*-

peripheral {
	 name = "WR Softcore PLL";
	 hdl_entity = "spll_wb_slave";
	 prefix = "spll";
	 
	 reg {
			name = "SPLL Control/Status Register";
			prefix = "CSR";
			

      field {
         align = 8;
         name = "Period detector reference select";
         prefix = "PER_SEL";
         size = 6;
         type = SLV;
         access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
      };

			field {
				 align = 8;
				 name = "Number of reference channels (max: 32)";
				 prefix = "N_REF";
				 type = SLV;
				 size = 6;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
			};

			field {
				 align = 8;
				 name = "Number of output channels (max: 8)";
				 prefix = "N_OUT";
				 type = SLV;
				 size = 3;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
			};

      field {
         name = "Enable Period Measurement";
         prefix = "PER_EN";
         type = BIT;
         access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
      };
	 };

---------------------------------------------
-- External clock input
---------------------------------------------

   reg {
      name = "External Clock Control Register";
			prefix = "ECCR";

      field {
         name = "Enable External Clock BB Detector";
         prefix = "EXT_EN";
         type = BIT;
         access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
      };


      field {
         name = "External Clock Input Available";
         description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
          0: no support for external 10 MHz clock input.";
         prefix = "EXT_SUPPORTED";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };


      field {
         name = "Enable PPS/phase alignment";
         description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
         right after the pulse on SYNC (PPS) input.\
         write 0: no effect.";
         prefix = "ALIGN_EN";
         type = BIT;
         access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
      };

      field {
         name = "PPS/phase alignment done";
         description = "1: phase alignment triggered by writing to ALIGN_EN done.\
          0: phase alignment in progress.";
         prefix = "ALIGN_DONE";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "External Clock Reference Present";
         description = "1: Reference clock present on the input\
         0: reference input dead";
         prefix = "EXT_REF_PRESENT";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

   };
  

---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
	 reg {
			name = "DMTD Clock Control Register";
			prefix = "DCCR";
			
      field {
         name = "DMTD Clock Undersampling Divider";
         prefix = "GATE_DIV";
         size = 6;
         type = SLV;
         access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
      };
	 };

   reg {
      name = "Reference Channel Undersampling Enable Register";
      prefix = "RCGER";
      
      field {
         name = "Reference Channel Undersampling Enable";
         prefix = "GATE_SEL";
         size = 32;
         type = PASS_THROUGH;
      };
   };

	 reg {
			name = "Output Channel Control Register";
			prefix = "OCCR";

			field {
				 align = 8;
				 name = "Output Channel HW enable flag";
				 prefix = "OUT_EN";
				 type = SLV;
				 size = 8;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
			};

			field {
				 name = "Output Channel locked flag";
				 prefix = "OUT_LOCK";
				 type = SLV;
				 size = 8;
				 access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
			};
	 };
	 
	 reg {
			name = "Reference Channel Enable Register";
			prefix = "RCER";
			
			field {
				 name = "Reference Channel Enable";
				 description = "write 1: enables tag generation on the input channel corresponding to the written bit\
				 write 0: disables tag generation";
				 type = SLV;
				 size = 32;
				 access_bus = READ_WRITE;
				 access_dev = READ_WRITE;
				 load = LOAD_EXT;
			};
	 };

	 reg {
			name = "Output Channel Enable Register";
			prefix = "OCER";
			
			field {
				 name = "Output Channel Enable";
				 description = "write 1: enables tag generation on the output channel corresponding to the written bit\
				 write 0: disables tag generation";
				 type = SLV;
				 size = 8;
				 access_bus = READ_WRITE;
				 access_dev = READ_WRITE;
				 load = LOAD_EXT;
			};
	 };


	 reg {
			name = "HPLL Period Error";
			prefix = "PER_HPLL";
			field {
				 name = "Period error value";
         prefix = "ERROR";
				 type = SLV;
				 size = 16;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
				 ack_read = "tag_hpll_rd_period_o";
			};


			field {
         name = "Period Error Valid";
         prefix = "VALID";
         type = BIT;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
      };

	 };

	 reg {
			name = "Helper DAC Output";
			prefix = "DAC_HPLL";
			
			field {
				 name = "DAC value";
				 type = PASS_THROUGH;
				 size = 16;
			};
	 };

	 reg {
			name = "Main DAC Output";
			prefix = "DAC_MAIN";
			
			field {
				 name = "DAC value";
				 prefix = "VALUE";
				 type = PASS_THROUGH;
				 size = 16;
			};

			field {
				 name = "DAC select";
				 prefix = "DAC_SEL";
				 description = "Selects the output DAC to be updated with VALUE";
				 type = PASS_THROUGH;
				 size = 4;
			};
	 }; 

	 reg {
			name = "Deglitcher threshold";
			prefix = "DEGLITCH_THR";
			
			field {
				 name = "Threshold";
				 type = SLV;
				 size = 16;
				 access_bus = READ_WRITE;
				 access_dev = READ_ONLY;
			};
	 };

   reg {
      name = "Debug FIFO Register - SPLL side";
      prefix = "DFR_SPLL";
      
      field {
         name = "Debug Value";
         prefix = "VALUE";
         size = 31;
         type = PASS_THROUGH;
      };

      field {
         name = "End-of-Sample";
         prefix = "EOS";
         size = 1;
         type = PASS_THROUGH;
      };
   };

	 fifo_reg {
			name = "Debug FIFO Register - Host side";		
			prefix = "DFR_HOST";
			direction = CORE_TO_BUS;		 		 
      size = 8192;

			flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
			flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};

      field {
				 name = "Value";
				 prefix = "VALUE";
				 type = SLV;
				 size = 32;
      };

      field {
         name = "Seq ID";
         prefix = "SEQ_ID";
         type = SLV;
         size = 16;
      };
   };

	 fifo_reg {
			name = "Tag Readout Register";		
			prefix = "TRR";
			direction = CORE_TO_BUS;		 		 
			size = 32;

			flags_dev = {FIFO_FULL, FIFO_EMPTY};
			flags_bus = {FIFO_EMPTY};

			field {
				 name = "Tag value";
				 prefix = "VALUE";
				 type = SLV;
				 size = 24;
			};

			field {
				 name = "Channel ID";
				 description = "Tagged Channel ID: 0-31: reference tags, 32-47: output tags"; 
				 prefix = "CHAN_ID";
				 type = SLV;
				 size = 7;
			};
			field {
				 name = "Discontinuous bit";
				 prefix = "DISC";
				 description = "1: previous tag has been dropped due to FIFO overflow";
				 type = BIT;
			};
	 };



	 irq {
			name = "Got a tag";
			prefix = "TAG";
			trigger = LEVEL_1;
	 };
};


