From a5a61f90ebdee0a1a718802a27fdc3a7fcdba785 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Wed, 17 Nov 2010 12:49:30 +0100
Subject: [PATCH] WR switch: new board-mch changes by Tom

---
 arch/arm/mach-at91/board-whiterabbit-mch.c |   86 +++++++++++++++++----------
 1 files changed, 54 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-at91/board-whiterabbit-mch.c b/arch/arm/mach-at91/board-whiterabbit-mch.c
index 2e5d458..e19ab93 100644
--- a/arch/arm/mach-at91/board-whiterabbit-mch.c
+++ b/arch/arm/mach-at91/board-whiterabbit-mch.c
@@ -97,13 +97,21 @@ static struct flash_platform_data wr_mch_flash_platform __initdata = {
 };
 
 static struct spi_board_info wr_mch_spi_devices[] __initdata = {
-	{
-		.modalias	= "mtd_dataflash",
-		.chip_select	= 0,
-		.max_speed_hz	= 5 * 1000 * 1000,
-		.bus_num	= 0,
-		.platform_data	= &wr_mch_flash_platform
-	}
+  {
+    .modalias	= "mtd_dataflash",
+    .chip_select	= 0,
+    .max_speed_hz	= 5 * 1000 * 1000,
+    .bus_num	= 0,
+    .platform_data	= &wr_mch_flash_platform
+  },
+  {
+    .modalias = "spidev",
+    .chip_select	= 0,
+    .max_speed_hz	= 20 * 1000,
+    .bus_num	= 1
+  }
+
+
 };
 
 /*
@@ -118,19 +126,28 @@ static struct at91_eth_data wr_mch_macb_data __initdata = {
  * WhiteRabbit NIC (wr-nic) stub
  */
 
-#define WR_MINIC_BASE_UP0 0x700a0000
-#define WR_MINIC_BASE_UP1 0x70080000
-
-#define WR_MINIC_BASE_DP0 0x700c0000
-#define WR_MINIC_BASE_DP1 0x700e0000
-#define WR_MINIC_BASE_DP2 0x70100000
-#define WR_MINIC_BASE_DP3 0x70120000
-#define WR_MINIC_BASE_DP4 0x70140000
-#define WR_MINIC_BASE_DP5 0x70160000
-#define WR_MINIC_BASE_DP6 0x70180000
-#define WR_MINIC_BASE_DP7 0x701a0000
-
-#define WR_MINIC_SIZE	  0x20000
+#define _FPGA_BUS_2_ADDR(bus) (0x70000000 + (bus) * 0x10000)
+
+#define FPGA_BASE_REVID     _FPGA_BUS_2_ADDR(0)
+#define FPGA_BASE_GPIO      _FPGA_BUS_2_ADDR(1)
+#define FPGA_BASE_SPIM      _FPGA_BUS_2_ADDR(2)
+#define FPGA_BASE_VIC       _FPGA_BUS_2_ADDR(3)
+#define FPGA_BASE_MINIC_UP1 _FPGA_BUS_2_ADDR(4)
+#define FPGA_BASE_MINIC_UP0 _FPGA_BUS_2_ADDR(5)
+#define FPGA_BASE_MINIC_DP0 _FPGA_BUS_2_ADDR(6)
+#define FPGA_BASE_MINIC_DP1 _FPGA_BUS_2_ADDR(7)
+#define FPGA_BASE_MINIC_DP2 _FPGA_BUS_2_ADDR(8)
+#define FPGA_BASE_MINIC_DP3 _FPGA_BUS_2_ADDR(9)
+#define FPGA_BASE_MINIC_DP4 _FPGA_BUS_2_ADDR(10)
+#define FPGA_BASE_MINIC_DP5 _FPGA_BUS_2_ADDR(11)
+#define FPGA_BASE_MINIC_DP6 _FPGA_BUS_2_ADDR(12)
+#define FPGA_BASE_MINIC_DP7    _FPGA_BUS_2_ADDR(13)
+#define FPGA_BASE_PPS_GEN      _FPGA_BUS_2_ADDR(14)
+#define FPGA_BASE_CALIBRATOR   _FPGA_BUS_2_ADDR(15) 
+#define FPGA_BASE_RTU          _FPGA_BUS_2_ADDR(16) 
+#define FPGA_BASE_RTU_TESTUNIT _FPGA_BUS_2_ADDR(17) 
+
+#define WR_MINIC_SIZE	  0x10000
 
 #define WR_MINIC_IRQ_UP0 0
 #define WR_MINIC_IRQ_UP1 1
@@ -165,7 +182,7 @@ static void __init wr_mch_register_minic_port(int id, int mode, int index, u32 b
   snprintf(buf, sizeof(buf), "wr%c%d", (mode == PORT_UP ? 'u' : 'd'), index);
 
   pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL); // FIXME: add error checking
-  res_list = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
+  res_list = kzalloc(3 * sizeof(struct resource), GFP_KERNEL);
 
   pdev->name = my_strdup("wr_minic");
   pdev->id = id;
@@ -173,7 +190,7 @@ static void __init wr_mch_register_minic_port(int id, int mode, int index, u32 b
   pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
   pdev->dev.platform_data = (void *) my_strdup(buf);
   pdev->resource = res_list;
-  pdev->num_resources = 2;
+  pdev->num_resources = 3;
 
   res_list[0].start = base_addr;
   res_list[0].end = base_addr + WR_MINIC_SIZE - 1;
@@ -183,6 +200,11 @@ static void __init wr_mch_register_minic_port(int id, int mode, int index, u32 b
   res_list[1].end = interrupt;
   res_list[1].flags = IORESOURCE_IRQ;
 
+  res_list[2].start = FPGA_BASE_PPS_GEN;
+  res_list[2].end = FPGA_BASE_PPS_GEN + 0x1000-1;
+  res_list[2].flags = IORESOURCE_MEM;
+
+
   platform_device_register(pdev);
 
 }
@@ -323,16 +345,16 @@ static void __init wr_mch_board_init(void)
 	at91_add_device_i2c(NULL, 0);
 
 	/* initialise the NIC */
-	wr_mch_register_minic_port(0, PORT_UP, 0, WR_MINIC_BASE_UP0, WR_MINIC_IRQ_UP0);
-	wr_mch_register_minic_port(1, PORT_UP, 1, WR_MINIC_BASE_UP1, WR_MINIC_IRQ_UP1);
-	wr_mch_register_minic_port(2, PORT_DOWN, 0, WR_MINIC_BASE_DP0, WR_MINIC_IRQ_DP0);
-	wr_mch_register_minic_port(3, PORT_DOWN, 1, WR_MINIC_BASE_DP1, WR_MINIC_IRQ_DP1);
-	wr_mch_register_minic_port(4, PORT_DOWN, 2, WR_MINIC_BASE_DP2, WR_MINIC_IRQ_DP2);
-	wr_mch_register_minic_port(5, PORT_DOWN, 3, WR_MINIC_BASE_DP3, WR_MINIC_IRQ_DP3);
-	wr_mch_register_minic_port(6, PORT_DOWN, 4, WR_MINIC_BASE_DP4, WR_MINIC_IRQ_DP4);
-	wr_mch_register_minic_port(7, PORT_DOWN, 5, WR_MINIC_BASE_DP5, WR_MINIC_IRQ_DP5);
-	wr_mch_register_minic_port(8, PORT_DOWN, 6, WR_MINIC_BASE_DP6, WR_MINIC_IRQ_DP6);
-	wr_mch_register_minic_port(9, PORT_DOWN, 7, WR_MINIC_BASE_DP7, WR_MINIC_IRQ_DP7);
+	wr_mch_register_minic_port(0, PORT_UP,   0, FPGA_BASE_MINIC_UP0, WR_MINIC_IRQ_UP0);
+	wr_mch_register_minic_port(1, PORT_UP,   1, FPGA_BASE_MINIC_UP1, WR_MINIC_IRQ_UP1);
+	wr_mch_register_minic_port(2, PORT_DOWN, 0, FPGA_BASE_MINIC_DP0, WR_MINIC_IRQ_DP0);
+	wr_mch_register_minic_port(3, PORT_DOWN, 1, FPGA_BASE_MINIC_DP1, WR_MINIC_IRQ_DP1);
+	wr_mch_register_minic_port(4, PORT_DOWN, 2, FPGA_BASE_MINIC_DP2, WR_MINIC_IRQ_DP2);
+	wr_mch_register_minic_port(5, PORT_DOWN, 3, FPGA_BASE_MINIC_DP3, WR_MINIC_IRQ_DP3);
+	wr_mch_register_minic_port(6, PORT_DOWN, 4, FPGA_BASE_MINIC_DP4, WR_MINIC_IRQ_DP4);
+	wr_mch_register_minic_port(7, PORT_DOWN, 5, FPGA_BASE_MINIC_DP5, WR_MINIC_IRQ_DP5);
+	wr_mch_register_minic_port(8, PORT_DOWN, 6, FPGA_BASE_MINIC_DP6, WR_MINIC_IRQ_DP6);
+	wr_mch_register_minic_port(9, PORT_DOWN, 7, FPGA_BASE_MINIC_DP7, WR_MINIC_IRQ_DP7);
 
 	/* shutdown controller, wakeup button (5 msec low) */
 	at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) |
-- 
1.5.6.5

