/*
  Register definitions for slave core: Routing Table Unit (RTU)

  * File           : rtu-regs.h
  * Author         : auto-generated by wbgen2 from rtu-regs.wb
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_RTU
#define __WBGEN2_REGDEFS_RTU

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif


#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: RTU Global Control Register */

/* definitions for field: RTU Global Enable in reg: RTU Global Control Register */
#define RTU_GCR_G_ENA                         WBGEN2_GEN_MASK(0, 1)

/* definitions for field: MFIFO Trigger in reg: RTU Global Control Register */
#define RTU_GCR_MFIFOTRIG                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Hash Poly in reg: RTU Global Control Register */
#define RTU_GCR_POLY_VAL_MASK                 WBGEN2_GEN_MASK(8, 16)
#define RTU_GCR_POLY_VAL_SHIFT                8
#define RTU_GCR_POLY_VAL_W(value)             WBGEN2_GEN_WRITE(value, 8, 16)
#define RTU_GCR_POLY_VAL_R(reg)               WBGEN2_GEN_READ(reg, 8, 16)

/* definitions for field: Version in reg: RTU Global Control Register */
#define RTU_GCR_RTU_VERSION_MASK              WBGEN2_GEN_MASK(24, 4)
#define RTU_GCR_RTU_VERSION_SHIFT             24
#define RTU_GCR_RTU_VERSION_W(value)          WBGEN2_GEN_WRITE(value, 24, 4)
#define RTU_GCR_RTU_VERSION_R(reg)            WBGEN2_GEN_READ(reg, 24, 4)

/* definitions for register: Port Select Register */

/* definitions for field: Port Select in reg: Port Select Register */
#define RTU_PSR_PORT_SEL_MASK                 WBGEN2_GEN_MASK(0, 8)
#define RTU_PSR_PORT_SEL_SHIFT                0
#define RTU_PSR_PORT_SEL_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
#define RTU_PSR_PORT_SEL_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for field: Number of ports in reg: Port Select Register */
#define RTU_PSR_N_PORTS_MASK                  WBGEN2_GEN_MASK(8, 8)
#define RTU_PSR_N_PORTS_SHIFT                 8
#define RTU_PSR_N_PORTS_W(value)              WBGEN2_GEN_WRITE(value, 8, 8)
#define RTU_PSR_N_PORTS_R(reg)                WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for register: Port Control Register */

/* definitions for field: Learning enable in reg: Port Control Register */
#define RTU_PCR_LEARN_EN                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Pass all packets in reg: Port Control Register */
#define RTU_PCR_PASS_ALL                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Pass BPDUs in reg: Port Control Register */
#define RTU_PCR_PASS_BPDU                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Fix priority in reg: Port Control Register */
#define RTU_PCR_FIX_PRIO                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Priority value in reg: Port Control Register */
#define RTU_PCR_PRIO_VAL_MASK                 WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR_PRIO_VAL_SHIFT                4
#define RTU_PCR_PRIO_VAL_W(value)             WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR_PRIO_VAL_R(reg)               WBGEN2_GEN_READ(reg, 4, 3)

/* definitions for field: Unrecognized request behaviour in reg: Port Control Register */
#define RTU_PCR_B_UNREC                       WBGEN2_GEN_MASK(7, 1)

/* definitions for register: VLAN Table Register 1 */

/* definitions for field: VLAN ID in reg: VLAN Table Register 1 */
#define RTU_VTR1_VID_MASK                     WBGEN2_GEN_MASK(0, 12)
#define RTU_VTR1_VID_SHIFT                    0
#define RTU_VTR1_VID_W(value)                 WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_VTR1_VID_R(reg)                   WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: Filtering Database ID in reg: VLAN Table Register 1 */
#define RTU_VTR1_FID_MASK                     WBGEN2_GEN_MASK(12, 8)
#define RTU_VTR1_FID_SHIFT                    12
#define RTU_VTR1_FID_W(value)                 WBGEN2_GEN_WRITE(value, 12, 8)
#define RTU_VTR1_FID_R(reg)                   WBGEN2_GEN_READ(reg, 12, 8)

/* definitions for field: Drop in reg: VLAN Table Register 1 */
#define RTU_VTR1_DROP                         WBGEN2_GEN_MASK(20, 1)

/* definitions for field: Has user-defined priority in reg: VLAN Table Register 1 */
#define RTU_VTR1_HAS_PRIO                     WBGEN2_GEN_MASK(21, 1)

/* definitions for field: Override endpoint-assigned priority in reg: VLAN Table Register 1 */
#define RTU_VTR1_PRIO_OVERRIDE                WBGEN2_GEN_MASK(22, 1)

/* definitions for field: Priority value in reg: VLAN Table Register 1 */
#define RTU_VTR1_PRIO_MASK                    WBGEN2_GEN_MASK(23, 3)
#define RTU_VTR1_PRIO_SHIFT                   23
#define RTU_VTR1_PRIO_W(value)                WBGEN2_GEN_WRITE(value, 23, 3)
#define RTU_VTR1_PRIO_R(reg)                  WBGEN2_GEN_READ(reg, 23, 3)

/* definitions for field: Force VLAN table entry update in reg: VLAN Table Register 1 */
#define RTU_VTR1_UPDATE                       WBGEN2_GEN_MASK(26, 1)

/* definitions for register: VLAN Table Register 2 */

/* definitions for field: Port Mask in reg: VLAN Table Register 2 */
#define RTU_VTR2_PORT_MASK_MASK               WBGEN2_GEN_MASK(0, 32)
#define RTU_VTR2_PORT_MASK_SHIFT              0
#define RTU_VTR2_PORT_MASK_W(value)           WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_VTR2_PORT_MASK_R(reg)             WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: RTU Extension: Control Register */

/* definitions for field: Fast Forward for Broadcast in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FF_MAC_BR                  WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Fast Forward for MAC Range in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FF_MAC_RANGE               WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Fast Forward for MAC Single Entries in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FF_MAC_SINGLE              WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Fast Forward for Link-Limited (Reserved) MACs in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FF_MAC_LL                  WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Fast Forward for PTP frames (PTP over IEEE 802.3 /Ethernet) in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FF_MAC_PTP                 WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Port Mirror Enable in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_MR_ENA                     WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Drop/Forward on FullMatch Full in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_AT_FMATCH_TOO_SLOW         WBGEN2_GEN_MASK(6, 1)

/* definitions for field: HP Priorities Mask in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_PRIO_MASK_MASK             WBGEN2_GEN_MASK(8, 8)
#define RTU_RX_CTR_PRIO_MASK_SHIFT            8
#define RTU_RX_CTR_PRIO_MASK_W(value)         WBGEN2_GEN_WRITE(value, 8, 8)
#define RTU_RX_CTR_PRIO_MASK_R(reg)           WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: HP forward to CPU in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_HP_FW_CPU_ENA              WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Urecognized forward to CPU in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_UREC_FW_CPU_ENA            WBGEN2_GEN_MASK(17, 1)

/* definitions for field: Learn Destination MAC enable in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_LEARN_DST_ENA              WBGEN2_GEN_MASK(18, 1)

/* definitions for field: DBG: Force Fast Match only in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FORCE_FAST_MATCH_ENA       WBGEN2_GEN_MASK(24, 1)

/* definitions for field: DBG: Force Full Match only in reg: RTU Extension: Control Register */
#define RTU_RX_CTR_FORCE_FULL_MATCH_ENA       WBGEN2_GEN_MASK(25, 1)

/* definitions for register: RTU Extension: Fast Forward MAC bits [31:0] (validated on write to RX_FF_MAC_R1). */

/* definitions for field: Fast Forward MAC in reg: RTU Extension: Fast Forward MAC bits [31:0] (validated on write to RX_FF_MAC_R1). */
#define RTU_RX_FF_MAC_R0_LO_MASK              WBGEN2_GEN_MASK(0, 32)
#define RTU_RX_FF_MAC_R0_LO_SHIFT             0
#define RTU_RX_FF_MAC_R0_LO_W(value)          WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_RX_FF_MAC_R0_LO_R(reg)            WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: RTU Extension: Fast Forward MAC and control */

/* definitions for field: Fast Forward MAC in reg: RTU Extension: Fast Forward MAC and control */
#define RTU_RX_FF_MAC_R1_HI_ID_MASK           WBGEN2_GEN_MASK(0, 16)
#define RTU_RX_FF_MAC_R1_HI_ID_SHIFT          0
#define RTU_RX_FF_MAC_R1_HI_ID_W(value)       WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_RX_FF_MAC_R1_HI_ID_R(reg)         WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Fast Forward entry index (single/range) in reg: RTU Extension: Fast Forward MAC and control */
#define RTU_RX_FF_MAC_R1_ID_MASK              WBGEN2_GEN_MASK(16, 8)
#define RTU_RX_FF_MAC_R1_ID_SHIFT             16
#define RTU_RX_FF_MAC_R1_ID_W(value)          WBGEN2_GEN_WRITE(value, 16, 8)
#define RTU_RX_FF_MAC_R1_ID_R(reg)            WBGEN2_GEN_READ(reg, 16, 8)

/* definitions for field: Fast Forward MAC single/range entry in reg: RTU Extension: Fast Forward MAC and control */
#define RTU_RX_FF_MAC_R1_TYPE                 WBGEN2_GEN_MASK(24, 1)

/* definitions for field: Fast Forward MAC valid in reg: RTU Extension: Fast Forward MAC and control */
#define RTU_RX_FF_MAC_R1_VALID                WBGEN2_GEN_MASK(25, 1)

/* definitions for register: RTU Extension: CPU port mask (Link-Limited Frames Fast Forward Mask) */

/* definitions for field:  CPU/LL Mask in reg: RTU Extension: CPU port mask (Link-Limited Frames Fast Forward Mask) */
#define RTU_CPU_PORT_MASK_MASK                WBGEN2_GEN_MASK(0, 32)
#define RTU_CPU_PORT_MASK_SHIFT               0
#define RTU_CPU_PORT_MASK_W(value)            WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_CPU_PORT_MASK_R(reg)              WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1 */

/* definitions for field: DST/SRC Mirror port in reg: RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1 */
#define RTU_RX_MP_R0_DST_SRC                  WBGEN2_GEN_MASK(0, 1)

/* definitions for field: RX/TX mirror port source in reg: RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1 */
#define RTU_RX_MP_R0_RX_TX                    WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Mirrored Port MASK Index in reg: RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1 */
#define RTU_RX_MP_R0_MASK_ID_MASK             WBGEN2_GEN_MASK(16, 16)
#define RTU_RX_MP_R0_MASK_ID_SHIFT            16
#define RTU_RX_MP_R0_MASK_ID_W(value)         WBGEN2_GEN_WRITE(value, 16, 16)
#define RTU_RX_MP_R0_MASK_ID_R(reg)           WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RTU Extension: Mirroring Ports Control Register 1 */

/* definitions for field: Mirror Port MASK in reg: RTU Extension: Mirroring Ports Control Register 1 */
#define RTU_RX_MP_R1_MASK_MASK                WBGEN2_GEN_MASK(0, 32)
#define RTU_RX_MP_R1_MASK_SHIFT               0
#define RTU_RX_MP_R1_MASK_W(value)            WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_RX_MP_R1_MASK_R(reg)              WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Interrupt disable register */

/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt disable register */
#define RTU_EIC_IDR_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt enable register */
#define RTU_EIC_IER_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt mask register */
#define RTU_EIC_IMR_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt status register */
#define RTU_EIC_ISR_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */

/* definitions for field: Destination MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_UFIFO_R0_DMAC_LO_MASK             WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R0_DMAC_LO_SHIFT            0
#define RTU_UFIFO_R0_DMAC_LO_W(value)         WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R0_DMAC_LO_R(reg)           WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */

/* definitions for field: Destination MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_UFIFO_R1_DMAC_HI_MASK             WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R1_DMAC_HI_SHIFT            0
#define RTU_UFIFO_R1_DMAC_HI_W(value)         WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R1_DMAC_HI_R(reg)           WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */

/* definitions for field: Source MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_UFIFO_R2_SMAC_LO_MASK             WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R2_SMAC_LO_SHIFT            0
#define RTU_UFIFO_R2_SMAC_LO_W(value)         WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R2_SMAC_LO_R(reg)           WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */

/* definitions for field: Source MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_UFIFO_R3_SMAC_HI_MASK             WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R3_SMAC_HI_SHIFT            0
#define RTU_UFIFO_R3_SMAC_HI_W(value)         WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R3_SMAC_HI_R(reg)           WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */

/* definitions for field: VLAN Identifier in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_VID_MASK                 WBGEN2_GEN_MASK(0, 12)
#define RTU_UFIFO_R4_VID_SHIFT                0
#define RTU_UFIFO_R4_VID_W(value)             WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_UFIFO_R4_VID_R(reg)               WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: Priority in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PRIO_MASK                WBGEN2_GEN_MASK(12, 3)
#define RTU_UFIFO_R4_PRIO_SHIFT               12
#define RTU_UFIFO_R4_PRIO_W(value)            WBGEN2_GEN_WRITE(value, 12, 3)
#define RTU_UFIFO_R4_PRIO_R(reg)              WBGEN2_GEN_READ(reg, 12, 3)

/* definitions for field: Port ID in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PID_MASK                 WBGEN2_GEN_MASK(16, 8)
#define RTU_UFIFO_R4_PID_SHIFT                16
#define RTU_UFIFO_R4_PID_W(value)             WBGEN2_GEN_WRITE(value, 16, 8)
#define RTU_UFIFO_R4_PID_R(reg)               WBGEN2_GEN_READ(reg, 16, 8)

/* definitions for field: VID valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_VID                  WBGEN2_GEN_MASK(24, 1)

/* definitions for field: PRIO valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_PRIO                 WBGEN2_GEN_MASK(25, 1)

/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */

/* definitions for field: FIFO empty flag in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_EMPTY                   WBGEN2_GEN_MASK(17, 1)

/* definitions for field: FIFO counter in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_USEDW_MASK              WBGEN2_GEN_MASK(0, 7)
#define RTU_UFIFO_CSR_USEDW_SHIFT             0
#define RTU_UFIFO_CSR_USEDW_W(value)          WBGEN2_GEN_WRITE(value, 0, 7)
#define RTU_UFIFO_CSR_USEDW_R(reg)            WBGEN2_GEN_READ(reg, 0, 7)

/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */

/* definitions for field: Address/data select in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_MFIFO_R0_AD_SEL                   WBGEN2_GEN_MASK(0, 1)

/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */

/* definitions for field: Address/data value in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_MFIFO_R1_AD_VAL_MASK              WBGEN2_GEN_MASK(0, 32)
#define RTU_MFIFO_R1_AD_VAL_SHIFT             0
#define RTU_MFIFO_R1_AD_VAL_W(value)          WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_MFIFO_R1_AD_VAL_R(reg)            WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */

/* definitions for field: FIFO full flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_FULL                    WBGEN2_GEN_MASK(16, 1)

/* definitions for field: FIFO empty flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_EMPTY                   WBGEN2_GEN_MASK(17, 1)

/* definitions for field: FIFO counter in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_USEDW_MASK              WBGEN2_GEN_MASK(0, 6)
#define RTU_MFIFO_CSR_USEDW_SHIFT             0
#define RTU_MFIFO_CSR_USEDW_W(value)          WBGEN2_GEN_WRITE(value, 0, 6)
#define RTU_MFIFO_CSR_USEDW_R(reg)            WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for RAM: Aging bitmap for main hashtable */
#define RTU_ARAM_BASE 0x00000400 /* base address */                                
#define RTU_ARAM_BYTES 0x00000400 /* size in bytes */                               
#define RTU_ARAM_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */        

PACKED struct RTU_WB {
  /* [0x0]: REG RTU Global Control Register */
  uint32_t GCR;
  /* [0x4]: REG Port Select Register */
  uint32_t PSR;
  /* [0x8]: REG Port Control Register */
  uint32_t PCR;
  /* [0xc]: REG VLAN Table Register 1 */
  uint32_t VTR1;
  /* [0x10]: REG VLAN Table Register 2 */
  uint32_t VTR2;
  /* [0x14]: REG RTU Extension: Control Register */
  uint32_t RX_CTR;
  /* [0x18]: REG RTU Extension: Fast Forward MAC bits [31:0] (validated on write to RX_FF_MAC_R1). */
  uint32_t RX_FF_MAC_R0;
  /* [0x1c]: REG RTU Extension: Fast Forward MAC and control */
  uint32_t RX_FF_MAC_R1;
  /* [0x20]: REG RTU Extension: CPU port mask (Link-Limited Frames Fast Forward Mask) */
  uint32_t CPU_PORT;
  /* [0x24]: REG RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1 */
  uint32_t RX_MP_R0;
  /* [0x28]: REG RTU Extension: Mirroring Ports Control Register 1 */
  uint32_t RX_MP_R1;
  /* padding to: 16 words */
  uint32_t __padding_0[5];
  /* [0x40]: REG Interrupt disable register */
  uint32_t EIC_IDR;
  /* [0x44]: REG Interrupt enable register */
  uint32_t EIC_IER;
  /* [0x48]: REG Interrupt mask register */
  uint32_t EIC_IMR;
  /* [0x4c]: REG Interrupt status register */
  uint32_t EIC_ISR;
  /* [0x50]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
  uint32_t UFIFO_R0;
  /* [0x54]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
  uint32_t UFIFO_R1;
  /* [0x58]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
  uint32_t UFIFO_R2;
  /* [0x5c]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
  uint32_t UFIFO_R3;
  /* [0x60]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
  uint32_t UFIFO_R4;
  /* [0x64]: REG FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
  uint32_t UFIFO_CSR;
  /* [0x68]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
  uint32_t MFIFO_R0;
  /* [0x6c]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
  uint32_t MFIFO_R1;
  /* [0x70]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
  uint32_t MFIFO_CSR;
  /* padding to: 256 words */
  uint32_t __padding_1[227];
  /* [0x400 - 0x7ff]: RAM Aging bitmap for main hashtable, 256 32-bit words, 32-bit aligned, word-addressable */
  uint32_t ARAM [256];
};

#endif
