/*
  Register definitions for slave core: Vectored Interrupt Controller (VIC)

  * File           : here.h
  * Author         : auto-generated by wbgen2 from wb_slave_vic.wb
  * Created        : Thu Jul 14 15:43:13 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_vic.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WB_SLAVE_VIC_WB
#define __WBGEN2_REGDEFS_WB_SLAVE_VIC_WB

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: VIC Control Register */

/* definitions for field: VIC Enable in reg: VIC Control Register */
#define VIC_CTL_ENABLE                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: VIC output polarity in reg: VIC Control Register */
#define VIC_CTL_POL                           WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Emulate Edge sensitive output in reg: VIC Control Register */
#define VIC_CTL_EMU_EDGE                      WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Emulated Edge pulse timer in reg: VIC Control Register */
#define VIC_CTL_EMU_LEN_MASK                  WBGEN2_GEN_MASK(3, 16)
#define VIC_CTL_EMU_LEN_SHIFT                 3
#define VIC_CTL_EMU_LEN_W(value)              WBGEN2_GEN_WRITE(value, 3, 16)
#define VIC_CTL_EMU_LEN_R(reg)                WBGEN2_GEN_READ(reg, 3, 16)

/* definitions for register: Raw Interrupt Status Register */

/* definitions for register: Interrupt Enable Register */

/* definitions for register: Interrupt Disable Register */

/* definitions for register: Interrupt Mask Register */

/* definitions for register: Vector Address Register */

/* definitions for register: Software Interrupt Register */

/* definitions for register: End Of Interrupt Acknowledge Register */
/* definitions for RAM: Interrupt Vector Table */
#define VIC_IVT_RAM_BASE 0x00000080 /* base address */                                
#define VIC_IVT_RAM_BYTES 0x00000080 /* size in bytes */                               
#define VIC_IVT_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */        
/* [0x0]: REG VIC Control Register */
#define VIC_REG_CTL 0x00000000
/* [0x4]: REG Raw Interrupt Status Register */
#define VIC_REG_RISR 0x00000004
/* [0x8]: REG Interrupt Enable Register */
#define VIC_REG_IER 0x00000008
/* [0xc]: REG Interrupt Disable Register */
#define VIC_REG_IDR 0x0000000c
/* [0x10]: REG Interrupt Mask Register */
#define VIC_REG_IMR 0x00000010
/* [0x14]: REG Vector Address Register */
#define VIC_REG_VAR 0x00000014
/* [0x18]: REG Software Interrupt Register */
#define VIC_REG_SWIR 0x00000018
/* [0x1c]: REG End Of Interrupt Acknowledge Register */
#define VIC_REG_EOIR 0x0000001c
#endif
