/*
  Register definitions for slave core: Mini NIC for WhiteRabbit

  * File           : ../../../software/include/hw/minic_regs.h
  * Author         : auto-generated by wbgen2 from mini_nic.wb
  * Created        : Fri Jul 30 00:33:27 2010
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_MINI_NIC_WB
#define __WBGEN2_REGDEFS_MINI_NIC_WB

//#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: miNIC Control Register */

/* definitions for field: TX DMA start in reg: miNIC Control Register */
#define MINIC_MCR_TX_START                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: TX DMA idle in reg: miNIC Control Register */
#define MINIC_MCR_TX_IDLE                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR                    WBGEN2_GEN_MASK(2, 1)

/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY                    WBGEN2_GEN_MASK(8, 1)

/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL                     WBGEN2_GEN_MASK(9, 1)

/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN                       WBGEN2_GEN_MASK(10, 1)

/* definitions for register: TX DMA Address */

/* definitions for register: RX DMA Address */

/* definitions for register: RX buffer size register */

/* definitions for register: Interrupt disable register */

/* definitions for field: TX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TX                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: RX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_RX                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: TX timestamp available in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TXTS                    WBGEN2_GEN_MASK(2, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: TX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_TX                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: RX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_RX                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: TX timestamp available in reg: Interrupt enable register */
#define MINIC_EIC_IER_TXTS                    WBGEN2_GEN_MASK(2, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: TX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TX                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: RX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_RX                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: TX timestamp available in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TXTS                    WBGEN2_GEN_MASK(2, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: TX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_TX                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: RX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_RX                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: TX timestamp available in reg: Interrupt status register */
#define MINIC_EIC_ISR_TXTS                    WBGEN2_GEN_MASK(2, 1)

/* definitions for register: FIFO 'TX timestamp FIFO' data output register 0 */

/* definitions for field: Timestamp value in reg: FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_TSFIFO_R0_TSVAL_MASK            WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSFIFO_R0_TSVAL_SHIFT           0
#define MINIC_TSFIFO_R0_TSVAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSFIFO_R0_TSVAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: FIFO 'TX timestamp FIFO' data output register 1 */

/* definitions for field: Port ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_PID_MASK              WBGEN2_GEN_MASK(0, 5)
#define MINIC_TSFIFO_R1_PID_SHIFT             0
#define MINIC_TSFIFO_R1_PID_W(value)          WBGEN2_GEN_WRITE(value, 0, 5)
#define MINIC_TSFIFO_R1_PID_R(reg)            WBGEN2_GEN_READ(reg, 0, 5)

/* definitions for field: Frame ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_FID_MASK              WBGEN2_GEN_MASK(5, 16)
#define MINIC_TSFIFO_R1_FID_SHIFT             5
#define MINIC_TSFIFO_R1_FID_W(value)          WBGEN2_GEN_WRITE(value, 5, 16)
#define MINIC_TSFIFO_R1_FID_R(reg)            WBGEN2_GEN_READ(reg, 5, 16)

/* definitions for register: FIFO 'TX timestamp FIFO' control/status register */

/* definitions for field: FIFO empty flag in reg: FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_TSFIFO_CSR_EMPTY                WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_AVAIL 0x0000000c
/* [0x20]: REG Interrupt disable register */
#define MINIC_REG_EIC_IDR 0x00000020
/* [0x24]: REG Interrupt enable register */
#define MINIC_REG_EIC_IER 0x00000024
/* [0x28]: REG Interrupt mask register */
#define MINIC_REG_EIC_IMR 0x00000028
/* [0x2c]: REG Interrupt status register */
#define MINIC_REG_EIC_ISR 0x0000002c
/* [0x30]: REG FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_REG_TSFIFO_R0 0x00000030
/* [0x34]: REG FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_REG_TSFIFO_R1 0x00000034
/* [0x38]: REG FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_REG_TSFIFO_CSR 0x00000038

#define MINIC_PBUF_SIZE_LOG2 (12)
#define MINIC_PBUF_SIZE (1<<(MINIC_PBUF_SIZE_LOG2+2))

#define MINIC_BASE_IO 0x0
#define MINIC_BASE_PBUF (2<<(MINIC_PBUF_SIZE_LOG2+2))
#define MINIC_BASE_ENDPOINT (1<<(MINIC_PBUF_SIZE_LOG2+2))
#define MINIC_BASE_GIGASPY (3<<(MINIC_PBUF_SIZE_LOG2+2))


#endif
