/*
  Register definitions for slave core: RTU testing unit

  * File           : 1.h
  * Author         : auto-generated by wbgen2 from rtu_testunit_wb.wb
  * Created        : Mon Nov  1 14:52:06 2010
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_testunit_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_RTU_TESTUNIT_WB_WB
#define __WBGEN2_REGDEFS_RTU_TESTUNIT_WB_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: FIFO Polling Register */

/* definitions for register: Interrupt disable register */

/* definitions for field: FIFO Not Empty in reg: Interrupt disable register */
#define RTT_EIC_IDR_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: FIFO Not Empty in reg: Interrupt enable register */
#define RTT_EIC_IER_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: FIFO Not Empty in reg: Interrupt mask register */
#define RTT_EIC_IMR_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: FIFO Not Empty in reg: Interrupt status register */
#define RTT_EIC_ISR_NEMPTY                    WBGEN2_GEN_MASK(0, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 0' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 0' data output register 0 */
#define RTT_RFIFO_CH0_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH0_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH0_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH0_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 0' data output register 0 */
#define RTT_RFIFO_CH0_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH0_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH0_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH0_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 0' data output register 0 */
#define RTT_RFIFO_CH0_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 1' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 1' data output register 0 */
#define RTT_RFIFO_CH1_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH1_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH1_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH1_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 1' data output register 0 */
#define RTT_RFIFO_CH1_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH1_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH1_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH1_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 1' data output register 0 */
#define RTT_RFIFO_CH1_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 2' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 2' data output register 0 */
#define RTT_RFIFO_CH2_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH2_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH2_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH2_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 2' data output register 0 */
#define RTT_RFIFO_CH2_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH2_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH2_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH2_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 2' data output register 0 */
#define RTT_RFIFO_CH2_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 3' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 3' data output register 0 */
#define RTT_RFIFO_CH3_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH3_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH3_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH3_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 3' data output register 0 */
#define RTT_RFIFO_CH3_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH3_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH3_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH3_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 3' data output register 0 */
#define RTT_RFIFO_CH3_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 4' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 4' data output register 0 */
#define RTT_RFIFO_CH4_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH4_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH4_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH4_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 4' data output register 0 */
#define RTT_RFIFO_CH4_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH4_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH4_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH4_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 4' data output register 0 */
#define RTT_RFIFO_CH4_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 5' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 5' data output register 0 */
#define RTT_RFIFO_CH5_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH5_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH5_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH5_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 5' data output register 0 */
#define RTT_RFIFO_CH5_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH5_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH5_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH5_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 5' data output register 0 */
#define RTT_RFIFO_CH5_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 6' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 6' data output register 0 */
#define RTT_RFIFO_CH6_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH6_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH6_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH6_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 6' data output register 0 */
#define RTT_RFIFO_CH6_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH6_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH6_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH6_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 6' data output register 0 */
#define RTT_RFIFO_CH6_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 7' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 7' data output register 0 */
#define RTT_RFIFO_CH7_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH7_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH7_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH7_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 7' data output register 0 */
#define RTT_RFIFO_CH7_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH7_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH7_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH7_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 7' data output register 0 */
#define RTT_RFIFO_CH7_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 8' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 8' data output register 0 */
#define RTT_RFIFO_CH8_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH8_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH8_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH8_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 8' data output register 0 */
#define RTT_RFIFO_CH8_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH8_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH8_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH8_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 8' data output register 0 */
#define RTT_RFIFO_CH8_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

/* definitions for register: FIFO 'Response FIFO for RTU channel 9' data output register 0 */

/* definitions for field: Destination port mask in reg: FIFO 'Response FIFO for RTU channel 9' data output register 0 */
#define RTT_RFIFO_CH9_R0_DPM_MASK             WBGEN2_GEN_MASK(0, 11)
#define RTT_RFIFO_CH9_R0_DPM_SHIFT            0
#define RTT_RFIFO_CH9_R0_DPM_W(value)         WBGEN2_GEN_WRITE(value, 0, 11)
#define RTT_RFIFO_CH9_R0_DPM_R(reg)           WBGEN2_GEN_READ(reg, 0, 11)

/* definitions for field: Final priority in reg: FIFO 'Response FIFO for RTU channel 9' data output register 0 */
#define RTT_RFIFO_CH9_R0_PRIO_MASK            WBGEN2_GEN_MASK(11, 3)
#define RTT_RFIFO_CH9_R0_PRIO_SHIFT           11
#define RTT_RFIFO_CH9_R0_PRIO_W(value)        WBGEN2_GEN_WRITE(value, 11, 3)
#define RTT_RFIFO_CH9_R0_PRIO_R(reg)          WBGEN2_GEN_READ(reg, 11, 3)

/* definitions for field: Drop packet flag in reg: FIFO 'Response FIFO for RTU channel 9' data output register 0 */
#define RTT_RFIFO_CH9_R0_DROP                 WBGEN2_GEN_MASK(14, 1)

PACKED struct RTT_WB {
  /* [0x0]: REG FIFO Polling Register */
  uint32_t FPR;
  /* padding to: 8 words */
  uint32_t __padding_0[7];
  /* [0x20]: REG Interrupt disable register */
  uint32_t EIC_IDR;
  /* [0x24]: REG Interrupt enable register */
  uint32_t EIC_IER;
  /* [0x28]: REG Interrupt mask register */
  uint32_t EIC_IMR;
  /* [0x2c]: REG Interrupt status register */
  uint32_t EIC_ISR;
  /* [0x30]: REG FIFO 'Response FIFO for RTU channel 0' data output register 0 */
  uint32_t RFIFO_CH0_R0;
  /* [0x34]: REG FIFO 'Response FIFO for RTU channel 1' data output register 0 */
  uint32_t RFIFO_CH1_R0;
  /* [0x38]: REG FIFO 'Response FIFO for RTU channel 2' data output register 0 */
  uint32_t RFIFO_CH2_R0;
  /* [0x3c]: REG FIFO 'Response FIFO for RTU channel 3' data output register 0 */
  uint32_t RFIFO_CH3_R0;
  /* [0x40]: REG FIFO 'Response FIFO for RTU channel 4' data output register 0 */
  uint32_t RFIFO_CH4_R0;
  /* [0x44]: REG FIFO 'Response FIFO for RTU channel 5' data output register 0 */
  uint32_t RFIFO_CH5_R0;
  /* [0x48]: REG FIFO 'Response FIFO for RTU channel 6' data output register 0 */
  uint32_t RFIFO_CH6_R0;
  /* [0x4c]: REG FIFO 'Response FIFO for RTU channel 7' data output register 0 */
  uint32_t RFIFO_CH7_R0;
  /* [0x50]: REG FIFO 'Response FIFO for RTU channel 8' data output register 0 */
  uint32_t RFIFO_CH8_R0;
  /* [0x54]: REG FIFO 'Response FIFO for RTU channel 9' data output register 0 */
  uint32_t RFIFO_CH9_R0;
};

#endif
