/*
  Register definitions for slave core: DMTD Helper PLL

  * File           : ../../../software/include/hw/hpll_regs.h
  * Author         : auto-generated by wbgen2 from hpll_wb.wb
  * Created        : Mon Jun 21 14:16:43 2010
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE hpll_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_HPLL_WB_WB
#define __WBGEN2_REGDEFS_HPLL_WB_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: HPLL Control Register */

/* definitions for field: PLL Enable in reg: HPLL Control Register */
#define HPLL_PCR_ENABLE                       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: PLL Force Freq mode in reg: HPLL Control Register */
#define HPLL_PCR_FORCE_F                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: DAC serial clock select in reg: HPLL Control Register */
#define HPLL_PCR_DAC_CLKSEL_MASK              WBGEN2_GEN_MASK(4, 3)
#define HPLL_PCR_DAC_CLKSEL_SHIFT             4
#define HPLL_PCR_DAC_CLKSEL_W(value)          WBGEN2_GEN_WRITE(value, 4, 3)
#define HPLL_PCR_DAC_CLKSEL_R(reg)            WBGEN2_GEN_READ(reg, 4, 3)

/* definitions for field: Phase detector gating period in reg: HPLL Control Register */
#define HPLL_PCR_PD_GATE_MASK                 WBGEN2_GEN_MASK(8, 3)
#define HPLL_PCR_PD_GATE_SHIFT                8
#define HPLL_PCR_PD_GATE_W(value)             WBGEN2_GEN_WRITE(value, 8, 3)
#define HPLL_PCR_PD_GATE_R(reg)               WBGEN2_GEN_READ(reg, 8, 3)

/* definitions for field: Reference clock input select in reg: HPLL Control Register */
#define HPLL_PCR_REFSEL_MASK                  WBGEN2_GEN_MASK(11, 2)
#define HPLL_PCR_REFSEL_SHIFT                 11
#define HPLL_PCR_REFSEL_W(value)              WBGEN2_GEN_WRITE(value, 11, 2)
#define HPLL_PCR_REFSEL_R(reg)                WBGEN2_GEN_READ(reg, 11, 2)

/* definitions for field: PLL Reset in reg: HPLL Control Register */
#define HPLL_PCR_SWRST                        WBGEN2_GEN_MASK(31, 1)

/* definitions for register: HPLL Divider Register */

/* definitions for field: Reference divider in reg: HPLL Divider Register */
#define HPLL_DIVR_DIV_REF_MASK                WBGEN2_GEN_MASK(0, 16)
#define HPLL_DIVR_DIV_REF_SHIFT               0
#define HPLL_DIVR_DIV_REF_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_DIVR_DIV_REF_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Feedback divider in reg: HPLL Divider Register */
#define HPLL_DIVR_DIV_FB_MASK                 WBGEN2_GEN_MASK(16, 16)
#define HPLL_DIVR_DIV_FB_SHIFT                16
#define HPLL_DIVR_DIV_FB_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_DIVR_DIV_FB_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: HPLL Frequency Branch Gain Register */

/* definitions for field: Proportional gain (Kp) in reg: HPLL Frequency Branch Gain Register */
#define HPLL_FBGR_F_KP_MASK                   WBGEN2_GEN_MASK(0, 16)
#define HPLL_FBGR_F_KP_SHIFT                  0
#define HPLL_FBGR_F_KP_W(value)               WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_FBGR_F_KP_R(reg)                 WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Integral gain (Ki) in reg: HPLL Frequency Branch Gain Register */
#define HPLL_FBGR_F_KI_MASK                   WBGEN2_GEN_MASK(16, 16)
#define HPLL_FBGR_F_KI_SHIFT                  16
#define HPLL_FBGR_F_KI_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_FBGR_F_KI_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: HPLL Phase Branch Gain Register */

/* definitions for field: Proportional gain (Kp) in reg: HPLL Phase Branch Gain Register */
#define HPLL_PBGR_P_KP_MASK                   WBGEN2_GEN_MASK(0, 16)
#define HPLL_PBGR_P_KP_SHIFT                  0
#define HPLL_PBGR_P_KP_W(value)               WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_PBGR_P_KP_R(reg)                 WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Integral gain (Ki) in reg: HPLL Phase Branch Gain Register */
#define HPLL_PBGR_P_KI_MASK                   WBGEN2_GEN_MASK(16, 16)
#define HPLL_PBGR_P_KI_SHIFT                  16
#define HPLL_PBGR_P_KI_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_PBGR_P_KI_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: HPLL Lock Detect Control Register */

/* definitions for field: Phase Lock detect threshold in reg: HPLL Lock Detect Control Register */
#define HPLL_LDCR_LD_THR_MASK                 WBGEN2_GEN_MASK(0, 8)
#define HPLL_LDCR_LD_THR_SHIFT                0
#define HPLL_LDCR_LD_THR_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
#define HPLL_LDCR_LD_THR_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for field: Lock detect samples in reg: HPLL Lock Detect Control Register */
#define HPLL_LDCR_LD_SAMP_MASK                WBGEN2_GEN_MASK(8, 8)
#define HPLL_LDCR_LD_SAMP_SHIFT               8
#define HPLL_LDCR_LD_SAMP_W(value)            WBGEN2_GEN_WRITE(value, 8, 8)
#define HPLL_LDCR_LD_SAMP_R(reg)              WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for register: HPLL Frequency branch control register */

/* definitions for field: Frequency detector gating period in reg: HPLL Frequency branch control register */
#define HPLL_FBCR_FD_GATE_MASK                WBGEN2_GEN_MASK(0, 3)
#define HPLL_FBCR_FD_GATE_SHIFT               0
#define HPLL_FBCR_FD_GATE_W(value)            WBGEN2_GEN_WRITE(value, 0, 3)
#define HPLL_FBCR_FD_GATE_R(reg)              WBGEN2_GEN_READ(reg, 0, 3)

/* definitions for field: Frequency error setpoint in reg: HPLL Frequency branch control register */
#define HPLL_FBCR_FERR_SET_MASK               WBGEN2_GEN_MASK(4, 12)
#define HPLL_FBCR_FERR_SET_SHIFT              4
#define HPLL_FBCR_FERR_SET_W(value)           WBGEN2_GEN_WRITE(value, 4, 12)
#define HPLL_FBCR_FERR_SET_R(reg)             WBGEN2_GEN_READ(reg, 4, 12)

/* definitions for register: HPLL Status Register */

/* definitions for field: Frequency lock in reg: HPLL Status Register */
#define HPLL_PSR_FREQ_LK                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Phase lock in reg: HPLL Status Register */
#define HPLL_PSR_PHASE_LK                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Loss-of-lock indicator in reg: HPLL Status Register */
#define HPLL_PSR_LOCK_LOST                    WBGEN2_GEN_MASK(2, 1)

/* definitions for register: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */

/* definitions for field: Freq/phase error in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_ERR_VAL_MASK            WBGEN2_GEN_MASK(0, 12)
#define HPLL_RFIFO_R0_ERR_VAL_SHIFT           0
#define HPLL_RFIFO_R0_ERR_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 12)
#define HPLL_RFIFO_R0_ERR_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: Freq/phase mode in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_FP_MODE                 WBGEN2_GEN_MASK(15, 1)

/* definitions for field: DAC output in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_DAC_VAL_MASK            WBGEN2_GEN_MASK(16, 16)
#define HPLL_RFIFO_R0_DAC_VAL_SHIFT           16
#define HPLL_RFIFO_R0_DAC_VAL_W(value)        WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_RFIFO_R0_DAC_VAL_R(reg)          WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: FIFO 'HPLL Phase/Output record FIFO' control/status register */

/* definitions for field: FIFO empty flag in reg: FIFO 'HPLL Phase/Output record FIFO' control/status register */
#define HPLL_RFIFO_CSR_EMPTY                  WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG HPLL Control Register */
#define HPLL_REG_PCR 0x00000000
/* [0x4]: REG HPLL Divider Register */
#define HPLL_REG_DIVR 0x00000004
/* [0x8]: REG HPLL Frequency Branch Gain Register */
#define HPLL_REG_FBGR 0x00000008
/* [0xc]: REG HPLL Phase Branch Gain Register */
#define HPLL_REG_PBGR 0x0000000c
/* [0x10]: REG HPLL Lock Detect Control Register */
#define HPLL_REG_LDCR 0x00000010
/* [0x14]: REG HPLL Frequency branch control register */
#define HPLL_REG_FBCR 0x00000014
/* [0x18]: REG HPLL Status Register */
#define HPLL_REG_PSR 0x00000018
/* [0x1c]: REG FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_REG_RFIFO_R0 0x0000001c
/* [0x20]: REG FIFO 'HPLL Phase/Output record FIFO' control/status register */
#define HPLL_REG_RFIFO_CSR 0x00000020
#endif
