/*
  Register definitions for slave core: DMTD phase-shifting PLL

  * File           : ../../../software/include/hw/dmpll_regs.h
  * Author         : auto-generated by wbgen2 from dmpll_wb.wb
  * Created        : Fri Jul 23 20:52:22 2010
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dmpll_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_DMPLL_WB_WB
#define __WBGEN2_REGDEFS_DMPLL_WB_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: DMPLL Control Register */

/* definitions for field: DMPLL Enable in reg: DMPLL Control Register */
#define DMPLL_PCR_ENABLE                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: DMPLL Force Freq mode in reg: DMPLL Control Register */
#define DMPLL_PCR_FORCE_F                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: DAC serial clock select in reg: DMPLL Control Register */
#define DMPLL_PCR_DAC_CLKSEL_MASK             WBGEN2_GEN_MASK(4, 3)
#define DMPLL_PCR_DAC_CLKSEL_SHIFT            4
#define DMPLL_PCR_DAC_CLKSEL_W(value)         WBGEN2_GEN_WRITE(value, 4, 3)
#define DMPLL_PCR_DAC_CLKSEL_R(reg)           WBGEN2_GEN_READ(reg, 4, 3)

/* definitions for field: Reference clock input select in reg: DMPLL Control Register */
#define DMPLL_PCR_REFSEL_MASK                 WBGEN2_GEN_MASK(8, 2)
#define DMPLL_PCR_REFSEL_SHIFT                8
#define DMPLL_PCR_REFSEL_W(value)             WBGEN2_GEN_WRITE(value, 8, 2)
#define DMPLL_PCR_REFSEL_R(reg)               WBGEN2_GEN_READ(reg, 8, 2)

/* definitions for field: Phase shifter speed in reg: DMPLL Control Register */
#define DMPLL_PCR_PS_SPEED_MASK               WBGEN2_GEN_MASK(10, 12)
#define DMPLL_PCR_PS_SPEED_SHIFT              10
#define DMPLL_PCR_PS_SPEED_W(value)           WBGEN2_GEN_WRITE(value, 10, 12)
#define DMPLL_PCR_PS_SPEED_R(reg)             WBGEN2_GEN_READ(reg, 10, 12)

/* definitions for field: PLL Reset in reg: DMPLL Control Register */
#define DMPLL_PCR_SWRST                       WBGEN2_GEN_MASK(31, 1)

/* definitions for register: DMPLL Frequency Branch Gain Register */

/* definitions for field: Proportional gain (Kp) in reg: DMPLL Frequency Branch Gain Register */
#define DMPLL_FBGR_F_KP_MASK                  WBGEN2_GEN_MASK(0, 16)
#define DMPLL_FBGR_F_KP_SHIFT                 0
#define DMPLL_FBGR_F_KP_W(value)              WBGEN2_GEN_WRITE(value, 0, 16)
#define DMPLL_FBGR_F_KP_R(reg)                WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Integral gain (Ki) in reg: DMPLL Frequency Branch Gain Register */
#define DMPLL_FBGR_F_KI_MASK                  WBGEN2_GEN_MASK(16, 16)
#define DMPLL_FBGR_F_KI_SHIFT                 16
#define DMPLL_FBGR_F_KI_W(value)              WBGEN2_GEN_WRITE(value, 16, 16)
#define DMPLL_FBGR_F_KI_R(reg)                WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: DMPLL Phase Branch Gain Register */

/* definitions for field: Proportional gain (Kp) in reg: DMPLL Phase Branch Gain Register */
#define DMPLL_PBGR_P_KP_MASK                  WBGEN2_GEN_MASK(0, 16)
#define DMPLL_PBGR_P_KP_SHIFT                 0
#define DMPLL_PBGR_P_KP_W(value)              WBGEN2_GEN_WRITE(value, 0, 16)
#define DMPLL_PBGR_P_KP_R(reg)                WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Integral gain (Ki) in reg: DMPLL Phase Branch Gain Register */
#define DMPLL_PBGR_P_KI_MASK                  WBGEN2_GEN_MASK(16, 16)
#define DMPLL_PBGR_P_KI_SHIFT                 16
#define DMPLL_PBGR_P_KI_W(value)              WBGEN2_GEN_WRITE(value, 16, 16)
#define DMPLL_PBGR_P_KI_R(reg)                WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: DMPLL Lock Detect Control Register */

/* definitions for field: Lock detect threshold in reg: DMPLL Lock Detect Control Register */
#define DMPLL_LDCR_LD_THR_MASK                WBGEN2_GEN_MASK(0, 12)
#define DMPLL_LDCR_LD_THR_SHIFT               0
#define DMPLL_LDCR_LD_THR_W(value)            WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_LDCR_LD_THR_R(reg)              WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: Lock detect samples in reg: DMPLL Lock Detect Control Register */
#define DMPLL_LDCR_LD_SAMP_MASK               WBGEN2_GEN_MASK(16, 12)
#define DMPLL_LDCR_LD_SAMP_SHIFT              16
#define DMPLL_LDCR_LD_SAMP_W(value)           WBGEN2_GEN_WRITE(value, 16, 12)
#define DMPLL_LDCR_LD_SAMP_R(reg)             WBGEN2_GEN_READ(reg, 16, 12)

/* definitions for register: DMPLL Status Register */

/* definitions for field: Frequency lock in reg: DMPLL Status Register */
#define DMPLL_PSR_FREQ_LK                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Phase lock in reg: DMPLL Status Register */
#define DMPLL_PSR_PHASE_LK                    WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Loss-of-lock indicator in reg: DMPLL Status Register */
#define DMPLL_PSR_LOCK_LOST                   WBGEN2_GEN_MASK(2, 1)

/* definitions for register: DMPLL Deglitcher Control Register for Reference input 0 clock */

/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_DGCR_IN0_THR_LO_MASK            WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN0_THR_LO_SHIFT           0
#define DMPLL_DGCR_IN0_THR_LO_W(value)        WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN0_THR_LO_R(reg)          WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_DGCR_IN0_THR_HI_MASK            WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN0_THR_HI_SHIFT           12
#define DMPLL_DGCR_IN0_THR_HI_W(value)        WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN0_THR_HI_R(reg)          WBGEN2_GEN_READ(reg, 12, 12)

/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_DGCR_IN0_THR_GLITCH_MASK        WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN0_THR_GLITCH_SHIFT       24
#define DMPLL_DGCR_IN0_THR_GLITCH_W(value)    WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN0_THR_GLITCH_R(reg)      WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: DMPLL Deglitcher Control Register for Reference input 1 clock */

/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_DGCR_IN1_THR_LO_MASK            WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN1_THR_LO_SHIFT           0
#define DMPLL_DGCR_IN1_THR_LO_W(value)        WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN1_THR_LO_R(reg)          WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_DGCR_IN1_THR_HI_MASK            WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN1_THR_HI_SHIFT           12
#define DMPLL_DGCR_IN1_THR_HI_W(value)        WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN1_THR_HI_R(reg)          WBGEN2_GEN_READ(reg, 12, 12)

/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_DGCR_IN1_THR_GLITCH_MASK        WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN1_THR_GLITCH_SHIFT       24
#define DMPLL_DGCR_IN1_THR_GLITCH_W(value)    WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN1_THR_GLITCH_R(reg)      WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: DMPLL Deglitcher Control Register for Reference input 2 clock */

/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_DGCR_IN2_THR_LO_MASK            WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN2_THR_LO_SHIFT           0
#define DMPLL_DGCR_IN2_THR_LO_W(value)        WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN2_THR_LO_R(reg)          WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_DGCR_IN2_THR_HI_MASK            WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN2_THR_HI_SHIFT           12
#define DMPLL_DGCR_IN2_THR_HI_W(value)        WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN2_THR_HI_R(reg)          WBGEN2_GEN_READ(reg, 12, 12)

/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_DGCR_IN2_THR_GLITCH_MASK        WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN2_THR_GLITCH_SHIFT       24
#define DMPLL_DGCR_IN2_THR_GLITCH_W(value)    WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN2_THR_GLITCH_R(reg)      WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: DMPLL Deglitcher Control Register for Reference input 3 clock */

/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_DGCR_IN3_THR_LO_MASK            WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_IN3_THR_LO_SHIFT           0
#define DMPLL_DGCR_IN3_THR_LO_W(value)        WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_IN3_THR_LO_R(reg)          WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_DGCR_IN3_THR_HI_MASK            WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_IN3_THR_HI_SHIFT           12
#define DMPLL_DGCR_IN3_THR_HI_W(value)        WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_IN3_THR_HI_R(reg)          WBGEN2_GEN_READ(reg, 12, 12)

/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_DGCR_IN3_THR_GLITCH_MASK        WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_IN3_THR_GLITCH_SHIFT       24
#define DMPLL_DGCR_IN3_THR_GLITCH_W(value)    WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_IN3_THR_GLITCH_R(reg)      WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: DMPLL Deglitcher Control Register for TCXO clock clock */

/* definitions for field: Low level stable threshold in reg: DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_DGCR_FB_THR_LO_MASK             WBGEN2_GEN_MASK(0, 12)
#define DMPLL_DGCR_FB_THR_LO_SHIFT            0
#define DMPLL_DGCR_FB_THR_LO_W(value)         WBGEN2_GEN_WRITE(value, 0, 12)
#define DMPLL_DGCR_FB_THR_LO_R(reg)           WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: High level stable threshold in reg: DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_DGCR_FB_THR_HI_MASK             WBGEN2_GEN_MASK(12, 12)
#define DMPLL_DGCR_FB_THR_HI_SHIFT            12
#define DMPLL_DGCR_FB_THR_HI_W(value)         WBGEN2_GEN_WRITE(value, 12, 12)
#define DMPLL_DGCR_FB_THR_HI_R(reg)           WBGEN2_GEN_READ(reg, 12, 12)

/* definitions for field: Glitch threshold in reg: DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_DGCR_FB_THR_GLITCH_MASK         WBGEN2_GEN_MASK(24, 8)
#define DMPLL_DGCR_FB_THR_GLITCH_SHIFT        24
#define DMPLL_DGCR_FB_THR_GLITCH_W(value)     WBGEN2_GEN_WRITE(value, 24, 8)
#define DMPLL_DGCR_FB_THR_GLITCH_R(reg)       WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 0 clock */

/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 0 clock */
#define DMPLL_PSCR_IN0_PS_VAL_MASK            WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN0_PS_VAL_SHIFT           0
#define DMPLL_PSCR_IN0_PS_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN0_PS_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 24)

/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 0 clock */
#define DMPLL_PSCR_IN0_BUSY                   WBGEN2_GEN_MASK(31, 1)

/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 1 clock */

/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 1 clock */
#define DMPLL_PSCR_IN1_PS_VAL_MASK            WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN1_PS_VAL_SHIFT           0
#define DMPLL_PSCR_IN1_PS_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN1_PS_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 24)

/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 1 clock */
#define DMPLL_PSCR_IN1_BUSY                   WBGEN2_GEN_MASK(31, 1)

/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 2 clock */

/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 2 clock */
#define DMPLL_PSCR_IN2_PS_VAL_MASK            WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN2_PS_VAL_SHIFT           0
#define DMPLL_PSCR_IN2_PS_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN2_PS_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 24)

/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 2 clock */
#define DMPLL_PSCR_IN2_BUSY                   WBGEN2_GEN_MASK(31, 1)

/* definitions for register: DMPLL Phase Shifter Control Register for Reference input 3 clock */

/* definitions for field: Current Phase Shift in reg: DMPLL Phase Shifter Control Register for Reference input 3 clock */
#define DMPLL_PSCR_IN3_PS_VAL_MASK            WBGEN2_GEN_MASK(0, 24)
#define DMPLL_PSCR_IN3_PS_VAL_SHIFT           0
#define DMPLL_PSCR_IN3_PS_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 24)
#define DMPLL_PSCR_IN3_PS_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 24)

/* definitions for field: Phase Shifter Busy in reg: DMPLL Phase Shifter Control Register for Reference input 3 clock */
#define DMPLL_PSCR_IN3_BUSY                   WBGEN2_GEN_MASK(31, 1)

/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 0 */

/* definitions for field: Freq/phase error in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 0 */
#define DMPLL_RFIFO_R0_ERR_VAL_MASK           WBGEN2_GEN_MASK(0, 18)
#define DMPLL_RFIFO_R0_ERR_VAL_SHIFT          0
#define DMPLL_RFIFO_R0_ERR_VAL_W(value)       WBGEN2_GEN_WRITE(value, 0, 18)
#define DMPLL_RFIFO_R0_ERR_VAL_R(reg)         WBGEN2_GEN_READ(reg, 0, 18)

/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 1 */

/* definitions for field: Ref tag in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 1 */
#define DMPLL_RFIFO_R1_TAG_REF_MASK           WBGEN2_GEN_MASK(0, 18)
#define DMPLL_RFIFO_R1_TAG_REF_SHIFT          0
#define DMPLL_RFIFO_R1_TAG_REF_W(value)       WBGEN2_GEN_WRITE(value, 0, 18)
#define DMPLL_RFIFO_R1_TAG_REF_R(reg)         WBGEN2_GEN_READ(reg, 0, 18)

/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */

/* definitions for field: Feedback tag in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
#define DMPLL_RFIFO_R2_TAG_FB_MASK            WBGEN2_GEN_MASK(0, 18)
#define DMPLL_RFIFO_R2_TAG_FB_SHIFT           0
#define DMPLL_RFIFO_R2_TAG_FB_W(value)        WBGEN2_GEN_WRITE(value, 0, 18)
#define DMPLL_RFIFO_R2_TAG_FB_R(reg)          WBGEN2_GEN_READ(reg, 0, 18)

/* definitions for field: Freq/phase mode in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
#define DMPLL_RFIFO_R2_FP_MODE                WBGEN2_GEN_MASK(29, 1)

/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' data output register 3 */

/* definitions for field: DAC output in reg: FIFO 'DMPLL Phase/Output record FIFO' data output register 3 */
#define DMPLL_RFIFO_R3_DAC_VAL_MASK           WBGEN2_GEN_MASK(0, 16)
#define DMPLL_RFIFO_R3_DAC_VAL_SHIFT          0
#define DMPLL_RFIFO_R3_DAC_VAL_W(value)       WBGEN2_GEN_WRITE(value, 0, 16)
#define DMPLL_RFIFO_R3_DAC_VAL_R(reg)         WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for register: FIFO 'DMPLL Phase/Output record FIFO' control/status register */

/* definitions for field: FIFO empty flag in reg: FIFO 'DMPLL Phase/Output record FIFO' control/status register */
#define DMPLL_RFIFO_CSR_EMPTY                 WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG DMPLL Control Register */
#define DMPLL_REG_PCR 0x00000000
/* [0x4]: REG DMPLL Frequency Branch Gain Register */
#define DMPLL_REG_FBGR 0x00000004
/* [0x8]: REG DMPLL Phase Branch Gain Register */
#define DMPLL_REG_PBGR 0x00000008
/* [0xc]: REG DMPLL Lock Detect Control Register */
#define DMPLL_REG_LDCR 0x0000000c
/* [0x10]: REG DMPLL Status Register */
#define DMPLL_REG_PSR 0x00000010
/* [0x14]: REG DMPLL Deglitcher Control Register for Reference input 0 clock */
#define DMPLL_REG_DGCR_IN0 0x00000014
/* [0x18]: REG DMPLL Deglitcher Control Register for Reference input 1 clock */
#define DMPLL_REG_DGCR_IN1 0x00000018
/* [0x1c]: REG DMPLL Deglitcher Control Register for Reference input 2 clock */
#define DMPLL_REG_DGCR_IN2 0x0000001c
/* [0x20]: REG DMPLL Deglitcher Control Register for Reference input 3 clock */
#define DMPLL_REG_DGCR_IN3 0x00000020
/* [0x24]: REG DMPLL Deglitcher Control Register for TCXO clock clock */
#define DMPLL_REG_DGCR_FB 0x00000024
/* [0x28]: REG DMPLL Phase Shifter Control Register for Reference input 0 clock */
#define DMPLL_REG_PSCR_IN0 0x00000028
/* [0x2c]: REG DMPLL Phase Shifter Control Register for Reference input 1 clock */
#define DMPLL_REG_PSCR_IN1 0x0000002c
/* [0x30]: REG DMPLL Phase Shifter Control Register for Reference input 2 clock */
#define DMPLL_REG_PSCR_IN2 0x00000030
/* [0x34]: REG DMPLL Phase Shifter Control Register for Reference input 3 clock */
#define DMPLL_REG_PSCR_IN3 0x00000034
/* [0x38]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 0 */
#define DMPLL_REG_RFIFO_R0 0x00000038
/* [0x3c]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 1 */
#define DMPLL_REG_RFIFO_R1 0x0000003c
/* [0x40]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 2 */
#define DMPLL_REG_RFIFO_R2 0x00000040
/* [0x44]: REG FIFO 'DMPLL Phase/Output record FIFO' data output register 3 */
#define DMPLL_REG_RFIFO_R3 0x00000044
/* [0x48]: REG FIFO 'DMPLL Phase/Output record FIFO' control/status register */
#define DMPLL_REG_RFIFO_CSR 0x00000048
#endif
