-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit Hardware Debugging Unit
-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--

peripheral {
 
  name = "WR Switch Hardware Info Unit";
  description = "The module provides basic info about the gateware version. It can be also used for reading registers inside WR Switch Gateware after connecting them to optional dbg input.";
  hdl_entity = "hwiu_wishbone_slave";
  prefix = "hwiu";


  reg {
    name = "Control Register";
    prefix = "CR";

    field {
        name = "Address of the register";
        description = "Which register (among those connected to HWDU) will be read";
        prefix = "ADR";
        size = 16;
        type = SLV;
        access_bus = READ_WRITE;
        access_dev = READ_ONLY;
    };

    field {
        name = "Read error";
        description = "read 1: read error, provided address is out of range \
                       read 0: read done successfully";
        prefix = "RD_ERR";
        type = BIT;
        align = 30;
        access_bus = READ_ONLY;
        access_dev = WRITE_ONLY;
    };

    field {
       name = "Read register value";
       description = "write 1: read the content \
                      write 0: no effect \
                      read  1: reading in progress \
                      read  0: reading done, register value available";
       prefix = "RD_EN";
       
       type = BIT;
       align = 31;
       access_dev = READ_WRITE;
       access_bus = READ_WRITE;
       load = LOAD_EXT;
    };
  };

  reg {
    name = "Value of the requested register";
    description = "The value of the register under ADR from the Control Register";
    prefix = "REG_VAL";

    field {
      name = "register value";
      size = 32;
      type = SLV;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

};
