Commit 06059cad authored by Nico Coesel's avatar Nico Coesel Committed by Grzegorz Daniluk

NC: Add patches for 1GB NAND flash on SCB3.4.1. These patches are (tested)…

NC: Add patches for 1GB NAND flash on SCB3.4.1. These patches are (tested) backwards compatible with the original SCB3.4.
parent 449c5c89
......@@ -4,6 +4,16 @@ Date: Mon, 28 Jul 2014 18:28:25 +0200
Subject: [PATCH 10/12] pm9g45/init (for wrs): more relaxed nand timings
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
OPNT NC 2-10-2018: Changed the timing parameters again. It seems a shorter ncs_xx_setup than the read or write
setup times means the read and write pulses get shorter! Solution: Keep all the setup times equal and
set the pulses to 3 cycles (=22.5ns).
Measurements show that in the original patch the read & write pulses where 15ns which is too short for
the 1GB replacement NAND flash. Besides that the pulses where shorter than expected (15ns instead of 30ns)
This patch has been engineered so it allows changing all parameters without creating a new patch.
---
arch/arm/boards/pm9g45/init.c | 22 +++++++++++-----------
1 files changed, 11 insertions(+), 11 deletions(-)
......@@ -12,7 +22,7 @@ diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index d4cea02..6d8f677 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -72,21 +72,21 @@ static struct atmel_nand_data nand_pdata = {
@@ -72,18 +72,18 @@
};
static struct sam9_smc_config pm_nand_smc_config = {
......@@ -20,31 +30,25 @@ index d4cea02..6d8f677 100644
- .nrd_setup = 1,
- .ncs_write_setup = 0,
- .nwe_setup = 1,
-
+ .ncs_read_setup = 2,
+ .nrd_setup = 2,
+ .ncs_write_setup = 2,
+ .nwe_setup = 2,
- .ncs_read_pulse = 2,
- .nrd_pulse = 3,
- .ncs_write_pulse = 3,
+ .ncs_read_setup = 2,
+ .nrd_setup = 4,
+ .ncs_write_setup = 2,
+ .nwe_setup = 4,
+
+ .ncs_read_pulse = 4,
+ .nrd_pulse = 4,
+ .ncs_write_pulse = 4,
.nwe_pulse = 4,
- .nwe_pulse = 4,
+ .ncs_read_pulse = 3,
+ .nrd_pulse = 3,
+ .ncs_write_pulse = 3,
+ .nwe_pulse = 3,
- .read_cycle = 4,
- .write_cycle = 7,
+ .read_cycle = 12,
+ .write_cycle = 12,
+ .read_cycle = 9,
+ .write_cycle = 9,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
- .tdf_cycles = 3,
+ .tdf_cycles = 4,
};
static void pm_add_device_nand(void)
--
1.7.7.2
.tdf_cycles = 3,
--- barebox-2014.04.0/drivers/mtd/devices/mtd_dataflash.c.orig 2018-06-28 14:39:56.000000000 +0200
+++ barebox-2014.04.0/drivers/mtd/devices/mtd_dataflash.c 2018-07-02 20:12:56.776148110 +0200
@@ -798,6 +798,27 @@
return ERR_PTR(-ENODEV);
}
+
+
+int adjust_page_size(struct spi_device *spi)
+{
+ int tmp;
+ uint8_t cmd_264b_per_page[]={0x3D, 0x2A, 0x80, 0xA7};
+
+ uint8_t dummy[5];
+
+ //Send command
+ tmp = spi_write_then_read(spi, cmd_264b_per_page, sizeof(cmd_264b_per_page), dummy, 0);
+ if (tmp < 0) {
+ pr_debug("%s: error %d setting 264b per pageD\n",
+ dev_name(&spi->dev), tmp);
+ return ERR_PTR(tmp);
+ }
+
+ return dataflash_waitready(spi);
+}
+
+
/*
* Detect and initialize DataFlash device, using JEDEC IDs on newer chips
* or else the ID code embedded in the status bits:
@@ -828,6 +849,17 @@
*/
info = jedec_probe(spi);
+
+ if ((info->flags & IS_POW2PS) !=0)
+ {
+ //NC: Hack to always have dataflash which is 264 pages for the SCB board
+ printk("Adjusting page size for %s\n", info->name);
+ adjust_page_size(spi);
+ }
+
+ //Re-probe to get the final device state
+ info = jedec_probe(spi);
+
pr_debug("MTD: %s 0x%08x %d %d %d %x\n",
info->name,info->jedec_id,
info->nr_pages,info->pagesize,info->pageoffset,info->flags);
--- barebox-2014.04.0/include/linux/mtd/nand.h.orig 2014-04-04 08:59:31.000000000 +0200
+++ barebox-2014.04.0/include/linux/mtd/nand.h 2018-07-10 21:06:26.555351999 +0200
@@ -462,6 +462,85 @@
* @write_page: [REPLACEABLE] High-level page write function
*/
+
+
+struct jedec_ecc_info {
+ u8 ecc_bits;
+ u8 codeword_size;
+ __le16 bb_per_lun;
+ __le16 block_endurance;
+ u8 reserved[2];
+} __packed;
+
+
+struct nand_jedec_params {
+ /* rev info and features block */
+ /* 'J' 'E' 'S' 'D' */
+ u8 sig[4];
+ __le16 revision;
+ __le16 features;
+ u8 opt_cmd[3];
+ __le16 sec_cmd;
+ u8 num_of_param_pages;
+ u8 reserved0[18];
+
+ /* manufacturer information block */
+ char manufacturer[12];
+ char model[20];
+ u8 jedec_id[6];
+ u8 reserved1[10];
+
+ /* memory organization block */
+ __le32 byte_per_page;
+ __le16 spare_bytes_per_page;
+ u8 reserved2[6];
+ __le32 pages_per_block;
+ __le32 blocks_per_lun;
+ u8 lun_count;
+ u8 addr_cycles;
+ u8 bits_per_cell;
+ u8 programs_per_page;
+ u8 multi_plane_addr;
+ u8 multi_plane_op_attr;
+ u8 reserved3[38];
+
+ /* electrical parameter block */
+ __le16 async_sdr_speed_grade;
+ __le16 toggle_ddr_speed_grade;
+ __le16 sync_ddr_speed_grade;
+ u8 async_sdr_features;
+ u8 toggle_ddr_features;
+ u8 sync_ddr_features;
+ __le16 t_prog;
+ __le16 t_bers;
+ __le16 t_r;
+ __le16 t_r_multi_plane;
+ __le16 t_ccs;
+ __le16 io_pin_capacitance_typ;
+ __le16 input_pin_capacitance_typ;
+ __le16 clk_pin_capacitance_typ;
+ u8 driver_strength_support;
+ __le16 t_ald;
+ u8 reserved4[36];
+
+ /* ECC and endurance block */
+ u8 guaranteed_good_blocks;
+ __le16 guaranteed_block_endurance;
+ struct jedec_ecc_info ecc_info[4];
+ u8 reserved5[29];
+
+ /* reserved */
+ u8 reserved6[148];
+
+ /* vendor */
+ __le16 vendor_rev_num;
+ u8 reserved7[88];
+
+ /* CRC for Parameter Page */
+ __le16 crc;
+} __packed;
+
+
struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
@@ -529,6 +608,13 @@
struct nand_bbt_descr *badblock_pattern;
+ int jedec_version;
+ uint8_t bits_per_cell;
+ uint16_t ecc_strength_ds;
+ uint16_t ecc_step_ds;
+
+ struct nand_jedec_params jedec_params;
+
void *priv;
};
@@ -550,6 +636,10 @@
/* The maximum expected count of bytes in the NAND ID sequence */
#define NAND_MAX_ID_LEN 8
+
+/* JEDEC features */
+#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
+
/*
* A helper for defining older NAND chips where the second ID byte fully
* defined the chip, including the geometry (chip size, eraseblock size, page
@@ -722,4 +812,10 @@
return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
}
+static inline int jedec_feature(struct nand_chip *chip)
+{
+ return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
+ : 0;
+}
+
#endif /* __LINUX_MTD_NAND_H */
......@@ -28,7 +28,9 @@ fi
# Not installing: assume we have ubi in place: attach and mount it now,
# either it is used for booting, or an interactive user can see it
addpart /dev/nand0 511M@1M(ubi-nand)
# OPNT NC: set partition size to 0 so addpart will use what is remaining. This
# is necessary to use different sizes of NAND flash (at the moment 512MB and 1024MB)
addpart /dev/nand0 0@1M(ubi-nand)
ubiattach /dev/nand0.ubi-nand
mkdir /boot
mount /dev/ubi0.boot /boot
......
......@@ -385,7 +385,7 @@ CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
# CONFIG_DRIVER_CFI is not set
CONFIG_NAND=y
CONFIG_NAND_ECC_SOFT=y
# CONFIG_NAND_ECC_BCH is not set
CONFIG_NAND_ECC_BCH=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_OOB_FIRST is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
......
......@@ -9,6 +9,16 @@ This patch has been ported from 2.6.39.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
OPNT NC 2-10-2018: Changed the timing parameters again. It seems a shorter ncs_xx_setup than the read or write
setup times means the read and write pulses get shorter! Solution: Keep all the setup times equal and
set the pulses to 3 cycles (=22.5ns).
Measurements show that in the original patch the read & write pulses where 15ns which is too short for
the 1GB replacement NAND flash. Besides that the pulses where shorter than expected (15ns instead of 30ns)
This patch has been engineered so it allows changing all parameters without creating a new patch.
---
arch/arm/mach-at91/board-sam9m10g45ek.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
......@@ -17,7 +27,7 @@ diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-
index ebd8ebd..5686a87 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -187,21 +187,21 @@ static struct atmel_nand_data __initdata ek_nand_data = {
@@ -187,21 +187,21 @@
};
static struct sam9_smc_config __initdata ek_nand_smc_config = {
......@@ -26,26 +36,28 @@ index ebd8ebd..5686a87 100644
- .ncs_write_setup = 0,
- .nwe_setup = 2,
+ .ncs_read_setup = 2,
+ .nrd_setup = 4,
+ .nrd_setup = 2,
+ .ncs_write_setup = 2,
+ .nwe_setup = 4,
+ .nwe_setup = 2,
.ncs_read_pulse = 4,
.nrd_pulse = 4,
.ncs_write_pulse = 4,
.nwe_pulse = 4,
- .ncs_read_pulse = 4,
- .nrd_pulse = 4,
- .ncs_write_pulse = 4,
- .nwe_pulse = 4,
+ .ncs_read_pulse = 3,
+ .nrd_pulse = 3,
+ .ncs_write_pulse = 3,
+ .nwe_pulse = 3,
- .read_cycle = 7,
- .write_cycle = 7,
+ .read_cycle = 12,
+ .write_cycle = 12,
+ .read_cycle = 9,
+ .write_cycle = 9,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
- .tdf_cycles = 3,
+ .tdf_cycles = 4,
+ .tdf_cycles = 3,
};
static void __init ek_add_device_nand(void)
--
2.7.4
--- a/drivers/mtd/nand/nand_base.c.orig 2018-06-28 14:31:09.000000000 +0200
+++ b/drivers/mtd/nand/nand_base.c 2018-06-28 14:34:18.801655500 +0200
@@ -3883,9 +3883,18 @@
ecc->layout = &nand_oob_128;
break;
default:
- pr_warn("No oob scheme defined for oobsize %d\n",
- mtd->oobsize);
- BUG();
+ pr_warn("No oob scheme defined for oobsize %d\n", mtd->oobsize);
+ if (mtd->oobsize>128)
+ {
+ //OPNT NC: Force OOB size to 128 because there is no layout for an OOB size of 224
+ mtd->oobsize=128;
+ pr_warn("Forcing oobsize to %d\n", mtd->oobsize);
+ ecc->layout = &nand_oob_128;
+ }
+ else
+ {
+ BUG();
+ }
}
}
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -861,12 +861,11 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
{
struct nand_chip *nand_chip = mtd->priv;
struct atmel_nand_host *host = nand_chip->priv;
- int i, err_nbr, eccbytes;
+ int i, err_nbr;
uint8_t *buf_pos;
int total_err = 0;
- eccbytes = nand_chip->ecc.bytes;
- for (i = 0; i < eccbytes; i++)
+ for (i = 0; i < nand_chip->ecc.total; i++)
if (ecc[i] != 0xff)
goto normal_check;
/* Erased page, return OK */
@@ -928,7 +927,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
{
struct atmel_nand_host *host = chip->priv;
- int eccsize = chip->ecc.size;
+ int eccsize = chip->ecc.size * chip->ecc.steps;
uint8_t *oob = chip->oob_poi;
uint32_t *eccpos = chip->ecc.layout->eccpos;
uint32_t stat;
@@ -1169,8 +1168,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
goto err;
}
- /* ECC is calculated for the whole page (1 step) */
- nand_chip->ecc.size = mtd->writesize;
+ nand_chip->ecc.size = sector_size;
/* set ECC page size and oob layout */
switch (mtd->writesize) {
@@ -1185,18 +1183,20 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
host->pmecc_index_of = host->pmecc_rom_base +
host->pmecc_lookup_table_offset;
- nand_chip->ecc.steps = 1;
+ nand_chip->ecc.steps = host->pmecc_sector_number;
nand_chip->ecc.strength = cap;
- nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
+ nand_chip->ecc.bytes = host->pmecc_bytes_per_sector;
+ nand_chip->ecc.total = host->pmecc_bytes_per_sector *
host->pmecc_sector_number;
- if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
+ if (nand_chip->ecc.total > mtd->oobsize - 2) {
dev_err(host->dev, "No room for ECC bytes\n");
err_no = -EINVAL;
goto err;
}
pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
mtd->oobsize,
- nand_chip->ecc.bytes);
+ nand_chip->ecc.total);
+
nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
break;
case 512:
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