Commit 0bdd6e2d authored by Adam Wujek's avatar Adam Wujek 💬

userspace/tools: remove wrs_port_tx_control

The tool wrs_port_tx_control is not needed anymore, its functionality (putting
the link down) is available by performing:
ifconfig <port> down
Such functionality was added in the commit:
[Feature: 1336] kernel/wr_nic: disable SFP when interface is down

Revert the following commits:
2b6c0bc2 userspace/tools: wrs_port_tx_control, rename network interfaces from wrX to wriX+1
ceb0c512 userspace/tools/wrs_port_tx_control: Include some defines
97d8878d userspace/tools/wrs_port_tx_control: initialise register address
35a63cd9 kernel/wb-regs: Added address offsets to endpoint-mdio.h
d11514e5 userspace/tools/wrs_port_tx_control: added unistd.h
3184c2a7 doc/wrs-user-manual: added description of wrs_port_tx_control
4da29df3 userspace/tools: dynamically check maximum port number in wr_port_tx_control
4244c894 userspace/tools: added a program to control the TX on a WRS port
Signed-off-by: Adam Wujek's avatarAdam Wujek <adam.wujek@cern.ch>
parent 6c9b1377
......@@ -1158,12 +1158,6 @@ The following tools and scripts are provided:
of the PPSi process, but PPSi switches the PPS output back on when a
link restart is detected and PPSi comes into @t{'TRACK_PHASE'} state.
@item wrs_port_tx_control
A tool to switch the TX (laser) of a port on and off by use of the @t{TX
disable} pin on the SFP. Usage ``@t{wrs_port_tx_control <port_no> on}''
switches the TX on, and ``@t{wrs_port_tx_control <port_no> off}''
switches the TX off. The port number @t{<port_no>} ranges from 1 to 18.
@item wr_date
The program can read or set the White Rabbit date. When setting,
......
......@@ -10,8 +10,8 @@
*/
#ifndef __WBGEN2_REGDEFS_ENDPOINT_MDIO_WB
#define __WBGEN2_REGDEFS_ENDPOINT_MDIO_WB
#ifndef __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#define __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#ifdef __KERNEL__
#include <linux/types.h>
......@@ -36,7 +36,6 @@
/* definitions for register: MDIO Control Register */
#define MDIO_MCR_ADDRESS 0x0
/* definitions for field: Reserved in reg: MDIO Control Register */
#define MDIO_MCR_RESV_MASK WBGEN2_GEN_MASK(0, 5)
......@@ -93,7 +92,6 @@
#define MDIO_MCR_RESET WBGEN2_GEN_MASK(15, 1)
/* definitions for register: MDIO Status Register */
#define MDIO_MSR_ADDRESS 0x4
/* definitions for field: Extended Capability in reg: MDIO Status Register */
#define MDIO_MSR_ERCAP_MASK WBGEN2_GEN_MASK(0, 1)
......@@ -183,7 +181,6 @@
#define MDIO_MSR_100BASE4_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: MDIO PHY Identification Register 1 */
#define MDIO_PHYSID_ADDRESS 0x8
/* definitions for field: Organizationally Unique Identifier (bits 7-21) in reg: MDIO PHY Identification Register 1 */
#define MDIO_PHYSID1_OUI_MASK WBGEN2_GEN_MASK(0, 16)
......@@ -192,7 +189,6 @@
#define MDIO_PHYSID1_OUI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_ADDRESS 0xc
/* definitions for field: Revision Number in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_REV_NUM_MASK WBGEN2_GEN_MASK(0, 4)
......@@ -213,7 +209,6 @@
#define MDIO_PHYSID2_OUI_R(reg) WBGEN2_GEN_READ(reg, 10, 6)
/* definitions for register: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_ADDRESS 0x10
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD3_MASK WBGEN2_GEN_MASK(0, 5)
......@@ -264,7 +259,6 @@
#define MDIO_ADVERTISE_NPAGE_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_ADDRESS 0x14
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RSVD3_MASK WBGEN2_GEN_MASK(0, 5)
......@@ -303,7 +297,6 @@
#define MDIO_LPA_NPAGE WBGEN2_GEN_MASK(15, 1)
/* definitions for register: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_ADDRESS 0x18
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_RSVD1_MASK WBGEN2_GEN_MASK(0, 1)
......@@ -330,7 +323,6 @@
#define MDIO_EXPANSION_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 3, 13)
/* definitions for register: MDIO Extended Status Register */
#define MDIO_ESTATUS_ADDRESS 0x3c
/* definitions for field: Reserved in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_RSVD1_MASK WBGEN2_GEN_MASK(0, 12)
......@@ -363,7 +355,6 @@
#define MDIO_ESTATUS_1000_XFULL_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_ADDRESS 0x40
/* definitions for field: TX Calibration Pattern in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_TX_CAL WBGEN2_GEN_MASK(0, 1)
......
......@@ -24,4 +24,3 @@ mkpasswd
wrs_status_led
wrs_sfp_dump
wrs_pps_control
wrs_port_tx_control
TOOLS = rtu_stat
TOOLS += wr_mon wr_phytool wrs_pps_control wrs_port_tx_control
TOOLS += spll_dbg_proxy load-lm32 load-virtex com
TOOLS = rtu_stat wr_mon wr_phytool wrs_pps_control spll_dbg_proxy load-lm32 load-virtex com
TOOLS += mapper wmapper
TOOLS += wrs_version wr_date lm32-vuart wrs_pstats
TOOLS += wrs_vlans wrs_dump_shmem
......
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <getopt.h>
#include <libwr/wrs-msg.h>
#include <regs/endpoint-regs.h>
/* #include <regs/endpoint-mdio.h> */
#include <fpga_io.h>
#include <libwr/switch_hw.h>
#include <libwr/shmem.h>
static struct EP_WB _ep_wb;
/* convert WR switch endpoint register name to an address value */
#define EP_REG(regname) ((uint32_t)((void *)&_ep_wb.regname - (void *)&_ep_wb))
/* convert port number (x) to an endpoint address, x is 1..18 on switch,
* ep is 0..17 */
#define IDX_TO_EP(x) (0x30000 + (((x) - 1) * 0x400))
/* FIXME: if include of endpoint-mdio.h is fixed this define can go:
* #ifndef __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB to
* #ifndef __WBGEN2_REGDEFS_ENDPOINT_MDIO_WB, otherwise the MDIO_WB is not
* used and it is not included.
*/
#define MDIO_MCR_PDOWN (1<<11)
/* PCS register address we want to read/write
* FIXME: these addresses could/should go into endpoint-mdio.h
*/
#define MDIO_MCR_ADDRESS 0x0
void help(char *prgname)
{
fprintf(stderr, "%s: Use: \"%s [<options>] <port_nr> <cmd>\n",
prgname, prgname);
fprintf(stderr,
" The program has the following options\n"
" -h print help\n"
"\n"
" Port numbers:\n"
" <port_nr> = 1 to 18 (on 18 port switch)\n"
"\n"
" Commands <cmd> are:\n"
" on - switch TX laser on.\n"
" off - switch TX laser off.\n");
exit(1);
}
/*
* Read a 1000base-X TBI PCS register on a WR switch endpoint
* port: endpoint number (1 to 18, will be translated to address offset)
* reg: WR endpoint 1000base-X TBI PCS register address to read from
*/
uint32_t pcs_read(int port, uint32_t reg)
{
/*
* write the PCS register address to read from to the MDIO control
* register on the WR switch endpoint.
*/
_fpga_writel(IDX_TO_EP(port) + EP_REG(MDIO_CR),
EP_MDIO_CR_ADDR_W(reg));
/*
* wait until the control register has processed the address and copied
* the data from the address into the control register
*/
while (!(_fpga_readl(IDX_TO_EP(port) + EP_REG(MDIO_ASR)) &
EP_MDIO_ASR_READY))
;
/* read data copied into the control register */
return EP_MDIO_CR_DATA_R(_fpga_readl(IDX_TO_EP(port) +
EP_REG(MDIO_ASR)));
}
/*
* Write a value to a 1000base-X TBI PCS register on a WR switch endpoint
* port: endpoint number (1 to 18, will be translated to address offset)
* reg: WR endpoint 1000base-X TBI PCS register address to write to
* value: PCS register value to write
*/
void pcs_write(int port, uint32_t reg, uint32_t val)
{
_fpga_writel(IDX_TO_EP(port) + EP_REG(MDIO_CR), EP_MDIO_CR_ADDR_W(reg)
| EP_MDIO_CR_DATA_W(val) | EP_MDIO_CR_RW);
while (!(_fpga_readl(IDX_TO_EP(port) + EP_REG(MDIO_ASR)) &
EP_MDIO_ASR_READY))
;
}
int get_nports_from_hal(void)
{
struct hal_shmem_header *h;
struct wrs_shm_head *hal_head = NULL;
int hal_nports_local; /* local copy of number of ports */
int ii;
int n_wait = 0;
int ret;
/* wait for HAL */
while ((ret = wrs_shm_get_and_check(wrs_shm_hal, &hal_head)) != 0) {
n_wait++;
if (n_wait > 10) {
if (ret == 1) {
fprintf(stderr, "rtu_stat: Unable to open "
"HAL's shm !\n");
}
if (ret == 2) {
fprintf(stderr, "rtu_stat: Unable to read "
"HAL's version!\n");
}
exit(1);
}
sleep(1);
}
h = (void *)hal_head + hal_head->data_off;
n_wait = 0;
while (1) { /* wait for 10 sec for HAL to produce consistent nports */
n_wait++;
ii = wrs_shm_seqbegin(hal_head);
/* Assume number of ports does not change in runtime */
hal_nports_local = h->nports;
if (!wrs_shm_seqretry(hal_head, ii))
break;
fprintf(stderr, "rtu_stat: Wait for HAL.\n");
if (n_wait > 10) {
exit(1);
}
sleep(1);
}
/* check hal's shm version */
if (hal_head->version != HAL_SHMEM_VERSION) {
fprintf(stderr, "rtu_stat: unknown HAL's shm version %i "
"(known is %i)\n",
hal_head->version, HAL_SHMEM_VERSION);
exit(-1);
}
if (hal_nports_local > HAL_MAX_PORTS) {
fprintf(stderr, "rtu_stat: Too many ports reported by HAL. "
"%d vs %d supported\n",
hal_nports_local, HAL_MAX_PORTS);
exit(-1);
}
return hal_nports_local;
}
int main(int argc, char *argv[])
{
int opt;
int port_number;
uint32_t reg = MDIO_MCR_ADDRESS;
uint32_t value;
while ((opt = getopt(argc, argv, "h")) != -1) {
switch (opt) {
case 'h':
default:
help(argv[0]);
}
}
assert_init(shw_fpga_mmap_init());
/* we need two arguments */
if (argc > 2) {
port_number = atoi(argv[1]);
if (port_number < 1 || port_number > get_nports_from_hal()) {
printf("Port number out of range\n");
exit(1);
}
if (strcmp(argv[2], "on") == 0) {
value = pcs_read(port_number, reg);
pcs_write(port_number, reg, value&~MDIO_MCR_PDOWN);
exit(0);
} else if (strcmp(argv[2], "off") == 0) {
value = pcs_read(port_number, reg);
pcs_write(port_number, reg, value|MDIO_MCR_PDOWN);
exit(0);
} else {
printf("Unknown command\n;");
exit(1);
}
} else {
printf("Need port and command\n");
exit(1);
}
}
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