Commit 0d6fee0a authored by Adam Wujek's avatar Adam Wujek 💬

userspace/rootfs_override: add script S70wrs_auxclk to configure external clock

Added init script /etc/init.d/S70wrs_auxclk to start wrs_auxclk with parameters
read from dot-config.

Added parameters to Kconfig:
--WRSAUXCLK_FREQ
--WRSAUXCLK_DUTY
--WRSAUXCLK_CSHIFT
--WRSAUXCLK_SIGDEL
--WRSAUXCLK_PPSHIFT
All above are used as parameters to wrs_auxclk,
which configure external clock clk2

NOTE: This patch requires new Gateware! wrs_auxclk will hang switch when using
gateware from last release of switch.
Signed-off-by: Adam Wujek's avatarAdam Wujek <adam.wujek@cern.ch>
parent 090e4eba
......@@ -408,5 +408,66 @@ config SNMP_SWCORESTATUS_RX_PRIO_FRAME_RATE
help
Error if frame rate of any RX priority exceed given value.
endmenu
menu "External clk2 clock signal configuration"
config WRSAUXCLK_FREQ
string "Frequency of the generated clock signal in MHz"
default "10"
help
--freq parameter of wrs_auxclk
Desired frequency of the generated clock signal in MHz. Available
range from 4kHz to 250MHz.
config WRSAUXCLK_DUTY
string "Duty cycle of the generated clock signal"
default "0.5"
help
--duty parameter of wrs_auxclk
Desired duty cycle given as a fraction (e.g. 0.5, 0.4).
config WRSAUXCLK_CSHIFT
string "Coarse shift of the generated clock signal"
default "36"
help
--cshift parameter of wrs_auxclk
Coarse shift (granularity 2ns) of the generated clock signal. This
parameter can be used to get desired delay relation between generated
1-PPS and clk2. The delay between 1-PPS and clk2 is constant for
a given bitstream but may be different for various hardware versions
and re-synthesized gateware. Therefore it should be measured and
adjusted only once for given hardware and gateware version.
config WRSAUXCLK_SIGDEL
string "Signal delay of the generated clock signal"
default "0"
help
--sigdel parameter of wrs_auxclk
Clock signal generated from the FPGA is cleaned by a discrete
flip-flop. It may happen that generated aux clock is in phase with
the flip-flop clock. In that case it is visible on the oscilloscope
that clk2 clock is jittering by 4ns. The "Signal delay" parameter
allows to add a precise delay to the FPGA-generated clock to avoid
such jitter. This delay is specified in steps, where each step is
around 150ps. This value, same as the "Coarse shift" parameter, is
constant for a given bitstream so should be verified only once.
config WRSAUXCLK_PPSHIFT
string "Fine signal delay of the generated clock signal"
default "0"
help
--ppshift parameter of wrs_auxclk
If one needs to precisely align 1-PPS output with the clk2 aux clock
using "Coarse shift" parameter is not enough as it has
4ns granularity. In that case this parameter lets you shift 1-PPS
output by a configured number of 150ps steps. However, please have in
mind that 1-PPS output is used as a reference for WR calibration
procedure. Therefore, once this parameter is modified, the device
should be re-calibrated. Otherwise, 1-PPS output will be shifted
from the WR timescale by <steps>*150ps.
endmenu
#!/bin/sh
# Script read wrs_auxclk parameters from dot-config, then start wrs_auxclk.
# First, read dot-config to get wrs_auxclk parameters
dotconfig=/wr/etc/dot-config
if [ -f $dotconfig ]; then
. $dotconfig
else
# exit
echo "dot-config not found! Don't setup wrs_auxclk"
exit 1
fi
if [ ! -z "$CONFIG_WRSAUXCLK_FREQ" ]; then
p_freq="--freq "$CONFIG_WRSAUXCLK_FREQ;
fi
if [ ! -z "$CONFIG_WRSAUXCLK_DUTY" ]; then
p_duty="--duty "$CONFIG_WRSAUXCLK_DUTY;
fi
if [ ! -z "$CONFIG_WRSAUXCLK_CSHIFT" ]; then
p_cshift="--cshift "$CONFIG_WRSAUXCLK_CSHIFT;
fi
if [ ! -z "$CONFIG_WRSAUXCLK_SIGDEL" ]; then
p_sigdel="--sigdel "$CONFIG_WRSAUXCLK_SIGDEL;
fi
if [ ! -z "$CONFIG_WRSAUXCLK_PPSHIFT" ]; then
p_ppshift="--ppshift "$CONFIG_WRSAUXCLK_PPSHIFT;
fi
# execute wrs_auxclk
echo "Configuring external clock clk2"
/wr/bin/wrs_auxclk $p_freq $p_duty $p_cshift $p_sigdel $p_ppshift > /dev/null 2>&1
if [ $? == 0 ]; then
echo "External clock clk2 OK"
else
echo "Failed to configure external clock clk2!!!"
fi
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