kernel:coht-vic: add VIC module from CERN BE-CO-HT

Copy the vic IRQ controller from the coht-vic repository. The maintainer prefers to have a copy instead of a submodule. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

kernel:coht-vic: add VIC module from CERN BE-CO-HT
Copy the vic IRQ controller from the coht-vic repository. The maintainer prefers to have a copy instead of a submodule. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
1d99d072 · Federico Vaga · Adam Wujek · a24f9143 · 1d99d072 · 1d99d072
Commit 1d99d072 authored Oct 20, 2016 by Federico Vaga Committed by Adam Wujek Dec 01, 2016
6 changed files
--- a/kernel/Makefile
+++ b/kernel/Makefile

-DIRS = wr_vic wr_nic wr_rtu wr_pstats wr_clocksource
+DIRS = coht_vic wr_nic wr_rtu wr_pstats wr_clocksource

 # We may "LINUX ?= /usr/src/linux-wrswitch", but it's better to leave it empty


--- a/kernel/coht_vic/Kbuild
+++ b/kernel/coht_vic/Kbuild
+ccflags-y += -Werror
+
+obj-m := htvic.o
--- a/kernel/coht_vic/Makefile
+++ b/kernel/coht_vic/Makefile
+
+export ARCH ?= arm
+export CROSS_COMPILE ?= $(CROSS_COMPILE_ARM)
+
+all: modules
+modules:
+	$(MAKE) -C $(LINUX) M=$(shell /bin/pwd)
+clean:
+	$(MAKE) -C $(LINUX) M=$(shell /bin/pwd) clean
+gtags:
+	gtags --statistics
+
+.PHONY: all clean gtags
--- a/kernel/coht_vic/htvic.c
+++ b/kernel/coht_vic/htvic.c
--- a/kernel/coht_vic/htvic.h
+++ b/kernel/coht_vic/htvic.h
+/*
+ * Copyright (c) 2016 CERN
+ * Author: Federico Vaga <federico.vaga@cern.ch>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __HTVIC_H__
+#define __HTVIC_H__
+
+#include "htvic_regs.h"
+
+#define VIC_MAX_VECTORS 32
+
+#define VIC_SDB_VENDOR 0xce42
+#define VIC_SDB_DEVICE 0x0013
+#define VIC_IRQ_BASE_NUMBER 0
+
+enum htvic_versions {
+	HTVIC_VER_SPEC = 0,
+	HTVIC_VER_SVEC,
+	HTVIC_VER_WRSWI,
+};
+
+enum htvic_mem_resources {
+	HTVIC_MEM_BASE = 0,
+};
+
+struct htvic_data {
+	uint32_t is_edge; /* 1 edge, 0 level */
+	uint32_t is_raising; /* 1 raising, 0 falling */
+	uint32_t pulse_len;
+};
+
+struct htvic_device {
+	struct platform_device *pdev;
+	struct irq_domain *domain;
+	unsigned int hwid[VIC_MAX_VECTORS]; /**> original ID from FPGA */
+	struct htvic_data *data;
+	void __iomem *kernel_va;
+
+	irq_flow_handler_t platform_handle_irq;
+	void *platform_handler_data;
+};
+
+
+struct memory_ops {
+	u32 (*read)(void *addr);
+	void (*write)(u32 value, void *addr);
+};
+
+extern struct memory_ops memop;
+
+static inline u32 htvic_ioread(struct htvic_device *htvic, void __iomem *addr)
+{
+	return memop.read(addr);
+}
+
+static inline void htvic_iowrite(struct htvic_device *htvic,
+				u32 value, void __iomem *addr)
+{
+	return memop.write(value, addr);
+}
+
+
+static inline u32 __htvic_ioread32(void *addr)
+{
+	return ioread32(addr);
+}
+
+static inline u32 __htvic_ioread32be(void *addr)
+{
+	return ioread32be(addr);
+}
+
+static inline void __htvic_iowrite32(u32 value,void __iomem *addr)
+{
+	iowrite32(value, addr);
+}
+
+static inline void  __htvic_iowrite32be(u32 value, void __iomem *addr)
+{
+	iowrite32be(value, addr);
+}
+
+#endif
--- a/kernel/coht_vic/htvic_regs.h
+++ b/kernel/coht_vic/htvic_regs.h
+/*
+  Register definitions for slave core: Vectored Interrupt Controller (VIC)
+
+  * File           : here.h
+  * Author         : auto-generated by wbgen2 from wb_slave_vic.wb
+  * Created        : Thu Jul 14 15:43:13 2016
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_vic.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WB_SLAVE_VIC_WB
+#define __WBGEN2_REGDEFS_WB_SLAVE_VIC_WB
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <inttypes.h>
+#endif
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: VIC Control Register */
+
+/* definitions for field: VIC Enable in reg: VIC Control Register */
+#define VIC_CTL_ENABLE                        WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: VIC output polarity in reg: VIC Control Register */
+#define VIC_CTL_POL                           WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Emulate Edge sensitive output in reg: VIC Control Register */
+#define VIC_CTL_EMU_EDGE                      WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Emulated Edge pulse timer in reg: VIC Control Register */
+#define VIC_CTL_EMU_LEN_MASK                  WBGEN2_GEN_MASK(3, 16)
+#define VIC_CTL_EMU_LEN_SHIFT                 3
+#define VIC_CTL_EMU_LEN_W(value)              WBGEN2_GEN_WRITE(value, 3, 16)
+#define VIC_CTL_EMU_LEN_R(reg)                WBGEN2_GEN_READ(reg, 3, 16)
+
+/* definitions for register: Raw Interrupt Status Register */
+
+/* definitions for register: Interrupt Enable Register */
+
+/* definitions for register: Interrupt Disable Register */
+
+/* definitions for register: Interrupt Mask Register */
+
+/* definitions for register: Vector Address Register */
+
+/* definitions for register: Software Interrupt Register */
+
+/* definitions for register: End Of Interrupt Acknowledge Register */
+/* definitions for RAM: Interrupt Vector Table */
+#define VIC_IVT_RAM_BASE 0x00000080 /* base address */                                
+#define VIC_IVT_RAM_BYTES 0x00000080 /* size in bytes */                               
+#define VIC_IVT_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */        
+/* [0x0]: REG VIC Control Register */
+#define VIC_REG_CTL 0x00000000
+/* [0x4]: REG Raw Interrupt Status Register */
+#define VIC_REG_RISR 0x00000004
+/* [0x8]: REG Interrupt Enable Register */
+#define VIC_REG_IER 0x00000008
+/* [0xc]: REG Interrupt Disable Register */
+#define VIC_REG_IDR 0x0000000c
+/* [0x10]: REG Interrupt Mask Register */
+#define VIC_REG_IMR 0x00000010
+/* [0x14]: REG Vector Address Register */
+#define VIC_REG_VAR 0x00000014
+/* [0x18]: REG Software Interrupt Register */
+#define VIC_REG_SWIR 0x00000018
+/* [0x1c]: REG End Of Interrupt Acknowledge Register */
+#define VIC_REG_EOIR 0x0000001c
+#endif