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White Rabbit Switch - Software
Commits
2e9542b1
Commit
2e9542b1
authored
Mar 09, 2012
by
Tomasz Wlostowski
Committed by
Alessandro Rubini
Mar 11, 2012
Browse files
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Plain Diff
userspace/wrsw_rtud: re-done register layout for N-port generic RTU
parent
00ce398d
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Side-by-side
Showing
8 changed files
with
316 additions
and
798 deletions
+316
-798
rtu.h
userspace/wrsw_rtud/rtu.h
+31
-34
rtu_drv.c
userspace/wrsw_rtud/rtu_drv.c
+158
-328
rtu_drv.h
userspace/wrsw_rtud/rtu_drv.h
+0
-5
rtu_fd.c
userspace/wrsw_rtud/rtu_fd.c
+70
-375
rtu_fd.h
userspace/wrsw_rtud/rtu_fd.h
+7
-7
rtu_hash.c
userspace/wrsw_rtud/rtu_hash.c
+16
-14
rtu_hash.h
userspace/wrsw_rtud/rtu_hash.h
+6
-6
rtud.c
userspace/wrsw_rtud/rtud.c
+28
-29
No files found.
userspace/wrsw_rtud/rtu.h
View file @
2e9542b1
...
...
@@ -39,16 +39,13 @@
#include "mac.h"
#define RTU_
BANKS 2
#define RTU_
ENTRIES 2048
#define RTU_BUCKETS 4
#define LAST_RTU_BUCKET ((RTU_BUCKETS)-1)
#define RTU_ENTRIES (16384/(RTU_BANKS))
#define HTAB_ENTRIES ((RTU_ENTRIES)/(RTU_BUCKETS))
#define LAST_HTAB_ENTRY ((HTAB_ENTRIES)-1)
#define LAST_RTU_BUCKET (RTU_BUCKETS-1)
#define ENTRY_WORDS 8
#define CAM_ENTRIES (((RTU_HCAM_WORDS)/(ENTRY_WORDS))/(RTU_BANKS))
#define LAST_CAM_ENTRY ((CAM_ENTRIES)-1)
#define MIN_PORT 0
#define MAX_PORT 9
...
...
userspace/wrsw_rtud/rtu_drv.c
View file @
2e9542b1
...
...
@@ -12,9 +12,7 @@
* to RTU_at_HW components including:
* - UFIFO
* - MFIFO
* - HCAM
* - Aging RAM for Main Hashtable
* - Aging Register for HCAM
* - VLAN Table
* - RTU Global Control Register
* - RTU Port settings
...
...
@@ -43,7 +41,7 @@
#include <sys/ioctl.h>
#include <hw/switch_hw.h>
#include <hw/
wrsw_rtu_wb
.h>
#include <hw/
rtu_regs
.h>
#include <hal_client.h>
#include "rtu_drv.h"
...
...
@@ -68,7 +66,6 @@ static void mac_entry_word3_r(uint32_t word, struct filtering_entry *ent);
static
void
mac_entry_word4_r
(
uint32_t
word
,
struct
filtering_entry
*
ent
);
static
uint32_t
vlan_entry_word0_w
(
struct
vlan_table_entry
*
ent
);
static
uint32_t
fpga_rtu_pcr_addr
(
int
port
);
/*
* Used to communicate to RTU UFIFO IRQ handler device at kernel space
...
...
@@ -85,14 +82,16 @@ int rtu_init(void)
if
(
halexp_client_init
()
<
0
)
TRACE
(
TRACE_FATAL
,
"
WRSW_
HAL is not responding... Are you sure it's running on your switch?
\n
"
"
The
HAL is not responding... Are you sure it's running on your switch?
\n
"
);
// Used to 'get' RTU IRQs from kernel
fd
=
open
(
RTU_DEVNAME
,
O_RDWR
);
if
(
fd
<
0
)
{
TRACE
(
TRACE_ERROR
,
"Can't open %s: is the RTU kernel driver loaded?"
,
RTU_DEVNAME
);
return
errno
;
}
// init IO memory map
err
=
shw_fpga_mmap_init
();
if
(
err
)
...
...
@@ -112,6 +111,28 @@ void rtu_exit(void)
}
static
inline
uint32_t
rtu_rd
(
uint32_t
reg
)
{
return
_fpga_readl
(
FPGA_BASE_RTU
+
reg
);
}
static
inline
void
rtu_wr
(
uint32_t
reg
,
uint32_t
value
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
reg
,
value
);
}
static
inline
void
write_pcr
(
int
port
,
uint32_t
pcr
)
{
rtu_wr
(
RTU_REG_PSR
,
RTU_PSR_PORT_SEL_W
(
port
));
rtu_wr
(
RTU_REG_PCR
,
pcr
);
}
static
inline
uint32_t
read_pcr
(
int
port
)
{
rtu_wr
(
RTU_REG_PSR
,
RTU_PSR_PORT_SEL_W
(
port
));
return
rtu_rd
(
RTU_REG_PCR
);
}
// UFIFO
/**
...
...
@@ -120,7 +141,7 @@ void rtu_exit(void)
*/
int
rtu_ufifo_is_empty
(
void
)
{
uint32_t
csr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_CSR
);
uint32_t
csr
=
rtu_rd
(
RTU_REG_UFIFO_CSR
);
return
RTU_UFIFO_CSR_EMPTY
&
csr
;
}
...
...
@@ -132,7 +153,7 @@ int rtu_read_learning_queue_cnt(void)
{
// Get counter from UFIFO Control-Status Register
// Fixme: USEDW returns 0 (FIFO overflow?)
uint32_t
csr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_CSR
);
uint32_t
csr
=
rtu_rd
(
RTU_REG_UFIFO_CSR
);
return
RTU_UFIFO_CSR_USEDW_R
(
csr
);
}
...
...
@@ -142,10 +163,19 @@ int rtu_read_learning_queue_cnt(void)
* @param req pointer to unrecognised request data. Memory handled by callee.
* @return error code
*/
static
int
irq_disabled
=
1
;
int
rtu_read_learning_queue
(
struct
rtu_request
*
req
)
{
int
err
;
if
(
irq_disabled
)
{
ioctl
(
fd
,
WR_RTU_IRQENA
);
irq_disabled
=
0
;
}
// If learning queue is empty, wait for UFIFO IRQ
if
(
rtu_ufifo_is_empty
())
{
err
=
ioctl
(
fd
,
WR_RTU_IRQWAIT
);
...
...
@@ -154,15 +184,13 @@ int rtu_read_learning_queue(struct rtu_request *req)
}
// read data from mapped IO memory
uint32_t
r0
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_R0
);
uint32_t
r1
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_R1
);
uint32_t
r2
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_R2
);
uint32_t
r3
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_R3
);
uint32_t
r4
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_UFIFO_R4
);
uint32_t
r0
=
rtu_rd
(
RTU_REG_UFIFO_R0
);
uint32_t
r1
=
rtu_rd
(
RTU_REG_UFIFO_R1
);
uint32_t
r2
=
rtu_rd
(
RTU_REG_UFIFO_R2
);
uint32_t
r3
=
rtu_rd
(
RTU_REG_UFIFO_R3
);
uint32_t
r4
=
rtu_rd
(
RTU_REG_UFIFO_R4
);
// Once read: if learning queue becomes empty again, enable UFIFO IRQ
if
(
rtu_ufifo_is_empty
())
ioctl
(
fd
,
WR_RTU_IRQENA
);
// unmarshall data and populate request
uint32_t
dmac_lo
=
RTU_UFIFO_R0_DMAC_LO_R
(
r0
);
...
...
@@ -189,6 +217,9 @@ int rtu_read_learning_queue(struct rtu_request *req)
req
->
src
[
2
]
=
0xFF
&
(
smac_lo
>>
24
);
req
->
src
[
1
]
=
0xFF
&
smac_hi
;
req
->
src
[
0
]
=
0xFF
&
(
smac_hi
>>
8
);
ioctl
(
fd
,
WR_RTU_IRQENA
);
return
0
;
}
...
...
@@ -202,7 +233,7 @@ int rtu_read_learning_queue(struct rtu_request *req)
int
rtu_read_mfifo_cnt
(
void
)
{
// Get counter from MFIFO Control-Status Register
uint32_t
csr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_CSR
);
uint32_t
csr
=
rtu_rd
(
RTU_REG_MFIFO_CSR
);
return
RTU_MFIFO_CSR_USEDW_R
(
csr
);
}
...
...
@@ -212,7 +243,7 @@ int rtu_read_mfifo_cnt(void)
*/
int
rtu_mfifo_is_full
(
void
)
{
uint32_t
csr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_CSR
);
uint32_t
csr
=
rtu_rd
(
RTU_REG_MFIFO_CSR
);
return
RTU_MFIFO_CSR_FULL
&
csr
;
}
...
...
@@ -222,20 +253,16 @@ int rtu_mfifo_is_full(void)
*/
int
rtu_mfifo_is_empty
(
void
)
{
uint32_t
csr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_CSR
);
uint32_t
csr
=
rtu_rd
(
RTU_REG_MFIFO_CSR
);
return
RTU_MFIFO_CSR_EMPTY
&
csr
;
}
/**
* \brief Cleans MFIFO
*/
void
rtu_clean_mfifo
(
void
)
static
inline
void
flush_mfifo
()
{
while
(
!
rtu_mfifo_is_empty
())
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_R0
,
RTU_MFIFO_R0_AD_SEL
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_R1
,
0
);
usleep
(
10
);
}
uint32_t
gcr
=
rtu_rd
(
RTU_REG_GCR
);
rtu_wr
(
RTU_REG_GCR
,
gcr
|
RTU_GCR_MFIFOTRIG
);
while
(
!
rtu_rd
(
RTU_REG_GCR
)
&
RTU_GCR_MFIFOTRIG
);
/* wait while the RTU is busy flushing the MFIFO */
}
/**
...
...
@@ -251,10 +278,11 @@ void rtu_write_htab_entry(uint16_t zbt_addr, struct filtering_entry *ent)
write_mfifo_data
(
mac_entry_word2_w
(
ent
));
write_mfifo_data
(
mac_entry_word3_w
(
ent
));
write_mfifo_data
(
mac_entry_word4_w
(
ent
));
flush_mfifo
();
TRACE_DBG
(
TRACE_INFO
,
"write htab entry: addr %x ent %08x %08x %08x %08x %08x"
,
"write htab entry
[with flush]
: addr %x ent %08x %08x %08x %08x %08x"
,
zbt_addr
,
mac_entry_word0_w
(
ent
),
mac_entry_word1_w
(
ent
),
...
...
@@ -288,95 +316,11 @@ void rtu_clean_htab(void)
write_mfifo_data
(
0x00000000
);
write_mfifo_data
(
0x00000000
);
write_mfifo_data
(
0x00000000
);
flush_mfifo
();
}
}
// HCAM
/**
* \brief Reads MAC entry from HCAM Hash collisions memory
* @param ent used to store the entry read. Memory should be handled by callee.
* @param cam_addr memory address which shoud be read.
*/
void
rtu_read_hcam_entry
(
uint16_t
cam_addr
,
struct
filtering_entry
*
ent
)
{
// read data from mapped IO memory
uint32_t
w0
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
cam_addr
);
uint32_t
w1
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x1
));
uint32_t
w2
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x2
));
uint32_t
w3
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x3
));
uint32_t
w4
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x4
));
TRACE_DBG
(
TRACE_INFO
,
"read hcam entry: addr %x ent %08x %08x %08x %08x %08x"
,
cam_addr
,
w0
,
w1
,
w2
,
w3
,
w4
);
// unmarshall data and populate entry
mac_entry_word0_r
(
w0
,
ent
);
mac_entry_word1_r
(
w1
,
ent
);
mac_entry_word2_r
(
w2
,
ent
);
mac_entry_word3_r
(
w3
,
ent
);
mac_entry_word4_r
(
w4
,
ent
);
}
/**
* \brief Writes MAC entry to HCAM Hash collisions memory
* @param ent MAC table entry to be written to HCAM.
* @param cam_addr memory address in which MAC entry shoud be added.
*/
void
rtu_write_hcam_entry
(
uint16_t
cam_addr
,
struct
filtering_entry
*
ent
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
cam_addr
,
mac_entry_word0_w
(
ent
));
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x1
),
mac_entry_word1_w
(
ent
));
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x2
),
mac_entry_word2_w
(
ent
));
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x3
),
mac_entry_word3_w
(
ent
));
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x4
),
mac_entry_word4_w
(
ent
));
TRACE_DBG
(
TRACE_INFO
,
"write hcam entry: addr %x ent %08x %08x %08x %08x %08x"
,
cam_addr
,
mac_entry_word0_w
(
ent
),
mac_entry_word1_w
(
ent
),
mac_entry_word2_w
(
ent
),
mac_entry_word3_w
(
ent
),
mac_entry_word4_w
(
ent
)
);
}
/**
* \brief Cleans MAC entry in HCAM Hash collisions memory
* @param addr memory address which shoud be cleaned.
*/
void
rtu_clean_hcam_entry
(
uint8_t
cam_addr
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
cam_addr
,
0x00000000
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x1
),
0x00000000
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x2
),
0x00000000
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x3
),
0x00000000
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
(
cam_addr
+
0x4
),
0x00000000
);
TRACE_DBG
(
TRACE_INFO
,
"write hcam entry: addr %x ent 00000000 00000000 00000000 00000000 00000000"
,
cam_addr
);
}
/**
* \brief Cleans HCAM.
* Cleans all entries in HCAM inactive bank.
*/
void
rtu_clean_hcam
(
void
)
{
int
addr
;
for
(
addr
=
0
;
addr
<
(
RTU_HCAM_WORDS
/
RTU_BANKS
);
addr
++
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_HCAM
+
4
*
addr
,
0x00000000
);
}
}
// AGING RAM - HTAB
/**
...
...
@@ -385,7 +329,7 @@ void rtu_clean_hcam(void)
*/
uint32_t
rtu_read_agr_htab
(
uint32_t
addr
)
{
return
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_ARAM_MAIN
+
4
*
addr
)
;
return
rtu_rd
(
RTU_ARAM_BASE
+
4
*
addr
)
;
}
/**
...
...
@@ -394,32 +338,11 @@ uint32_t rtu_read_agr_htab( uint32_t addr )
void
rtu_clean_agr_htab
(
void
)
{
int
addr
;
for
(
addr
=
0
;
addr
<
RTU_ARAM_
MAIN_
WORDS
;
addr
++
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_ARAM_MAIN
+
4
*
addr
,
0x00000000
);
for
(
addr
=
0
;
addr
<
RTU_ARAM_WORDS
;
addr
++
)
{
rtu_wr
(
RTU_ARAM_BASE
+
4
*
addr
,
0x00000000
);
}
}
// AGING RAM - HCAM
/**
* \brief Read aging register for HCAM.
* Each bit corresponds to one MAC entry in HCAM memory.
*/
uint32_t
rtu_read_agr_hcam
(
void
)
{
return
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_AGR_HCAM
);
}
/**
* \brief Clears aging register for HCAM
*/
void
rtu_clean_agr_hcam
(
void
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_AGR_HCAM
,
0x00000000
);
}
// VLAN TABLE
/**
...
...
@@ -431,7 +354,7 @@ void rtu_write_vlan_entry(uint32_t addr, struct vlan_table_entry *ent)
{
// printf("write_VLAN_ent: addr %x val %x\n", + RTU_VLAN_TAB + 4*addr, vlan_entry_word0_w(ent));
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_VLAN_TAB
+
4
*
addr
,
vlan_entry_word0_w
(
ent
));
rtu_wr
(
RTU_VLAN_TAB_BASE
+
4
*
addr
,
vlan_entry_word0_w
(
ent
));
TRACE_DBG
(
TRACE_INFO
,
"write vlan entry: addr %x ent %08x %08x %08x %08x %08x"
,
...
...
@@ -447,7 +370,7 @@ void rtu_write_vlan_entry(uint32_t addr, struct vlan_table_entry *ent)
void
rtu_clean_vlan_entry
(
uint32_t
addr
)
{
// Value 0x80000000 sets drop field to 1 (VLAN entry not registered)
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_VLAN_TAB
+
4
*
addr
,
0x80000000
);
rtu_wr
(
RTU_VLAN_TAB_BASE
+
4
*
addr
,
0x80000000
);
}
/**
...
...
@@ -457,7 +380,7 @@ void rtu_clean_vlan(void)
{
int
addr
;
for
(
addr
=
0
;
addr
<
NUM_VLANS
;
addr
++
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_VLAN_TAB
+
4
*
addr
,
0x80000000
);
rtu_wr
(
RTU_VLAN_TAB_BASE
+
4
*
addr
,
0x80000000
);
}
}
...
...
@@ -469,12 +392,8 @@ void rtu_clean_vlan(void)
*/
void
rtu_enable
(
void
)
{
// Get current GCR
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
// Set G_ENA bit value = 1
gcr
=
gcr
|
RTU_GCR_G_ENA
;
// Update GCR
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_GCR
,
gcr
);
uint32_t
gcr
=
rtu_rd
(
RTU_REG_GCR
);
rtu_wr
(
RTU_REG_GCR
,
gcr
|
RTU_GCR_G_ENA
);
TRACE_DBG
(
TRACE_INFO
,
"updated gcr (enable): %x
\n
"
,
gcr
);
}
...
...
@@ -483,12 +402,8 @@ void rtu_enable(void)
*/
void
rtu_disable
(
void
)
{
// Get current GCR
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
// Set G_ENA bit value = 0
gcr
=
gcr
&
(
~
RTU_GCR_G_ENA
);
// Update GCR
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_GCR
,
gcr
);
uint32_t
gcr
=
rtu_rd
(
RTU_REG_GCR
);
rtu_wr
(
RTU_REG_GCR
,
gcr
&
(
~
RTU_GCR_G_ENA
));
TRACE_DBG
(
TRACE_INFO
,
"updated gcr (disable): %x
\n
"
,
gcr
);
}
...
...
@@ -498,8 +413,7 @@ void rtu_disable(void)
*/
uint16_t
rtu_read_hash_poly
(
void
)
{
// Get current GCR
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
uint32_t
gcr
=
rtu_rd
(
RTU_REG_GCR
);
return
RTU_GCR_POLY_VAL_R
(
gcr
);
}
...
...
@@ -510,56 +424,14 @@ uint16_t rtu_read_hash_poly(void)
void
rtu_write_hash_poly
(
uint16_t
hash_poly
)
{
// Get current GCR
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
uint32_t
gcr
=
rtu_rd
(
RTU_REG_GCR
);
// Clear previous hash poly and insert the new one
gcr
=
(
gcr
&
(
~
RTU_GCR_POLY_VAL_MASK
))
|
RTU_GCR_POLY_VAL_W
(
hash_poly
);
// Update GCR
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_GCR
,
gcr
);
rtu_wr
(
RTU_REG_GCR
,
gcr
);
TRACE_DBG
(
TRACE_INFO
,
"updated gcr (poly): %x
\n
"
,
gcr
);
}
/**
* \brief Set active ZBT bank.
* @param bank active ZBT bank (0 or 1). Other values will be evaluated as 1.
*/
void
rtu_set_active_htab_bank
(
uint8_t
bank
)
{
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
gcr
=
bank
?
(
RTU_GCR_HT_BSEL
|
gcr
)
:
((
~
RTU_GCR_HT_BSEL
)
&
gcr
)
;
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_GCR
,
gcr
);
TRACE_DBG
(
TRACE_INFO
,
"updated gcr (htab bank): %x
\n
"
,
gcr
);
}
/**
* \brief Set active CAM bank.
* @param bank active CAM bank (0 or 1). Other values will be evaluated as 1.
*/
void
rtu_set_active_hcam_bank
(
uint8_t
bank
)
{
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
gcr
=
bank
?
(
RTU_GCR_HCAM_BSEL
|
gcr
)
:
((
~
RTU_GCR_HCAM_BSEL
)
&
gcr
)
;
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_GCR
,
gcr
);
TRACE_DBG
(
TRACE_INFO
,
"updated gcr (hcam bank): %x
\n
"
,
gcr
);
}
/**
* \brief Set active ZBT and CAM banks at once.
* @param bank active ZBT and CAM bank (0 or 1). Other values will be evaluated as 1.
*/
void
rtu_set_active_bank
(
uint8_t
bank
)
{
uint32_t
gcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
RTU_REG_GCR
);
gcr
=
bank
?
(
RTU_GCR_HT_BSEL
|
RTU_GCR_HCAM_BSEL
|
gcr
)
:
((
~
RTU_GCR_HT_BSEL
)
&
(
~
RTU_GCR_HCAM_BSEL
)
&
gcr
)
;
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_GCR
,
gcr
);
TRACE_DBG
(
TRACE_INFO
,
"updated gcr (htab/hcam bank): %x
\n
"
,
gcr
);
}
// PORT SETTINGS
...
...
@@ -574,11 +446,9 @@ int rtu_set_fixed_prio_on_port(int port, uint8_t prio)
{
if
(
(
port
<
MIN_PORT
)
||
(
port
>
MAX_PORT
)
)
return
-
EINVAL
;
uint32_t
pcr_addr
=
fpga_rtu_pcr_addr
(
port
);
uint32_t
pcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
pcr_addr
);
// Be careful! the following assumes every port control reg has same layout
pcr
=
pcr
|
RTU_PCR0_FIX_PRIO
|
RTU_PCR0_PRIO_VAL_W
(
prio
);
_fpga_writel
(
FPGA_BASE_RTU
+
pcr_addr
,
pcr
);
uint32_t
pcr
=
read_pcr
(
port
);
write_pcr
(
port
,
pcr
|
RTU_PCR_FIX_PRIO
|
RTU_PCR_PRIO_VAL_W
(
prio
));
return
0
;
}
...
...
@@ -592,11 +462,10 @@ int rtu_unset_fixed_prio_on_port(int port)
{
if
(
(
port
<
MIN_PORT
)
||
(
port
>
MAX_PORT
)
)
return
-
EINVAL
;
uint32_t
pcr_addr
=
fpga_rtu_pcr_addr
(
port
);
uint32_t
pcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
pcr_addr
);
// Be careful! the following assumes every port control reg has same layout
pcr
=
pcr
&
(
RTU_PCR0_LEARN_EN
|
RTU_PCR0_PASS_ALL
|
RTU_PCR0_PASS_BPDU
|
RTU_PCR0_B_UNREC
);
_fpga_writel
(
FPGA_BASE_RTU
+
pcr_addr
,
pcr
);
uint32_t
pcr
=
read_pcr
(
port
);
write_pcr
(
port
,
pcr
&
(
RTU_PCR_LEARN_EN
|
RTU_PCR_PASS_ALL
|
RTU_PCR_PASS_BPDU
|
RTU_PCR_B_UNREC
));
return
0
;
}
...
...
@@ -610,13 +479,13 @@ int rtu_learn_enable_on_port(int port, int flag)
{
if
(
(
port
<
MIN_PORT
)
||
(
port
>
MAX_PORT
)
)
return
-
EINVAL
;
uint32_t
pcr_addr
=
fpga_rtu_pcr_addr
(
port
);
uint32_t
pcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
pcr_addr
);
// Be careful! the following assumes every port control reg has same layout
uint32_t
pcr
=
read_pcr
(
port
);
pcr
=
flag
?
RTU_PCR0_LEARN_EN
|
pcr
:
(
~
RTU_PCR0_LEARN_EN
)
&
pcr
;
_fpga_writel
(
FPGA_BASE_RTU
+
pcr_addr
,
pcr
);
RTU_PCR_LEARN_EN
|
pcr
:
(
~
RTU_PCR_LEARN_EN
)
&
pcr
;
write_pcr
(
port
,
pcr
);
return
0
;
}
...
...
@@ -631,13 +500,12 @@ int rtu_pass_bpdu_on_port(int port, int flag)
{
if
(
(
port
<
MIN_PORT
)
||
(
port
>
MAX_PORT
)
)
return
-
EINVAL
;
uint32_t
pcr_addr
=
fpga_rtu_pcr_addr
(
port
);
uint32_t
pcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
pcr_addr
);
// Be careful! the following assumes every port control reg has same layout
uint32_t
pcr
=
read_pcr
(
port
);
pcr
=
flag
?
RTU_PCR0
_PASS_BPDU
|
pcr
:
(
~
RTU_PCR0
_PASS_BPDU
)
&
pcr
;
_fpga_writel
(
FPGA_BASE_RTU
+
pcr_addr
,
pcr
);
RTU_PCR
_PASS_BPDU
|
pcr
:
(
~
RTU_PCR
_PASS_BPDU
)
&
pcr
;
write_pcr
(
port
,
pcr
);
return
0
;
}
...
...
@@ -651,13 +519,13 @@ int rtu_pass_all_on_port(int port, int flag)
{
if
(
(
port
<
MIN_PORT
)
||
(
port
>
MAX_PORT
)
)
return
-
EINVAL
;
uint32_t
pcr_addr
=
fpga_rtu_pcr_addr
(
port
);
uint32_t
pcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
pcr_addr
);
// Be careful! the following assumes every port control reg has same layout
uint32_t
pcr
=
read_pcr
(
port
);
pcr
=
flag
?
RTU_PCR0
_PASS_ALL
|
pcr
:
(
~
RTU_PCR0
_PASS_ALL
)
&
pcr
;
_fpga_writel
(
FPGA_BASE_RTU
+
pcr_addr
,
pcr
);
RTU_PCR
_PASS_ALL
|
pcr
:
(
~
RTU_PCR
_PASS_ALL
)
&
pcr
;
write_pcr
(
port
,
pcr
);
return
0
;
}
...
...
@@ -671,32 +539,17 @@ int rtu_set_unrecognised_behaviour_on_port(int port, int flag)
{
if
(
(
port
<
MIN_PORT
)
||
(
port
>
MAX_PORT
)
)
return
-
EINVAL
;
uint32_t
pcr_addr
=
fpga_rtu_pcr_addr
(
port
);
uint32_t
pcr
=
_fpga_readl
(
FPGA_BASE_RTU
+
pcr_addr
);
// Be careful! the following assumes every port control reg has same layout
pcr
=
flag
?
RTU_PCR0_B_UNREC
|
pcr
:
(
~
RTU_PCR0_B_UNREC
)
&
pcr
;
_fpga_writel
(
FPGA_BASE_RTU
+
pcr_addr
,
pcr
);
return
0
;
}
// IRQs
uint32_t
pcr
=
read_pcr
(
port
);
void
rtu_enable_irq
(
void
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_EIC_IER
,
RTU_EIC_IER_NEMPTY
);
}
pcr
=
flag
?
RTU_PCR_B_UNREC
|
pcr
:
(
~
RTU_PCR_B_UNREC
)
&
pcr
;
void
rtu_disable_irq
(
void
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_EIC_IDR
,
RTU_EIC_IDR_NEMPTY
);
write_pcr
(
port
,
pcr
);
return
0
;
}
void
rtu_clear_irq
(
void
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_EIC_ISR
,
RTU_EIC_ISR_NEMPTY
);
}
//---------------------------------------------
// Private Methods
...
...
@@ -706,19 +559,14 @@ void rtu_clear_irq(void)
static
void
write_mfifo_addr
(
uint32_t
zbt_addr
)
{
// workaround required to solve MFIFO overflow
rtu_clean_mfifo
();
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_R0
,
RTU_MFIFO_R0_AD_SEL
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_R1
,
zbt_addr
);
rtu_wr
(
RTU_REG_MFIFO_R0
,
RTU_MFIFO_R0_AD_SEL
);
rtu_wr
(
RTU_REG_MFIFO_R1
,
zbt_addr
);
}
static
void
write_mfifo_data
(
uint32_t
word
)
{
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_R0
,
RTU_MFIFO_R0_DATA_SEL
);
_fpga_writel
(
FPGA_BASE_RTU
+
RTU_REG_MFIFO_R1
,
word
);
// workaround required to solve MFIFO overflow
while
(
rtu_mfifo_is_full
());
rtu_wr
(
RTU_REG_MFIFO_R0
,
RTU_MFIFO_R0_DATA_SEL
);
rtu_wr
(
RTU_REG_MFIFO_R1
,
word
);
}
// to marshall MAC entries
...
...
@@ -833,21 +681,3 @@ static uint32_t vlan_entry_word0_w(struct vlan_table_entry *ent)
((
0xFFFF
&
ent
->
port_mask
)
)
;
}
static
uint32_t
fpga_rtu_pcr_addr
(
int
port
)
{
switch
(
port
){
case
0
:
return
RTU_REG_PCR0
;
case
1
:
return
RTU_REG_PCR1
;
case
2
:
return
RTU_REG_PCR2
;
case
3
:
return
RTU_REG_PCR3
;
case
4
:
return
RTU_REG_PCR4
;
case
5
:
return
RTU_REG_PCR5
;
case
6
:
return
RTU_REG_PCR6
;
case
7
:
return
RTU_REG_PCR7
;
case
8
:
return
RTU_REG_PCR8
;
case
9
:
return
RTU_REG_PCR9
;
default:
return
-
EINVAL
;
}
}
userspace/wrsw_rtud/rtu_drv.h
View file @
2e9542b1
...
...
@@ -33,11 +33,6 @@
#include "rtu.h"
// HW RTU (should be given by wrsw_rtu_wb.h)
#define RTU_HCAM 0x4000
#define RTU_ARAM_MAIN 0x8000
#define RTU_VLAN_TAB 0xc000
#define RTU_MFIFO_R0_DATA_SEL 0x00000000
#define RTU_MFIFO_R1_ADDR_MASK 0x0007FFFF
...
...
userspace/wrsw_rtud/rtu_fd.c
View file @
2e9542b1
/*
/*
\
* White Rabbit RTU (Routing Table Unit)
* Copyright (C) 2010, CERN.
*
...
...
@@ -36,7 +36,7 @@
#include <unistd.h>
#include <pthread.h>
#include <hw/
wrsw_rtu_wb
.h>
#include <hw/
rtu_regs
.h>
#include <hw/trace.h>
#include "rtu_fd.h"
...
...
@@ -45,7 +45,6 @@
// Used to declare memory type at filtering database entry handles.
#define HTAB 0
#define HCAM 1
// Used to declare HW request types.
#define HW_WRITE_REQ 0
...
...
@@ -90,23 +89,10 @@ struct hw_req *hw_req_list;
*/
static
struct
filtering_entry
rtu_htab
[
HTAB_ENTRIES
][
RTU_BUCKETS
];
/**
* \brief Mirror of CAM lookup table.
* For RTU entries with more than 4 matches
*/
static
struct
filtering_entry
rtu_hcam
[
CAM_ENTRIES
];
/**
* \brief Table bank to write entries to.
* HTAB and HCAM banks will be handled according to this single bank value.
*/
static
uint8_t
bank
;
/**
* \brief Mirror of Aging RAM.
*/
static
uint32_t
rtu_agr_htab
[
RTU_ARAM_MAIN_WORDS
];
static
uint32_t
rtu_agr_hcam
;
static
uint32_t
rtu_agr_htab
[
RTU_ARAM_WORDS
];
/**
* \brief Max time that a dynamic MAC entry can remain
...
...
@@ -129,13 +115,10 @@ static void clean_list(struct hw_req *head);
static
int
add_hw_req
(
int
type
,
int
mem
,
uint16_t
addr
,
struct
filtering_entry
*
ent
);
static
inline
int
write_htab_entry
(
uint16_t
addr
,
struct
filtering_entry
*
e
);
static
inline
int
write_hcam_entry
(
uint16_t
addr
,
struct
filtering_entry
*
e
);
static
inline
int
clean_htab_entry
(
uint16_t
addr
);
static
inline
int
clean_hcam_entry
(
uint16_t
addr
);
static
inline
uint16_t
zbt_addr
(
uint16_t
hash
,
int
bucket
);
static
inline
uint16_t
cam_addr
(
int
bucket
);
static
inline
int
cam_bucket
(
uint16_t
cam_addr
);
...
...
@@ -143,12 +126,6 @@ static inline int matched(uint32_t word, int offset);
static
int
htab_contains
(
uint8_t
mac
[
ETH_ALEN
],
uint8_t
fid
,
int
*
bucket
,
struct
filtering_entry
**
ent
);
static
int
hcam_contains
(
uint8_t
mac
[
ETH_ALEN
],
uint8_t
fid
,
int
*
bucket
,
struct
filtering_entry
**
ent
);
static
int
find_empty_bucket_in_hcam
(
void
);
static
void
set_active_bank
(
int
n
);
static
void
clean_fd
(
void
);
static
void
clean_vd
(
void
);
...
...
@@ -160,10 +137,8 @@ static void rtu_hw_commit(void);
static
void
rtu_fd_commit
(
void
);
static
void
shift_htab_entries
(
uint16_t
hash
,
int
bucket
);
static
int
shift_hcam_entries
(
int
bucket
);
static
void
delete_htab_entry
(
uint16_t
hash
,
int
bucket
);
static
void
delete_hcam_entry
(
int
bucket
);
static
void
rtu_fd_age_out
(
void
);
static
void
rtu_fd_age_update
(
void
);
...
...
@@ -246,57 +221,10 @@ int rtu_fd_create_entry(uint8_t mac[ETH_ALEN], uint16_t vid, uint32_t port_map,
write_htab_entry
(
zbt_addr
(
hash
,
bucket
),
ent
);
break
;
case
NOT_FOUND_AND_FULL
:
// Not found and HTAB full for this hash
// Check whether HCAM was already used.
if
(
ent
->
go_to_cam
){
bucket
=
cam_bucket
(
ent
->
cam_addr
);
}
else
{
bucket
=
find_empty_bucket_in_hcam
();
if
(
bucket
<
0
)
{
ret
=
-
ENOMEM
;
break
;
}
// update htab last entry to point to hcam entry
ent
->
go_to_cam
=
1
;
ent
->
cam_addr
=
cam_addr
(
bucket
);
write_htab_entry
(
zbt_addr
(
hash
,
LAST_RTU_BUCKET
),
ent
);
}
/* fixme: allocate an entry in HTAB which is not used by any hash value */
// Check HCAM
ent
=
&
rtu_hcam
[
bucket
];
switch
(
hcam_contains
(
mac
,
fid
,
&
bucket
,
&
ent
)){
case
FOUND
:
// update
mask_dst
=
ent
->
port_mask_dst
|
port_map
;
mask_src
=
ent
->
port_mask_src
|
vlan_tab
[
vid
].
port_mask
;
if
((
ent
->
port_mask_dst
!=
mask_dst
)
||
(
ent
->
port_mask_src
!=
mask_src
))
{
// something new
ent
->
port_mask_dst
=
mask_dst
;
ent
->
port_mask_src
=
mask_src
;
write_hcam_entry
(
cam_addr
(
bucket
),
ent
);
}
break
;
case
NOT_FOUND
:
// existing list does not contain the entry and is necessary to
// append new entry at the end of current list
ent
->
end_of_bucket
=
0
;
write_hcam_entry
(
cam_addr
(
bucket
),
ent
);
ent
++
;
bucket
++
;
case
NOT_FOUND_AND_FIRST
:
// First entry in HCAM for this hash.
ent
->
valid
=
1
;
ent
->
end_of_bucket
=
1
;
ent
->
fid
=
fid
;
ent
->
port_mask_src
=
vlan_tab
[
vid
].
port_mask
;
ent
->
port_mask_dst
=
port_map
;
ent
->
dynamic
=
dynamic
;
ent
->
last_access_t
=
now
();
mac_copy
(
ent
->
mac
,
mac
);
write_hcam_entry
(
cam_addr
(
bucket
),
ent
);
break
;
default:
ret
=
-
ENOMEM
;
}
}
}
rtu_fd_commit
();
...
...
@@ -429,24 +357,12 @@ int write_htab_entry(uint16_t addr, struct filtering_entry *e)
return
add_hw_req
(
HW_WRITE_REQ
,
HTAB
,
addr
,
e
);
}
static
inline
int
write_hcam_entry
(
uint16_t
addr
,
struct
filtering_entry
*
e
)
{
return
add_hw_req
(
HW_WRITE_REQ
,
HCAM
,
addr
,
e
);
}
static
inline
int
clean_htab_entry
(
uint16_t
addr
)
{
return
add_hw_req
(
HW_CLEAN_REQ
,
HTAB
,
addr
,
NULL
);
}
static
inline
int
clean_hcam_entry
(
uint16_t
addr
)
{
return
add_hw_req
(
HW_CLEAN_REQ
,
HCAM
,
addr
,
NULL
);
}
static
inline
uint16_t
zbt_addr
(
uint16_t
hash
,
int
bucket
)
{
...
...
@@ -497,92 +413,6 @@ static int htab_contains(
return
-
EINVAL
;
}
/**
* Checks whether a given pair (mac,fid) is at HCAM
* @param mac mac address
* @param fid filtering database identifier
* @param bucket inout param.Returns the bucket number where the entry was found
* @param ent pointer to entry found.
* @return 0 if entry was not found. 1 if entry was found. -1 if entry was not
* found and the end of bucket was reached. -ENOMEM if no more entries after the
* end of bucket. -EINVAL if bucket >= CAM_ENTRIES or HCAM inconsistent.
*/
static
int
hcam_contains
(
uint8_t
mac
[
ETH_ALEN
],
uint8_t
fid
,
int
*
bucket
,
struct
filtering_entry
**
ent
)
{
for
(;
*
bucket
<
CAM_ENTRIES
;
(
*
bucket
)
++
,
(
*
ent
)
++
)
{
if
(
!
(
*
ent
)
->
valid
)
return
NOT_FOUND_AND_FIRST
;
if
(
mac_equal
((
*
ent
)
->
mac
,
mac
)
&&
((
*
ent
)
->
fid
==
fid
))
return
FOUND
;
if
((
*
ent
)
->
end_of_bucket
)
return
(
*
bucket
+
1
<
CAM_ENTRIES
)
&&
!
rtu_hcam
[
*
bucket
+
1
].
valid
?
NOT_FOUND
:-
ENOMEM
;
}
return
-
EINVAL
;
}
/**
* \brief Find the most appropriate empty bucket to insert new hash collision
* list. The algorithm first finds the fragment which contains the max number of
* consecutive empty positions. Then divides this fragment into two parts: first
* block is still available for possible increment of any existing list; The
* second block will be available for the new list.
* The algorithm keeps a fair and uniform distribution of fragments space.
* @return bucket index or -1 if the HCAM table is full.
*/
static
int
find_empty_bucket_in_hcam
(
void
)
{
int
bucket
=
0
;
// bucket loop index
int
res
=
0
;
// result bucket
int
empty
=
0
;
// consecutive empty buckets
int
max
=
0
;
// max consecutive empty buckets
// First obtain position with max consecutive empty space
for
(;
bucket
<
CAM_ENTRIES
;
bucket
++
)
{
if
(
rtu_hcam
[
bucket
].
valid
)
{
if
(
empty
>
max
)
{
max
=
empty
;
res
=
bucket
-
empty
;
}
empty
=
0
;
}
else
{
empty
++
;
}
}
// Update max consecutive empty buckets if necessary
if
(
empty
>
max
)
{
max
=
empty
;
res
=
bucket
-
empty
;
}
if
(
max
==
0
)
// bank is full
return
-
1
;
else
if
(
max
==
CAM_ENTRIES
)
// bank is empty
return
0
;
else
// Divide max space in two blocks and take address of second block
return
res
+
max
/
2
;
}
/**
* \brief Set the filtering database active bank both in software and hardware.
* Note both HTAB and HCAM active banks are switched at once.
* Bank switching is delayed until MFIFO is empty (method remains blocked
* meanwhile).
*/
static
void
set_active_bank
(
int
b
)
{
// wait until MFIFO is empty
rtu_clean_mfifo
();
// inactive bank becomes active (both banks are switched at once)
rtu_set_active_bank
(
b
);
// active bank becomes inactive one
bank
=
(
b
==
0
)
?
1
:
0
;
}
/**
* Filtering database initialisation.
...
...
@@ -590,14 +420,8 @@ static void set_active_bank(int b)
static
void
clean_fd
(
void
)
{
memset
(
&
rtu_htab
,
0
,
sizeof
(
rtu_htab
));
memset
(
&
rtu_hcam
,
0
,
sizeof
(
rtu_hcam
));
set_active_bank
(
0
);
rtu_clean_htab
();
rtu_clean_hcam
();
set_active_bank
(
1
);
rtu_clean_htab
();
rtu_clean_hcam
();
}
/**
...
...
@@ -630,9 +454,7 @@ static void clean_aging_map(void)
{
int
i
;
rtu_agr_hcam
=
0x00000000
;
rtu_clean_agr_hcam
();
for
(
i
=
0
;
i
<
RTU_ARAM_MAIN_WORDS
;
i
++
)
{
for
(
i
=
0
;
i
<
RTU_ARAM_WORDS
;
i
++
)
{
rtu_agr_htab
[
i
]
=
0x00000000
;
}
rtu_clean_agr_htab
();
...
...
@@ -645,8 +467,7 @@ static void update_aging_map(void)
{
int
i
;
rtu_agr_hcam
=
rtu_read_agr_hcam
();
for
(
i
=
0
;
i
<
RTU_ARAM_MAIN_WORDS
;
i
++
)
{
for
(
i
=
0
;
i
<
RTU_ARAM_WORDS
;
i
++
)
{
rtu_agr_htab
[
i
]
=
rtu_read_agr_htab
(
i
);
}
}
...
...
@@ -667,7 +488,7 @@ static void rtu_fd_age_update(void)
// Update 'last access time' for accessed entries
t
=
now
();
// HTAB
for
(
i
=
0
;
i
<
RTU_ARAM_
MAIN_
WORDS
;
i
++
)
{
for
(
i
=
0
;
i
<
RTU_ARAM_WORDS
;
i
++
)
{
agr_word
=
rtu_agr_htab
[
i
];
if
(
agr_word
!=
0x00000000
)
{
for
(
j
=
0
;
j
<
32
;
j
++
){
...
...
@@ -690,19 +511,6 @@ static void rtu_fd_age_update(void)
}
}
}
// HCAM
agr_word
=
rtu_agr_hcam
;
for
(
j
=
0
;
j
<
32
;
j
++
){
if
(
matched
(
agr_word
,
j
))
{
rtu_hcam
[
j
].
last_access_t
=
t
;
TRACE
(
TRACE_INFO
,
"updated hcam entry age: mac = %s, bucket = %d
\n
"
,
mac_to_string
(
rtu_hcam
[
j
].
mac
),
j
);
}
}
}
/**
...
...
@@ -717,19 +525,6 @@ static void rtu_fd_age_out(void)
unsigned
long
t
;
// (secs)
t
=
now
()
-
aging_time
;
// HCAM
for
(
j
=
CAM_ENTRIES
;
j
--
>
0
;){
ent
=
&
rtu_hcam
[
j
];
if
(
ent
->
valid
&&
ent
->
dynamic
&&
time_after
(
t
,
ent
->
last_access_t
))
{
TRACE
(
TRACE_INFO
,
"deleting hcam entry: mac = %s, bucket = %d
\n
"
,
mac_to_string
(
ent
->
mac
),
j
);
delete_hcam_entry
(
j
);
}
}
// HTAB
for
(
i
=
HTAB_ENTRIES
;
i
--
>
0
;)
{
for
(
j
=
RTU_BUCKETS
;
j
--
>
0
;)
{
...
...
@@ -763,14 +558,10 @@ static void rtu_hw_commit(void)
case
HW_WRITE_REQ
:
if
(
req
->
handle
.
mem_type
==
HTAB
)
rtu_write_htab_entry
(
req
->
handle
.
addr
,
req
->
handle
.
entry_ptr
);
else
rtu_write_hcam_entry
(
req
->
handle
.
addr
,
req
->
handle
.
entry_ptr
);
break
;
case
HW_CLEAN_REQ
:
if
(
req
->
handle
.
mem_type
==
HTAB
)
rtu_clean_htab_entry
(
req
->
handle
.
addr
);
else
rtu_clean_hcam_entry
(
req
->
handle
.
addr
);
break
;
}
}
...
...
@@ -784,11 +575,6 @@ static void rtu_fd_commit(void)
if
(
!
hw_req_list
)
return
;
// write entries to inactive bank
rtu_hw_commit
();
// switch bank to make entries available to RTU at HW
set_active_bank
(
bank
);
// both banks need same content
rtu_hw_commit
();
// this list no longer needed
...
...
@@ -819,71 +605,6 @@ static void shift_htab_entries(uint16_t hash, int bucket)
}
}
/**
* \brief Shifts HCAM list one position, starting at bucket.
* If entry to remove is end of bucket, marks previous one (if exists) as the
* new end of bucket.
* @return -1 if more entries remain in HCAM. Otherwise, returns the hash for
* entry, in order to help modifying the last HTAB entry
*/
static
int
shift_hcam_entries
(
int
bucket
)
{
struct
filtering_entry
*
ent
;
// entry to remove
struct
filtering_entry
*
next_ent
;
// following entry
struct
filtering_entry
*
prev_ent
;
// previous entry
int
ret
;
// return value
int
i
;
ret
=
-
1
;
ent
=
&
rtu_hcam
[
bucket
];
for
(
i
=
bucket
;
i
<
LAST_CAM_ENTRY
;
i
++
){
if
(
ent
->
end_of_bucket
){
if
(
i
>
bucket
)
// entry to remove was not the last
break
;
if
(
i
==
0
){
// entry to remove was last but there are no previous
ret
=
rtu_hash
(
ent
->
mac
,
ent
->
fid
);
break
;
}
prev_ent
=
ent
-
1
;
if
(
!
prev_ent
->
valid
||
prev_ent
->
end_of_bucket
){
// prev entry not valid or part of another list
ret
=
rtu_hash
(
ent
->
mac
,
ent
->
fid
);
break
;
}
// mark previous as end_of_bucket
prev_ent
->
end_of_bucket
=
1
;
write_hcam_entry
(
cam_addr
(
i
-
1
),
prev_ent
);
break
;
}
next_ent
=
&
rtu_hcam
[
i
+
1
];
rtu_fe_copy
(
ent
,
next_ent
);
write_hcam_entry
(
cam_addr
(
i
),
ent
);
ent
=
next_ent
;
}
rtu_fe_clean
(
ent
);
clean_hcam_entry
(
cam_addr
(
i
));
return
ret
;
}
/**
* \brief Deletes HCAM entry by shifting HCAM list.
* Updates HTAB last entry if neccessary.
* @param bucket CAM entry address
*/
static
void
delete_hcam_entry
(
int
bucket
)
{
struct
filtering_entry
*
ent
;
int
hash
;
hash
=
shift_hcam_entries
(
bucket
);
if
(
hash
>
-
1
){
// no entries remain at HCAM
ent
=
&
rtu_htab
[
hash
][
LAST_RTU_BUCKET
];
ent
->
go_to_cam
=
0
;
ent
->
cam_addr
=
0
;
write_htab_entry
(
zbt_addr
(
hash
,
LAST_RTU_BUCKET
),
ent
);
}
}
/**
* \brief Deletes HTAB entry by shifting HTAB list.
...
...
@@ -894,39 +615,13 @@ static void delete_hcam_entry(int bucket)
static
void
delete_htab_entry
(
uint16_t
hash
,
int
bucket
)
{
struct
filtering_entry
*
ent
;
struct
filtering_entry
*
prev_ent
;
struct
filtering_entry
*
cam_ent
;
int
hcam_bucket
;
shift_htab_entries
(
hash
,
bucket
);
ent
=
&
rtu_htab
[
hash
][
LAST_RTU_BUCKET
];
if
(
ent
->
go_to_cam
)
{
// HCAM used
// go_to_cam was copied to prev_ent while shifting. clean it.
prev_ent
=
ent
-
1
;
prev_ent
->
go_to_cam
=
0
;
prev_ent
->
cam_addr
=
0
;
// changes will be written to hw when shift operations are commited
// copy first cam entry into last HTAB entry
hcam_bucket
=
cam_bucket
(
ent
->
cam_addr
);
cam_ent
=
&
rtu_hcam
[
hcam_bucket
];
rtu_fe_copy
(
ent
,
cam_ent
);
if
(
ent
->
end_of_bucket
){
// entry was the only one in HCAM
ent
->
go_to_cam
=
0
;
ent
->
cam_addr
=
0
;
ent
->
end_of_bucket
=
0
;
}
else
{
// point to the next one
ent
->
go_to_cam
=
1
;
ent
->
cam_addr
=
cam_addr
(
hcam_bucket
+
1
);
}
write_htab_entry
(
zbt_addr
(
hash
,
LAST_RTU_BUCKET
),
ent
);
// clean HCAM entry
rtu_fe_clean
(
cam_ent
);
clean_hcam_entry
(
cam_addr
(
hcam_bucket
));
}
else
if
(
ent
->
valid
)
{
if
(
ent
->
valid
)
{
// clean last HTAB entry
rtu_fe_clean
(
ent
);
clean_htab_entry
(
zbt_addr
(
hash
,
LAST_RTU_BUCKET
));
...
...
userspace/wrsw_rtud/rtu_fd.h
View file @
2e9542b1
userspace/wrsw_rtud/rtu_hash.c
View file @
2e9542b1
...
...
@@ -28,6 +28,8 @@
*/
#include <hw/trace.h>
#include "rtu.h"
#include "rtu_hash.h"
...
...
@@ -53,7 +55,7 @@ uint16_t rtu_hash(uint8_t mac[ETH_ALEN], uint8_t fid)
hash
=
crc16
(
hash
,
((
uint16_t
)
mac
[
2
]
<<
8
)
|
mac
[
3
]);
hash
=
crc16
(
hash
,
((
uint16_t
)
mac
[
4
]
<<
8
)
|
mac
[
5
]);
return
hash
&
0x7FF
;
// trim to fit in ZBT SRAM addr
return
hash
&
(
HTAB_ENTRIES
-
1
);
/* warning: assumes that HTAB_ENTRIES is a power of 2 */
}
/*
...
...
userspace/wrsw_rtud/rtu_hash.h
View file @
2e9542b1
userspace/wrsw_rtud/rtud.c
View file @
2e9542b1
...
...
@@ -122,7 +122,7 @@ static void *rtu_daemon_wripc_process(void *arg)
{
while
(
1
){
rtud_handle_wripc
();
sleep
(
1
);
usleep
(
10000
);
}
return
NULL
;
}
...
...
@@ -195,7 +195,6 @@ static int rtu_daemon_init(uint16_t poly, unsigned long aging_time)
TRACE
(
TRACE_INFO
,
"init port config."
);
for
(
i
=
MIN_PORT
;
i
<=
MAX_PORT
;
i
++
)
{
// MIN_PORT <= port <= MAX_PORT, thus no err returned
fprintf
(
stderr
,
"**4**"
);
err
=
rtu_learn_enable_on_port
(
i
,
1
);
err
=
rtu_pass_all_on_port
(
i
,
1
);
...
...
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