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White Rabbit Switch - Software
Commit 6db696dd authored by Alessandro Rubini's avatar Alessandro Rubini
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doc: removed "installing from jtag" 

The information is not up to date with the new installation.  We are
not using JTAG ourselves these times, so we'd better remove this
chapter, stating it is still in the history of the package, if it is
needed by someone.
Signed-off-by: Alessandro Rubini's avatarAlessandro Rubini <rubini@gnudd.com>
parent 9d6e7aae
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doc/wrs-build.in
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......@@ -1662,171 +1662,16 @@ For example, the v3.3 backplane with v3.3 LX240T SCB must be configured as bello
As an alternative to the serial flasher, you can take control of the
system with a JTAG debugger. Please note that
the @i{USB Flasher} is @b{really} the preferred technique, but in case
it doesn't work for your, JTAG is the only way to
it doesn't work for you, JTAG is the only way to
communicate with the switch.
Each debugger has its own command language, so you will need to adapt
to yours. What is shown here refers to the @i{peedi} & @i{sam-ice} tools.
These notes are only aimed at low-level developers and leave a lot
unsaid.
Previous versions of this manual included detailed instructions about
such recovery procedure, but we have not been using JTAG for a long
while, so we didn't update the information to the V4 filesystem layout.
@menu
* Using PEEDI::
* Using SAM-ICE::
* Installation the Boot Loader from JTAG::
@end menu
@c ==========================================================================
@node Using PEEDI
@section Using PEEDI
As a first step, you will need to ensure the JTAG clock is slow enough.
The clock can be no faster than 1/6th of the CPU clock, so you need
3kHz at most (the G45 starts up with an internal oscillator, which has
an unpredictable value between 20kHz and 40kHz). Then, I would verify
that the internal SRAM is working; I do that with cool food and bad
coffee instead of the usual smelly dead beef.
@smallexample
clock init
mem write 0x300000 0xc001f00d
mem write 0x300004 0xbadc0ffe
mem read 0x300000 2
==> 0x300000: 0xC001F00D 0xBADC0FFE
@end smallexample
Now, you can load your @i{at91bootstrap} to the internal SRAM,
retrieving it from the network or your host filesystem. Since no boot
loader is there, you should place a breakpoint after @i{at91bootstrap}
initialized SDRAM and the PLL. Finally you can load @i{barebox} and jump
to it. Such step is better performed with the full JTAG clock, or
it would take several dozen minutes.
@smallexample
mem load at91bootstrap.bin 0x300000
break add hard 0x300088
go
## wait for the breakpoint to happen
break del all
clock normal
mem load barebox.bin 0x73f00000
go
@end smallexample
@c ==========================================================================
@node Using SAM-ICE
@section Using SAM-ICE
This section follows the same steps as in @ref{Using PEEDI}, but using
the syntax of the SAM-ICE tool recommended by Atmel
@example
./start
@end example
Checking SRAM
@smallexample
speed 2
w4 0x300000 0xc001f00d
w4 0x300004 0xcbadc0ffe
mem32 0x300000 2
@end smallexample
Uploading at91bootstrap & barebox to DDR
@smallexample
speed 2
r
wreg "R15 (PC)" 300000
loadbin /tftpboot/at91bootstrap.bin 0x300000
SetBP 0x300088 H #Check 0x300088
g
speed a
loadbin /tftpboot/barebox.bin 0x73f00000
ClrBP 1
g
@end smallexample
@c ==========================================================================
@node Installation the Boot Loader from JTAG
@section Installing the Boot Loader from JTAG
After tou managed to load and run @i{barebox.bin},
you will see the following messages on the serial port, at 115200,8N1.
The first 4 lines are printed by @i{at91bootstrap}, the rest by @i{barebox}.
@smallexample
Start AT91Bootstrap...
DDR2 Config: 0x39 (NC=0xa, NR=0xd, CAS=0x3, ba_offset = 0x18)
DDR2 Config: 0x39 (NC=0xa, NR=0xd, CAS=0x3, ba_offset = 0x18)
Compiled by Alessandro Rubini (May 2 2014 @ 18:32:34)
git rev:wr-switch-sw-v3.3.1-113-g0b2af1f+
Begin to load image...
++++++++++++++++
Loading image done.
barebox 2014.04.0 #1 Thu Jun 19 12:27:42 CEST 2014
Board: White Rabbit Switch
AT91: Detected soc type: at91sam9g45
AT91: Detected soc subtype: Unknown
Clocks: CPU 400 MHz, master 133 MHz, main 12.000 MHz
netconsole: registered as cs1
atmel_nand: Use On Flash BBT
nand: Trying ONFI probe in 16 bits mode, aborting !
nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xbc (Micron NAND 512MiB 1,8V 16-bit), 512MiB, page size: 2048, OOB size: 64
Bad block table found at page 262080, version 0x01
Bad block table found at page 262016, version 0x01
mtd_dataflash mtd_dataflash0: AT45DB642x (8448 KBytes) pagesize 1056 bytes (OTP)
mdio_bus: miibus0: probed
macb macb0: Cadence MACB at 0xfffbc000
GPIOs: PA4=1 (4), PC7=1 (71)
malloc space: 0x73b00000 -> 0x73efffff (size 4 MiB)
running /env/bin/init...
files differ at offset 0
Starting up barebox [wrs3] (MAC=22:23:24:25:26:27)
starting menu in 3 seconds
@end smallexample
When the boot loader is running, you can boot a kernel and use its
own @i{/dev/mtd} devices to write to the DataFlash and NAND memories.
According to the partition table you have in your kernel sources, you will
see a different set of @i{mtd} files, but you can identify them by looking
at @code{/proc/mtd}:
@c FIXME: mtd layout
@example
# cat /proc/mtd
mtd0: 00100000 00020000 "Barebox-environment-backup"
mtd1: 00800000 00020000 "Kernel"
mtd2: 08000000 00020000 "Filesystem"
mtd3: 14000000 00020000 "Available-nand"
mtd4: 00008400 00000420 "at91boot"
mtd5: 00084000 00000420 "Barebox"
mtd6: 00008400 00000420 "Barebox-Environment"
mtd7: 007ab800 00000420 "Available-dataflash"
@end example
Here above, the DataFlash is @i{/dev/mtd4} and later,
whereas the former partitions
refer to NAND memory. You should then write @i{at91boot} to @t{/dev/mtd4}
and @i{barebox} to @t{/dev/mtd5}, but the devices are not created
by default:
@example
mknod /dev/mtd4 c 90 8
cat at91bootstrap.bin > /dev/mtd4
mknod /dev/mtd5 c 90 10
cat barebox.bin > /dev/mtd5
@end example
Now you can detach the debugger, press reset and see @i{barebox} starting
without the need for the JTAG any more. The following steps are the same
as already described.
If you need to boot from JTAG, please refer to documentation in
version 3.3 or earlier of @t{wr-switch-sw} for generic ideas, knowing the
details are different.
@c ##########################################################################
@node Bugs and Troubleshooting
......
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