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White Rabbit Switch - Software
Commit 8a9dd5d5 authored by Juan Luis Manas's avatar Juan Luis Manas Committed by Alessandro Rubini
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wr_rtu: use the new wb header from ../wbgen-regs and associated symbols 

This removes duplicate register structures and uses the ../wbgen-regs
directory of the wr software package that now hosts the code
Signed-off-by: 's avatarJuan Luis Manas <juan.manas@integrasys.es>
Signed-off-by: 's avatarMiguel Baizan <miguel.baizan@integrasys.es>
parent 7bbf1650
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Showing with 10 additions and 474 deletions
wr_rtu/wr_rtu.c
View file @ 8a9dd5d5
......@@ -39,7 +39,7 @@
#include <linux/wait.h>
#include <linux/spinlock.h>
#include "wrsw_rtu_wb.h"
#include "../wbgen-regs/rtu-regs.h"
#include "wr_rtu.h"
#define DRV_MODULE_VERSION "0.1"
......@@ -58,37 +58,29 @@ struct wr_rtu_dev {
static struct wr_rtu_dev dev;
struct wr_rtu_regs {
u32 reg_idr; // [0x40]: Interrupt Disable Register
u32 reg_ier; // [0x44]: Interrupt Enable Register
u32 reg_imr; // [0x48]: Interrupt Mask Register
u32 reg_isr; // [0x4c]: Interrupt Status Register
u32 unused[5]; //
u32 reg_ufifo_csr; // [0x64]: UFIFO control/status Register
};
static struct RTU_WB __iomem *regs;
static struct wr_rtu_regs __iomem *regs;
#define wr_rtu_readl(r) __raw_readl(&regs->r);
#define wr_rtu_writel(val, r) __raw_writel(val, &regs->r);
static void wr_rtu_enable_irq(void)
{
wr_rtu_writel(RTU_EIC_IER_NEMPTY, reg_ier);
wr_rtu_writel(RTU_EIC_IER_NEMPTY, EIC_IER);
}
static void wr_rtu_disable_irq(void)
{
wr_rtu_writel(RTU_EIC_IDR_NEMPTY, reg_idr);
wr_rtu_writel(RTU_EIC_IDR_NEMPTY, EIC_IDR);
}
static void wr_rtu_clear_irq(void)
{
wr_rtu_writel(RTU_EIC_ISR_NEMPTY, reg_isr);
wr_rtu_writel(RTU_EIC_ISR_NEMPTY, EIC_ISR);
}
static int rtu_ufifo_is_empty(void)
{
uint32_t csr = wr_rtu_readl(reg_ufifo_csr);
uint32_t csr = wr_rtu_readl(UFIFO_CSR);
return RTU_UFIFO_CSR_EMPTY & csr;
}
......@@ -171,8 +163,8 @@ static int __init wr_rtu_init(void)
// map RTU memory
regs = ioremap(
FPGA_BASE_RTU + RTU_REG_EIC_IDR,
RTU_REG_MFIFO_R0 - RTU_REG_EIC_IDR
FPGA_BASE_RTU,
sizeof(struct RTU_WB)
);
if (!regs) {
......@@ -188,7 +180,7 @@ static int __init wr_rtu_init(void)
wr_rtu_interrupt,
IRQF_SHARED,
"wr-rtu",
regs
(void*)regs
);
// if succeeded, enable interrupts
......@@ -213,7 +205,7 @@ static void __exit wr_rtu_exit(void)
// disable RTU interrupts
wr_rtu_disable_irq();
// Unregister IRQ handler
free_irq(WRVIC_BASE_IRQ + WR_RTU_IRQ, regs);
free_irq(WRVIC_BASE_IRQ + WR_RTU_IRQ, (void*)regs);
// Unmap RTU memory
iounmap(regs);
// Unregister misc device driver
......
wr_rtu/wrsw_rtu_wb.h deleted 100644 → 0
View file @ 7bbf1650
/*
Register definitions for slave core: Routing Table Unit (RTU)
* File : wrsw_rtu_wb.h
* Author : auto-generated by wbgen2 from wrsw_rtu_wb.wb
* Created : Wed Oct 6 11:42:20 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_rtu_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_RTU_WB_WB
#define __WBGEN2_REGDEFS_WRSW_RTU_WB_WB
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: RTU Global Control Register */
/* definitions for field: Main table bank select in reg: RTU Global Control Register */
#define RTU_GCR_HT_BSEL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Hash collision table (HCAM) bank select in reg: RTU Global Control Register */
#define RTU_GCR_HCAM_BSEL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RTU Global Enable in reg: RTU Global Control Register */
#define RTU_GCR_G_ENA WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Hash Poly in reg: RTU Global Control Register */
#define RTU_GCR_POLY_VAL_MASK WBGEN2_GEN_MASK(8, 16)
#define RTU_GCR_POLY_VAL_SHIFT 8
#define RTU_GCR_POLY_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define RTU_GCR_POLY_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: Aging register for HCAM */
/* definitions for register: Port Control Register 0 */
/* definitions for field: Learning enable in reg: Port Control Register 0 */
#define RTU_PCR0_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 0 */
#define RTU_PCR0_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 0 */
#define RTU_PCR0_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 0 */
#define RTU_PCR0_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 0 */
#define RTU_PCR0_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR0_PRIO_VAL_SHIFT 4
#define RTU_PCR0_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR0_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 0 */
#define RTU_PCR0_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 1 */
/* definitions for field: Learning enable in reg: Port Control Register 1 */
#define RTU_PCR1_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 1 */
#define RTU_PCR1_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 1 */
#define RTU_PCR1_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 1 */
#define RTU_PCR1_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 1 */
#define RTU_PCR1_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR1_PRIO_VAL_SHIFT 4
#define RTU_PCR1_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR1_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 1 */
#define RTU_PCR1_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 2 */
/* definitions for field: Learning enable in reg: Port Control Register 2 */
#define RTU_PCR2_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 2 */
#define RTU_PCR2_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 2 */
#define RTU_PCR2_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 2 */
#define RTU_PCR2_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 2 */
#define RTU_PCR2_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR2_PRIO_VAL_SHIFT 4
#define RTU_PCR2_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR2_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 2 */
#define RTU_PCR2_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 3 */
/* definitions for field: Learning enable in reg: Port Control Register 3 */
#define RTU_PCR3_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 3 */
#define RTU_PCR3_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 3 */
#define RTU_PCR3_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 3 */
#define RTU_PCR3_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 3 */
#define RTU_PCR3_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR3_PRIO_VAL_SHIFT 4
#define RTU_PCR3_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR3_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 3 */
#define RTU_PCR3_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 4 */
/* definitions for field: Learning enable in reg: Port Control Register 4 */
#define RTU_PCR4_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 4 */
#define RTU_PCR4_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 4 */
#define RTU_PCR4_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 4 */
#define RTU_PCR4_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 4 */
#define RTU_PCR4_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR4_PRIO_VAL_SHIFT 4
#define RTU_PCR4_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR4_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 4 */
#define RTU_PCR4_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 5 */
/* definitions for field: Learning enable in reg: Port Control Register 5 */
#define RTU_PCR5_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 5 */
#define RTU_PCR5_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 5 */
#define RTU_PCR5_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 5 */
#define RTU_PCR5_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 5 */
#define RTU_PCR5_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR5_PRIO_VAL_SHIFT 4
#define RTU_PCR5_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR5_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 5 */
#define RTU_PCR5_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 6 */
/* definitions for field: Learning enable in reg: Port Control Register 6 */
#define RTU_PCR6_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 6 */
#define RTU_PCR6_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 6 */
#define RTU_PCR6_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 6 */
#define RTU_PCR6_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 6 */
#define RTU_PCR6_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR6_PRIO_VAL_SHIFT 4
#define RTU_PCR6_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR6_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 6 */
#define RTU_PCR6_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 7 */
/* definitions for field: Learning enable in reg: Port Control Register 7 */
#define RTU_PCR7_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 7 */
#define RTU_PCR7_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 7 */
#define RTU_PCR7_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 7 */
#define RTU_PCR7_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 7 */
#define RTU_PCR7_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR7_PRIO_VAL_SHIFT 4
#define RTU_PCR7_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR7_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 7 */
#define RTU_PCR7_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 8 */
/* definitions for field: Learning enable in reg: Port Control Register 8 */
#define RTU_PCR8_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 8 */
#define RTU_PCR8_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 8 */
#define RTU_PCR8_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 8 */
#define RTU_PCR8_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 8 */
#define RTU_PCR8_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR8_PRIO_VAL_SHIFT 4
#define RTU_PCR8_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR8_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 8 */
#define RTU_PCR8_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 9 */
/* definitions for field: Learning enable in reg: Port Control Register 9 */
#define RTU_PCR9_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 9 */
#define RTU_PCR9_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 9 */
#define RTU_PCR9_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 9 */
#define RTU_PCR9_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 9 */
#define RTU_PCR9_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR9_PRIO_VAL_SHIFT 4
#define RTU_PCR9_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR9_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 9 */
#define RTU_PCR9_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt disable register */
#define RTU_EIC_IDR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt enable register */
#define RTU_EIC_IER_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt mask register */
#define RTU_EIC_IMR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt status register */
#define RTU_EIC_ISR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
/* definitions for field: Destination MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_UFIFO_R0_DMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R0_DMAC_LO_SHIFT 0
#define RTU_UFIFO_R0_DMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R0_DMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
/* definitions for field: Destination MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_UFIFO_R1_DMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R1_DMAC_HI_SHIFT 0
#define RTU_UFIFO_R1_DMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R1_DMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
/* definitions for field: Source MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_UFIFO_R2_SMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R2_SMAC_LO_SHIFT 0
#define RTU_UFIFO_R2_SMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R2_SMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
/* definitions for field: Source MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_UFIFO_R3_SMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R3_SMAC_HI_SHIFT 0
#define RTU_UFIFO_R3_SMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R3_SMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
/* definitions for field: VLAN Identifier in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define RTU_UFIFO_R4_VID_SHIFT 0
#define RTU_UFIFO_R4_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_UFIFO_R4_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Priority in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PRIO_MASK WBGEN2_GEN_MASK(12, 3)
#define RTU_UFIFO_R4_PRIO_SHIFT 12
#define RTU_UFIFO_R4_PRIO_W(value) WBGEN2_GEN_WRITE(value, 12, 3)
#define RTU_UFIFO_R4_PRIO_R(reg) WBGEN2_GEN_READ(reg, 12, 3)
/* definitions for field: Port ID in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PID_MASK WBGEN2_GEN_MASK(16, 4)
#define RTU_UFIFO_R4_PID_SHIFT 16
#define RTU_UFIFO_R4_PID_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define RTU_UFIFO_R4_PID_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for field: VID valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_VID WBGEN2_GEN_MASK(20, 1)
/* definitions for field: PRIO valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_PRIO WBGEN2_GEN_MASK(21, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 7)
#define RTU_UFIFO_CSR_USEDW_SHIFT 0
#define RTU_UFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define RTU_UFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
/* definitions for field: Address/data select in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_MFIFO_R0_AD_SEL WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
/* definitions for field: Address/data value in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_MFIFO_R1_AD_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_MFIFO_R1_AD_VAL_SHIFT 0
#define RTU_MFIFO_R1_AD_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_MFIFO_R1_AD_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 6)
#define RTU_MFIFO_CSR_USEDW_SHIFT 0
#define RTU_MFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define RTU_MFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for RAM: Hash collisions memory (HCAM) */
#define RTU_HCAM_BYTES 0x00000800 /* size in bytes */
#define RTU_HCAM_WORDS 0x00000200 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: Aging bitmap for main hashtable */
#define RTU_ARAM_MAIN_BYTES 0x00000400 /* size in bytes */
#define RTU_ARAM_MAIN_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: VLAN table (VLAN_TAB) */
#define RTU_VLAN_TAB_BYTES 0x00004000 /* size in bytes */
#define RTU_VLAN_TAB_WORDS 0x00001000 /* size in 32-bit words, 32-bit aligned */
/* [0x0]: REG RTU Global Control Register */
#define RTU_REG_GCR 0x00000000
/* [0x4]: REG Aging register for HCAM */
#define RTU_REG_AGR_HCAM 0x00000004
/* [0x8]: REG Port Control Register 0 */
#define RTU_REG_PCR0 0x00000008
/* [0xc]: REG Port Control Register 1 */
#define RTU_REG_PCR1 0x0000000c
/* [0x10]: REG Port Control Register 2 */
#define RTU_REG_PCR2 0x00000010
/* [0x14]: REG Port Control Register 3 */
#define RTU_REG_PCR3 0x00000014
/* [0x18]: REG Port Control Register 4 */
#define RTU_REG_PCR4 0x00000018
/* [0x1c]: REG Port Control Register 5 */
#define RTU_REG_PCR5 0x0000001c
/* [0x20]: REG Port Control Register 6 */
#define RTU_REG_PCR6 0x00000020
/* [0x24]: REG Port Control Register 7 */
#define RTU_REG_PCR7 0x00000024
/* [0x28]: REG Port Control Register 8 */
#define RTU_REG_PCR8 0x00000028
/* [0x2c]: REG Port Control Register 9 */
#define RTU_REG_PCR9 0x0000002c
/* [0x40]: REG Interrupt disable register */
#define RTU_REG_EIC_IDR 0x00000040
/* [0x44]: REG Interrupt enable register */
#define RTU_REG_EIC_IER 0x00000044
/* [0x48]: REG Interrupt mask register */
#define RTU_REG_EIC_IMR 0x00000048
/* [0x4c]: REG Interrupt status register */
#define RTU_REG_EIC_ISR 0x0000004c
/* [0x50]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_REG_UFIFO_R0 0x00000050
/* [0x54]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_REG_UFIFO_R1 0x00000054
/* [0x58]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_REG_UFIFO_R2 0x00000058
/* [0x5c]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_REG_UFIFO_R3 0x0000005c
/* [0x60]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_REG_UFIFO_R4 0x00000060
/* [0x64]: REG FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_REG_UFIFO_CSR 0x00000064
/* [0x68]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_REG_MFIFO_R0 0x00000068
/* [0x6c]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_REG_MFIFO_R1 0x0000006c
/* [0x70]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_REG_MFIFO_CSR 0x00000070
#endif
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