Commit b51a3337 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Alessandro Rubini

kernel: updated WB file and header for the RTUd

parent dfc30f2a
This diff is collapsed.
-- -*- Mode: LUA; tab-width: 2 -*- -- -*- Mode: LUA; tab-width: 2 -*-
PCR_template = reg { peripheral {
name = "Routing Table Unit (RTU)";
prefix = "rtu";
hdl_entity="rtu_wishbone_slave";
-- Port Configuration Register
reg {
name = "RTU Global Control Register";
description = "Control register containing global (port-independent) settings of the RTU.";
prefix = "GCR";
field {
name = "RTU Global Enable";
description = "Global RTU enable bit. Overrides all port settings.\
0: RTU is disabled. All packets are dropped.\
1: RTU is enabled.";
type = BIT;
prefix = "G_ENA";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "clk_match_i";
};
field {
name = "MFIFO Trigger";
description = "write 1: triggers a flush of MFIFO into the hash table (blocks the RTU for a few cycles)\
write 0: no effect\
read 1: MFIFO is busy\
read 0: MFIFO is idle";
prefix = "MFIFOTRIG";
type = BIT;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_match_i";
};
field {
name = "Hash Poly";
description = "Determines the polynomial used for hash computation. Currently available: 0x1021, 0x8005, 0x0589 ";
type = SLV;
prefix = "POLY_VAL";
align = 8;
size = 16 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "clk_match_i";
};
};
reg {
name = "Port Select Register";
description = "Selects the port to control through the PCR register";
prefix = "PSR";
field {
name = "Port Select";
prefix = "PORT_SEL";
description = "Selected Port";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Number of ports";
prefix = "N_PORTS";
description = "Number of RTU ports compiled in.";
size = 8;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Port Control Register"; name = "Port Control Register";
description = "Register controlling the mode of certain RTU port."; description = "Register controlling the mode of the RTU port selected by PSELR register.";
prefix = "PCR"; prefix = "PCR";
field { field {
...@@ -12,8 +98,9 @@ PCR_template = reg { ...@@ -12,8 +98,9 @@ PCR_template = reg {
prefix = "LEARN_EN"; prefix = "LEARN_EN";
type = BIT; type = BIT;
access_dev = READ_ONLY; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
load = LOAD_EXT;
}; };
field { field {
...@@ -24,8 +111,9 @@ PCR_template = reg { ...@@ -24,8 +111,9 @@ PCR_template = reg {
prefix = "PASS_ALL"; prefix = "PASS_ALL";
type = BIT; type = BIT;
access_dev = READ_ONLY; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
load = LOAD_EXT;
}; };
field { field {
...@@ -36,8 +124,10 @@ PCR_template = reg { ...@@ -36,8 +124,10 @@ PCR_template = reg {
prefix = "PASS_BPDU"; prefix = "PASS_BPDU";
type = BIT; type = BIT;
access_dev = READ_ONLY; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
load = LOAD_EXT;
}; };
field { field {
...@@ -48,8 +138,9 @@ PCR_template = reg { ...@@ -48,8 +138,9 @@ PCR_template = reg {
prefix = "FIX_PRIO"; prefix = "FIX_PRIO";
type = BIT; type = BIT;
access_dev = READ_ONLY; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
load = LOAD_EXT;
}; };
...@@ -62,8 +153,9 @@ PCR_template = reg { ...@@ -62,8 +153,9 @@ PCR_template = reg {
type = SLV; type = SLV;
align = 4; align = 4;
size =3 ; size =3 ;
access_dev = READ_ONLY; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
load = LOAD_EXT;
}; };
...@@ -75,81 +167,13 @@ PCR_template = reg { ...@@ -75,81 +167,13 @@ PCR_template = reg {
prefix = "B_UNREC"; prefix = "B_UNREC";
type = BIT; type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
-- Mirroring Control fields go here.
};
peripheral {
name = "Routing Table Unit (RTU)";
prefix="rtu";
hdl_entity="wrsw_rtu_wb";
-- Port Configuration Register
reg {
name = "RTU Global Control Register";
description = "Control register containing global (port-independent) settings of the RTU.";
prefix = "GCR";
field {
name = "Main table bank select";
description = "Selects active bank of RTU hashtable (ZBT).\
0: bank 0 is used by lookup engine and bank 1 can be accessed using MFIFO\
1: bank 1 is used by lookup engine and bank 0 can be accessed using MFIFO";
type = BIT;
prefix = "HT_BSEL";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Hash collision table (HCAM) bank select";
description = "Selects active bank of RTU extra memory for colliding hashes.\
0: bank 0 is used by lookup engine\
1: bank 1 is used by lookup engine";
type = BIT;
prefix = "HCAM_BSEL";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "RTU Global Enable";
description = "Global RTU enable bit. Overrides all port settings.\
0: RTU is disabled. All packets are dropped.\
1: RTU is enabled.";
type = BIT;
prefix = "G_ENA";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field { access_dev = READ_WRITE;
name = "Hash Poly";
description = "Determines the polynomial used for hash computation. Currently available: 0x1021, 0x8005, 0x0589 ";
type = SLV;
prefix = "POLY_VAL";
align = 8;
size = 16 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE; access_bus = READ_WRITE;
load = LOAD_EXT;
}; };
clock = "zbt_clk_i";
}; };
-- TXTSU interrupts
irq { irq {
name = "UFIFO Not Empty IRQ"; name = "UFIFO Not Empty IRQ";
description = "Interrupt active when there are some requests in UFIFO."; description = "Interrupt active when there are some requests in UFIFO.";
...@@ -169,7 +193,7 @@ peripheral { ...@@ -169,7 +193,7 @@ peripheral {
flags_dev = {FIFO_FULL, FIFO_EMPTY}; flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY, FIFO_COUNT}; flags_bus = {FIFO_EMPTY, FIFO_COUNT};
--clock = "zbt_clk_i"; --clock = "clk_match_i";
-- clock = ""; - make it asynchronous if you want -- clock = ""; - make it asynchronous if you want
field { field {
...@@ -256,37 +280,21 @@ peripheral { ...@@ -256,37 +280,21 @@ peripheral {
}; };
}; };
ram {
name = "Hash collisions memory (HCAM)";
description = "Memory block containing the 'tails' for hashes which have more than 4 entries and don't fit into a single bucket of main ZBT hashtable. \
<b>Note:</b> MSB of the address is the bank select bit. ";
prefix = "HCAM";
width = 32;
size = 32 * 8 * 2; -- 32 entries * 8 words per entry * 2 banks
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "zbt_clk_i"; --async?
};
ram { ram {
name = "Aging bitmap for main hashtable"; name = "Aging bitmap for main hashtable";
description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\ description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
0: entry wasn't matched\ 0: entry wasn't matched\
1: entry was matched at least once.\ 1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters."; CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "ARAM_MAIN"; prefix = "ARAM";
width = 32; width = 32;
size = 8192 / 32; -- 8192 bits size = 8192 / 32; -- 8192 bits
access_dev = READ_WRITE; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
--[changed 6/10/2010] clock = "zbt_clk_i"; --[changed 6/10/2010] clock = "clk_match_i";
--clock = "zbt_clk_i"; --async? --clock = "clk_match_i"; --async?
}; };
...@@ -300,30 +308,8 @@ peripheral { ...@@ -300,30 +308,8 @@ peripheral {
access_dev = READ_ONLY; access_dev = READ_ONLY;
access_bus = READ_WRITE; access_bus = READ_WRITE;
-- --[changed 6/10/2010] clock = "zbt_clk_i"; -- --[changed 6/10/2010] clock = "clk_match_i";
--clock = "zbt_clk_i"; --async? --clock = "clk_match_i"; --async?
};
reg {
name = "Aging register for HCAM";
description = "Each bit in this register reflects the state of corresponding entry in HCAM:\
0: entry wasn't matched\
1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "AGR_HCAM";
field {
name = "Aging register value";
type = SLV;
size = 32;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
clock = "zbt_clk_i";
-- clock = "zbt_clk_i"; --async?
}; };
...@@ -356,22 +342,10 @@ peripheral { ...@@ -356,22 +342,10 @@ peripheral {
size = 32; size = 32;
}; };
clock = "zbt_clk_i"; clock = "clk_match_i";
}; };
}; };
function gen_PCRs(num_pcrs)
local i;
for i=0,num_pcrs-1 do
local rp = deepcopy(PCR_template);
rp.name = rp.name.." "..i;
rp.prefix = rp.prefix..i;
table.insert(periph, rp);
end
end
gen_PCRs(10);
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