Commit dd955562 authored by Benoit Rat's avatar Benoit Rat

shw_tool: update code to be compatible with v3.3 (add LED, IO, Temp, ...)

parent 962f8a25
## Makefile
#-------------------------------------------------------------------------------
# Makefile
#
# Copyright (c) 2012
# All rights reserved. This program and the accompanying materials
# are made available under the terms of the GNU Public License v2.0
# which accompanies this distribution, and is available at
# http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
#
# Contributors:
# Cesar Prados
# Benoit Rat
#-------------------------------------------------------------------------------
# Parameters
TMP=$(warning $(shell WRS_BASE_DIR=$(WRS_BASE_DIR)/ printenv | grep WRS_BASE_DIR))
ifeq ($(strip $(WRS_BASE_DIR)),)
$(error You first need to define WRS_BASE_DIR variable)
#WRS_BASE_DIR=/home/neub/Work/7S/WR/wr-switch-sw/build
endif
EXEC = shw_tool
INCLUDES =-I. -I${WRS_BASE_DIR}/../userspace/include -I${WRS_BASE_DIR}/../userspace/libswitchhw
LDFLAGS = -L${WRS_BASE_DIR}/../userspace/libswitchhw -lswitchhw -lm -ldl -llua
......@@ -16,7 +32,10 @@ CC = ${CROSS_COMPILE}gcc
#############
all: $(EXEC)
all: libswitchhw.a ${WRS_BASE_DIR}/../userspace/libswitchhw/libswitchhw.a $(EXEC)
libswitchhw.a:
$(MAKE) -C ${WRS_BASE_DIR}/../userspace/libswitchhw all
%.o: %.c %.h $(DEPS)
${CC} ${CFLAGS} -c $< -o $@
......@@ -32,9 +51,10 @@ clean:
INSTALLDIR=alpha-pts/bin/
install: all
cp ${EXEC} ../${INSTALLDIR}
$(MAKE) -C ${WRS_BASE_DIR}/../userspace/libswitchhw install
cp $(EXEC) ../$(INSTALLDIR)
cp $(EXEC) $(WR_INSTALL_ROOT)/bin/
#cp $(EXEC) $(WR_INSTALL_ROOT)/../$(INSTALLDIR)
cp: all
cp ${EXEC} ../${INSTALLDIR}
cp ${EXEC} /tftpboot/rootfs-test/${INSTALLDIR}
\ No newline at end of file
install2: libswitchhw.a clean install
This diff is collapsed.
/*
Register definitions for slave core: Wishbone monitor port
* File : header.h
* Author : auto-generated by wbgen2 from Sysmon_wbslavev5.wb
* Created : Thu Oct 11 16:51:24 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE Sysmon_wbslavev5.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SYSMON_WBSLAVEV5_WB
#define __WBGEN2_REGDEFS_SYSMON_WBSLAVEV5_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Temp register */
/* definitions for field: Reset bit in reg: Temp register */
#define WB2_SYSMON_TEMP_RESET WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Actual Temp in reg: Temp register */
#define WB2_SYSMON_TEMP_ACT_MASK WBGEN2_GEN_MASK(8, 8)
#define WB2_SYSMON_TEMP_ACT_SHIFT 8
#define WB2_SYSMON_TEMP_ACT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB2_SYSMON_TEMP_ACT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Max Temp in reg: Temp register */
#define WB2_SYSMON_TEMP_MAX_MASK WBGEN2_GEN_MASK(16, 8)
#define WB2_SYSMON_TEMP_MAX_SHIFT 16
#define WB2_SYSMON_TEMP_MAX_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define WB2_SYSMON_TEMP_MAX_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: Min Temp in reg: Temp register */
#define WB2_SYSMON_TEMP_MIN_MASK WBGEN2_GEN_MASK(24, 8)
#define WB2_SYSMON_TEMP_MIN_SHIFT 24
#define WB2_SYSMON_TEMP_MIN_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB2_SYSMON_TEMP_MIN_R(reg) WBGEN2_GEN_READ(reg, 24, 8)
/* definitions for register: Actual Voltage register */
/* definitions for field: Actual VccIN in reg: Actual Voltage register */
#define WB2_SYSMON_V_ACT_VCCIN_MASK WBGEN2_GEN_MASK(0, 16)
#define WB2_SYSMON_V_ACT_VCCIN_SHIFT 0
#define WB2_SYSMON_V_ACT_VCCIN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WB2_SYSMON_V_ACT_VCCIN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Actual VccAux in reg: Actual Voltage register */
#define WB2_SYSMON_V_ACT_VCCAUX_MASK WBGEN2_GEN_MASK(16, 16)
#define WB2_SYSMON_V_ACT_VCCAUX_SHIFT 16
#define WB2_SYSMON_V_ACT_VCCAUX_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WB2_SYSMON_V_ACT_VCCAUX_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Max. Voltage register */
/* definitions for field: Maximum VccIN in reg: Max. Voltage register */
#define WB2_SYSMON_V_MAX_VCCIN_MASK WBGEN2_GEN_MASK(0, 16)
#define WB2_SYSMON_V_MAX_VCCIN_SHIFT 0
#define WB2_SYSMON_V_MAX_VCCIN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WB2_SYSMON_V_MAX_VCCIN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Maximum VccAux in reg: Max. Voltage register */
#define WB2_SYSMON_V_MAX_VCCAUX_MASK WBGEN2_GEN_MASK(16, 16)
#define WB2_SYSMON_V_MAX_VCCAUX_SHIFT 16
#define WB2_SYSMON_V_MAX_VCCAUX_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WB2_SYSMON_V_MAX_VCCAUX_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Min. Voltage register */
/* definitions for field: Minimum VccIN in reg: Min. Voltage register */
#define WB2_SYSMON_V_MIN_VCCIN_MASK WBGEN2_GEN_MASK(0, 16)
#define WB2_SYSMON_V_MIN_VCCIN_SHIFT 0
#define WB2_SYSMON_V_MIN_VCCIN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WB2_SYSMON_V_MIN_VCCIN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Minimum VccAux in reg: Min. Voltage register */
#define WB2_SYSMON_V_MIN_VCCAUX_MASK WBGEN2_GEN_MASK(16, 16)
#define WB2_SYSMON_V_MIN_VCCAUX_SHIFT 16
#define WB2_SYSMON_V_MIN_VCCAUX_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WB2_SYSMON_V_MIN_VCCAUX_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
PACKED struct WB2_SYSMON_WB {
/* [0x0]: REG Temp register */
uint32_t TEMP;
/* [0x4]: REG Actual Voltage register */
uint32_t V_ACT;
/* [0x8]: REG Max. Voltage register */
uint32_t V_MAX;
/* [0xc]: REG Min. Voltage register */
uint32_t V_MIN;
};
#endif
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