set projDir [file dirname [info script]]

set_param general.maxThreads 8
get_param general.maxThreads

# Xilinx speed grades: 1,2,3: 1 = slowest, 3 = fastest
set speed   2
set kintex7 xc7k160tfbg676-${speed}
set device  ${kintex7}

set top     wr2rf_vme

# Check hdlmake has generated file dependencies
if {![file exists files.tcl]} {
    puts "File: files.tcl not found, please check hdlmake has generated the file dependencies."
    exit 1
}

source files.tcl

# constraint files
set swap_sfp false
if {$swap_sfp eq "true"} {
    read_xdc $projDir/${top}_sfp_swap.xdc
} else {
    read_xdc $projDir/${top}_sfp.xdc
}
read_xdc $projDir/${top}.xdc

set start_time [clock seconds]

#synth_design  -rtl -top ${top} -part ${device} > ${top}_synth.log
synth_design -top ${top} -part ${device} > ${top}_synth.log
write_checkpoint -force ${top}_synth

source wr2rf_async_regs.tcl
source wr2rf_maxdelays.tcl
source wr2rf_dmtd_falsepath.tcl
source wr2rf_t1sync_falsepath.tcl

#opt_design -directive Explore -verbose > ${top}_opt.log
#write_checkpoint -force ${top}_opt

#place_design -directive Explore > ${top}_place.log
place_design  > ${top}_place.log
place_design -post_place_opt
write_checkpoint -force ${projDir}/${top}_place

#phys_opt_design -directive Explore > ${top}_phys_opt.log
#write_checkpoint -force ${projDir}/${top}_phys_opt

route_design  > ${top}_route.log
write_checkpoint -force ${projDir}/${top}_route

source wr2rf_cdc_waivers.tcl
report_cdc -name wr2rf_cdc -file wr2rf_cdc.rpt

report_timing_summary -file ${top}_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type full -file ${top}_timing.rpt
report_utilization -hierarchical -file ${top}_utilization.rpt
report_io -file ${top}_pin.rpt

# Some reports to monitor min/max delays on key outputs plus skew for the iqdac data lines
source wr2rf_triggers.tcl
source wr2rf_iqdac_skew.tcl

# bitstream configuration...
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
# CONFIGRATE valid values for 7 series: 3, 6, 9, 12, 16, 22, 26, 33, 40, 50, 66
set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
write_bitstream -force ${projDir}/${top}.bit
write_cfgmem -force -format mcs -interface spix1 -size 16 -loadbit "up 0x0 ${top}.bit" ${top}.mcs

set end_time [clock seconds]
set total_time [ expr { $end_time - $start_time} ]
set absolute_time [clock format $total_time -format {%H:%M:%S} -gmt true ]
puts "\ntotal build time: $absolute_time\n"


