-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
-- Generated on Thu May 11 10:38:00 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

entity trigunit_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- Status register of the VTU.
    -- VTU is started, waiting for sync
    status_started_i     : in    std_logic;
    -- VTU is idle, waiting for a start
    status_idle_i        : in    std_logic;
    -- VTU core running
    status_running_i     : in    std_logic;
    -- Start ignored as VTU already running
    status_missIdle_i    : in    std_logic;
    -- Start ignored as no configuration parameters
    status_missValid_i   : in    std_logic;
    -- Start ignored as VTU not ready
    status_missReady_i   : in    std_logic;
    -- The VTU is ready to accept the start pulse
    status_startReady_i  : in    std_logic;
    -- Wrong B value for the current mode
    status_wrongBvalue_i : in    std_logic;
    -- Wrong HT value for the current mode
    status_wrongHTvalue_i : in    std_logic;
    -- Wrong W value for the current mode
    status_wrongWvalue_i : in    std_logic;

    -- Behaviour flags
    -- Consider offline values as always valid
    flags_forceValidOffline_o : out   std_logic;
    -- Start will stop the vtu if running
    flags_StartAsStop_o  : out   std_logic;

    -- Control signals
    -- Keep VTU and I/O serdes under reset
    control_vtuReset_o   : out   std_logic;
    -- Force stop
    control_stopSoftTrigger_o : out   std_logic;
    -- Force start.
    control_startSoftTrigger_o : out   std_logic;

    -- Control signals
    -- Running mode selector
    configOffline_mode_o : out   std_logic_vector(2 downto 0);
    -- Switch between HT and HT+1 values while running
    configOffline_htSwitchingEnable_o : out   std_logic;
    -- Offline values are set
    configOffline_valid_i : in    std_logic;
    configOffline_valid_o : out   std_logic;
    configOffline_wr_o   : out   std_logic;

    -- Number of RF clock cycles to delay (B)
    bValueOffline_o      : out   std_logic_vector(63 downto 0);

    -- Not used in singlePulse and playMemory modes
    htValueOffline_o     : out   std_logic_vector(63 downto 0);

    -- Used in windowedOperation mode
    wValueOffline_o      : out   std_logic_vector(63 downto 0);

    -- Control signals
    -- Running mode selector
    configOnline_mode_i  : in    std_logic_vector(2 downto 0);
    -- Switch between HT and HT+1 values while running
    configOnline_htSwitchingEnable_i : in    std_logic;

    -- Used in all modes
    bValueOnline_i       : in    std_logic_vector(63 downto 0);

    -- Not used in singlePulse and playMemory modes
    htValueOnline_i      : in    std_logic_vector(63 downto 0);

    -- Used in windowedOperation mode
    wValueOnline_i       : in    std_logic_vector(63 downto 0);

    -- Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay
    trigOHCDelay_set_o   : out   std_logic;

    -- Delay on the trigger output
    -- value
    trigODelay_delay_o   : out   std_logic_vector(4 downto 0);

    -- Timestamp TAI seconds of the first VTU output trigger after a start pulse
    TS_FirstTrigTAIsec_i : in    std_logic_vector(63 downto 0);

    -- Timestamp TAI cycles of the first VTU output trigger after a start pulse
    TS_FirstTrigTAIcycles_i : in    std_logic_vector(31 downto 0);

    -- Timestamp TAI seconds of the last VTU output trigger
    TS_LastTrigTAIsec_i  : in    std_logic_vector(63 downto 0);

    -- Timestamp TAI cycles of the last VTU output trigger
    TS_LastTrigTAIcycles_i : in    std_logic_vector(31 downto 0);

    -- Control register
    -- Enable the unit
    trigdiag_control_enable_o : out   std_logic;
    -- Select the window to measure the frequency.  A change to this value is taken into account at the end of the current window. 000: 5us; 010: 500us; 100: 50ms; 101: 5s; 110: 20s 001, 011, 111: unused.
    trigdiag_control_window_o : out   std_logic_vector(2 downto 0);

    -- This register is incremented at the end of the window, when the new frequency is made available.
    trigdiag_generation_i : in    std_logic_vector(15 downto 0);

    -- Number of period of the input signal during the previous window period.
    trigdiag_freq_i      : in    std_logic_vector(31 downto 0);

    -- This register is incremented on each rising edge of the signal. Not valid if the input frequency is greater than the clock.
    trigdiag_counter_i   : in    std_logic_vector(31 downto 0)
  );
end trigunit_regs;

architecture syn of trigunit_regs is
  signal adr_int                        : std_logic_vector(6 downto 1);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal flags_forceValidOffline_reg    : std_logic;
  signal flags_StartAsStop_reg          : std_logic;
  signal flags_wreq                     : std_logic;
  signal flags_wack                     : std_logic;
  signal control_vtuReset_reg           : std_logic;
  signal control_stopSoftTrigger_reg    : std_logic;
  signal control_startSoftTrigger_reg   : std_logic;
  signal control_wreq                   : std_logic;
  signal control_wack                   : std_logic;
  signal configOffline_mode_reg         : std_logic_vector(2 downto 0);
  signal configOffline_htSwitchingEnable_reg : std_logic;
  signal configOffline_wreq             : std_logic;
  signal configOffline_wack             : std_logic;
  signal bValueOffline_reg              : std_logic_vector(63 downto 0);
  signal bValueOffline_wreq             : std_logic_vector(3 downto 0);
  signal bValueOffline_wack             : std_logic_vector(3 downto 0);
  signal htValueOffline_reg             : std_logic_vector(63 downto 0);
  signal htValueOffline_wreq            : std_logic_vector(3 downto 0);
  signal htValueOffline_wack            : std_logic_vector(3 downto 0);
  signal wValueOffline_reg              : std_logic_vector(63 downto 0);
  signal wValueOffline_wreq             : std_logic_vector(3 downto 0);
  signal wValueOffline_wack             : std_logic_vector(3 downto 0);
  signal trigOHCDelay_set_reg           : std_logic;
  signal trigOHCDelay_wreq              : std_logic;
  signal trigOHCDelay_wack              : std_logic;
  signal trigODelay_delay_reg           : std_logic_vector(4 downto 0);
  signal trigODelay_wreq                : std_logic;
  signal trigODelay_wack                : std_logic;
  signal trigdiag_control_enable_reg    : std_logic;
  signal trigdiag_control_window_reg    : std_logic_vector(2 downto 0);
  signal trigdiag_control_wreq          : std_logic;
  signal trigdiag_control_wack          : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(15 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(6 downto 1);
  signal wr_dat_d0                      : std_logic_vector(15 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(6 downto 1);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat(15 downto 0) <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat(15 downto 0);
      end if;
    end if;
  end process;

  -- Register status

  -- Register flags
  flags_forceValidOffline_o <= flags_forceValidOffline_reg;
  flags_StartAsStop_o <= flags_StartAsStop_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        flags_forceValidOffline_reg <= '0';
        flags_StartAsStop_reg <= '0';
        flags_wack <= '0';
      else
        if flags_wreq = '1' then
          flags_forceValidOffline_reg <= wr_dat_d0(0);
          flags_StartAsStop_reg <= wr_dat_d0(1);
        end if;
        flags_wack <= flags_wreq;
      end if;
    end if;
  end process;

  -- Register control
  control_vtuReset_o <= control_vtuReset_reg;
  control_stopSoftTrigger_o <= control_stopSoftTrigger_reg;
  control_startSoftTrigger_o <= control_startSoftTrigger_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        control_vtuReset_reg <= '1';
        control_stopSoftTrigger_reg <= '0';
        control_startSoftTrigger_reg <= '0';
        control_wack <= '0';
      else
        if control_wreq = '1' then
          control_vtuReset_reg <= wr_dat_d0(2);
          control_stopSoftTrigger_reg <= wr_dat_d0(1);
          control_startSoftTrigger_reg <= wr_dat_d0(0);
        else
          control_stopSoftTrigger_reg <= '0';
          control_startSoftTrigger_reg <= '0';
        end if;
        control_wack <= control_wreq;
      end if;
    end if;
  end process;

  -- Register configOffline
  configOffline_mode_o <= configOffline_mode_reg;
  configOffline_htSwitchingEnable_o <= configOffline_htSwitchingEnable_reg;
  configOffline_valid_o <= wr_dat_d0(0);
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        configOffline_mode_reg <= "000";
        configOffline_htSwitchingEnable_reg <= '0';
        configOffline_wack <= '0';
      else
        if configOffline_wreq = '1' then
          configOffline_mode_reg <= wr_dat_d0(6 downto 4);
          configOffline_htSwitchingEnable_reg <= wr_dat_d0(1);
        end if;
        configOffline_wack <= configOffline_wreq;
      end if;
    end if;
  end process;
  configOffline_wr_o <= configOffline_wack;

  -- Register bValueOffline
  bValueOffline_o <= bValueOffline_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        bValueOffline_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        bValueOffline_wack <= (others => '0');
      else
        if bValueOffline_wreq(0) = '1' then
          bValueOffline_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if bValueOffline_wreq(1) = '1' then
          bValueOffline_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if bValueOffline_wreq(2) = '1' then
          bValueOffline_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if bValueOffline_wreq(3) = '1' then
          bValueOffline_reg(63 downto 48) <= wr_dat_d0;
        end if;
        bValueOffline_wack <= bValueOffline_wreq;
      end if;
    end if;
  end process;

  -- Register htValueOffline
  htValueOffline_o <= htValueOffline_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        htValueOffline_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        htValueOffline_wack <= (others => '0');
      else
        if htValueOffline_wreq(0) = '1' then
          htValueOffline_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if htValueOffline_wreq(1) = '1' then
          htValueOffline_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if htValueOffline_wreq(2) = '1' then
          htValueOffline_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if htValueOffline_wreq(3) = '1' then
          htValueOffline_reg(63 downto 48) <= wr_dat_d0;
        end if;
        htValueOffline_wack <= htValueOffline_wreq;
      end if;
    end if;
  end process;

  -- Register wValueOffline
  wValueOffline_o <= wValueOffline_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wValueOffline_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        wValueOffline_wack <= (others => '0');
      else
        if wValueOffline_wreq(0) = '1' then
          wValueOffline_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if wValueOffline_wreq(1) = '1' then
          wValueOffline_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if wValueOffline_wreq(2) = '1' then
          wValueOffline_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if wValueOffline_wreq(3) = '1' then
          wValueOffline_reg(63 downto 48) <= wr_dat_d0;
        end if;
        wValueOffline_wack <= wValueOffline_wreq;
      end if;
    end if;
  end process;

  -- Register configOnline

  -- Register bValueOnline

  -- Register htValueOnline

  -- Register wValueOnline

  -- Register trigOHCDelay
  trigOHCDelay_set_o <= trigOHCDelay_set_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        trigOHCDelay_set_reg <= '0';
        trigOHCDelay_wack <= '0';
      else
        if trigOHCDelay_wreq = '1' then
          trigOHCDelay_set_reg <= wr_dat_d0(0);
        end if;
        trigOHCDelay_wack <= trigOHCDelay_wreq;
      end if;
    end if;
  end process;

  -- Register trigODelay
  trigODelay_delay_o <= trigODelay_delay_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        trigODelay_delay_reg <= "00000";
        trigODelay_wack <= '0';
      else
        if trigODelay_wreq = '1' then
          trigODelay_delay_reg <= wr_dat_d0(4 downto 0);
        end if;
        trigODelay_wack <= trigODelay_wreq;
      end if;
    end if;
  end process;

  -- Register TS_FirstTrigTAIsec

  -- Register TS_FirstTrigTAIcycles

  -- Register TS_LastTrigTAIsec

  -- Register TS_LastTrigTAIcycles

  -- Register trigdiag_control
  trigdiag_control_enable_o <= trigdiag_control_enable_reg;
  trigdiag_control_window_o <= trigdiag_control_window_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        trigdiag_control_enable_reg <= '0';
        trigdiag_control_window_reg <= "000";
        trigdiag_control_wack <= '0';
      else
        if trigdiag_control_wreq = '1' then
          trigdiag_control_enable_reg <= wr_dat_d0(4);
          trigdiag_control_window_reg <= wr_dat_d0(2 downto 0);
        end if;
        trigdiag_control_wack <= trigdiag_control_wreq;
      end if;
    end if;
  end process;

  -- Register trigdiag_generation

  -- Register trigdiag_freq

  -- Register trigdiag_counter

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, flags_wack, control_wack, configOffline_wack,
           bValueOffline_wack, htValueOffline_wack, wValueOffline_wack,
           trigOHCDelay_wack, trigODelay_wack, trigdiag_control_wack) begin
    flags_wreq <= '0';
    control_wreq <= '0';
    configOffline_wreq <= '0';
    bValueOffline_wreq <= (others => '0');
    htValueOffline_wreq <= (others => '0');
    wValueOffline_wreq <= (others => '0');
    trigOHCDelay_wreq <= '0';
    trigODelay_wreq <= '0';
    trigdiag_control_wreq <= '0';
    case wr_adr_d0(6 downto 3) is
    when "0000" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg status
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg flags
        flags_wreq <= wr_req_d0;
        wr_ack_int <= flags_wack;
      when "10" =>
        -- Reg control
        control_wreq <= wr_req_d0;
        wr_ack_int <= control_wack;
      when "11" =>
        -- Reg configOffline
        configOffline_wreq <= wr_req_d0;
        wr_ack_int <= configOffline_wack;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0001" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg bValueOffline
        bValueOffline_wreq(3) <= wr_req_d0;
        wr_ack_int <= bValueOffline_wack(3);
      when "01" =>
        -- Reg bValueOffline
        bValueOffline_wreq(2) <= wr_req_d0;
        wr_ack_int <= bValueOffline_wack(2);
      when "10" =>
        -- Reg bValueOffline
        bValueOffline_wreq(1) <= wr_req_d0;
        wr_ack_int <= bValueOffline_wack(1);
      when "11" =>
        -- Reg bValueOffline
        bValueOffline_wreq(0) <= wr_req_d0;
        wr_ack_int <= bValueOffline_wack(0);
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0010" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg htValueOffline
        htValueOffline_wreq(3) <= wr_req_d0;
        wr_ack_int <= htValueOffline_wack(3);
      when "01" =>
        -- Reg htValueOffline
        htValueOffline_wreq(2) <= wr_req_d0;
        wr_ack_int <= htValueOffline_wack(2);
      when "10" =>
        -- Reg htValueOffline
        htValueOffline_wreq(1) <= wr_req_d0;
        wr_ack_int <= htValueOffline_wack(1);
      when "11" =>
        -- Reg htValueOffline
        htValueOffline_wreq(0) <= wr_req_d0;
        wr_ack_int <= htValueOffline_wack(0);
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0011" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg wValueOffline
        wValueOffline_wreq(3) <= wr_req_d0;
        wr_ack_int <= wValueOffline_wack(3);
      when "01" =>
        -- Reg wValueOffline
        wValueOffline_wreq(2) <= wr_req_d0;
        wr_ack_int <= wValueOffline_wack(2);
      when "10" =>
        -- Reg wValueOffline
        wValueOffline_wreq(1) <= wr_req_d0;
        wr_ack_int <= wValueOffline_wack(1);
      when "11" =>
        -- Reg wValueOffline
        wValueOffline_wreq(0) <= wr_req_d0;
        wr_ack_int <= wValueOffline_wack(0);
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0100" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg configOnline
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0101" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg bValueOnline
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg bValueOnline
        wr_ack_int <= wr_req_d0;
      when "10" =>
        -- Reg bValueOnline
        wr_ack_int <= wr_req_d0;
      when "11" =>
        -- Reg bValueOnline
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0110" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg htValueOnline
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg htValueOnline
        wr_ack_int <= wr_req_d0;
      when "10" =>
        -- Reg htValueOnline
        wr_ack_int <= wr_req_d0;
      when "11" =>
        -- Reg htValueOnline
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "0111" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg wValueOnline
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg wValueOnline
        wr_ack_int <= wr_req_d0;
      when "10" =>
        -- Reg wValueOnline
        wr_ack_int <= wr_req_d0;
      when "11" =>
        -- Reg wValueOnline
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1000" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg trigOHCDelay
        trigOHCDelay_wreq <= wr_req_d0;
        wr_ack_int <= trigOHCDelay_wack;
      when "01" =>
        -- Reg trigODelay
        trigODelay_wreq <= wr_req_d0;
        wr_ack_int <= trigODelay_wack;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1001" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg TS_FirstTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg TS_FirstTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when "10" =>
        -- Reg TS_FirstTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when "11" =>
        -- Reg TS_FirstTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1010" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg TS_FirstTrigTAIcycles
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg TS_FirstTrigTAIcycles
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1011" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg TS_LastTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg TS_LastTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when "10" =>
        -- Reg TS_LastTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when "11" =>
        -- Reg TS_LastTrigTAIsec
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1100" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg TS_LastTrigTAIcycles
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg TS_LastTrigTAIcycles
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1110" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        case wr_adr_d0(1 downto 1) is
        when "0" =>
          -- Reg trigdiag_control
          trigdiag_control_wreq <= wr_req_d0;
          wr_ack_int <= trigdiag_control_wack;
        when "1" =>
          -- Reg trigdiag_generation
          wr_ack_int <= wr_req_d0;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "1" =>
        case wr_adr_d0(1 downto 1) is
        when "0" =>
          -- Reg trigdiag_freq
          wr_ack_int <= wr_req_d0;
        when "1" =>
          -- Reg trigdiag_freq
          wr_ack_int <= wr_req_d0;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1111" =>
      case wr_adr_d0(2 downto 1) is
      when "00" =>
        -- Reg trigdiag_counter
        wr_ack_int <= wr_req_d0;
      when "01" =>
        -- Reg trigdiag_counter
        wr_ack_int <= wr_req_d0;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, status_wrongWvalue_i, status_wrongHTvalue_i,
           status_wrongBvalue_i, status_startReady_i, status_missReady_i,
           status_missValid_i, status_missIdle_i, status_running_i,
           status_idle_i, status_started_i, flags_forceValidOffline_reg,
           flags_StartAsStop_reg, control_vtuReset_reg, configOffline_valid_i,
           configOffline_htSwitchingEnable_reg, configOffline_mode_reg,
           bValueOffline_reg, htValueOffline_reg, wValueOffline_reg,
           configOnline_htSwitchingEnable_i, configOnline_mode_i,
           bValueOnline_i, htValueOnline_i, wValueOnline_i, trigOHCDelay_set_reg,
           trigODelay_delay_reg, TS_FirstTrigTAIsec_i, TS_FirstTrigTAIcycles_i,
           TS_LastTrigTAIsec_i, TS_LastTrigTAIcycles_i,
           trigdiag_control_window_reg, trigdiag_control_enable_reg,
           trigdiag_generation_i, trigdiag_freq_i, trigdiag_counter_i) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case adr_int(6 downto 3) is
    when "0000" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg status
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= '0';
        rd_dat_d0(1) <= status_wrongWvalue_i;
        rd_dat_d0(2) <= status_wrongHTvalue_i;
        rd_dat_d0(3) <= status_wrongBvalue_i;
        rd_dat_d0(4) <= status_startReady_i;
        rd_dat_d0(7 downto 5) <= (others => '0');
        rd_dat_d0(8) <= status_missReady_i;
        rd_dat_d0(9) <= status_missValid_i;
        rd_dat_d0(10) <= status_missIdle_i;
        rd_dat_d0(11) <= '0';
        rd_dat_d0(12) <= status_running_i;
        rd_dat_d0(13) <= status_idle_i;
        rd_dat_d0(14) <= status_started_i;
        rd_dat_d0(15) <= '0';
      when "01" =>
        -- Reg flags
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= flags_forceValidOffline_reg;
        rd_dat_d0(1) <= flags_StartAsStop_reg;
        rd_dat_d0(15 downto 2) <= (others => '0');
      when "10" =>
        -- Reg control
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= '0';
        rd_dat_d0(1) <= '0';
        rd_dat_d0(2) <= control_vtuReset_reg;
        rd_dat_d0(15 downto 3) <= (others => '0');
      when "11" =>
        -- Reg configOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= configOffline_valid_i;
        rd_dat_d0(1) <= configOffline_htSwitchingEnable_reg;
        rd_dat_d0(3 downto 2) <= (others => '0');
        rd_dat_d0(6 downto 4) <= configOffline_mode_reg;
        rd_dat_d0(15 downto 7) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0001" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg bValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOffline_reg(63 downto 48);
      when "01" =>
        -- Reg bValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOffline_reg(47 downto 32);
      when "10" =>
        -- Reg bValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOffline_reg(31 downto 16);
      when "11" =>
        -- Reg bValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOffline_reg(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0010" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg htValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOffline_reg(63 downto 48);
      when "01" =>
        -- Reg htValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOffline_reg(47 downto 32);
      when "10" =>
        -- Reg htValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOffline_reg(31 downto 16);
      when "11" =>
        -- Reg htValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOffline_reg(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0011" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg wValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOffline_reg(63 downto 48);
      when "01" =>
        -- Reg wValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOffline_reg(47 downto 32);
      when "10" =>
        -- Reg wValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOffline_reg(31 downto 16);
      when "11" =>
        -- Reg wValueOffline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOffline_reg(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0100" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg configOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= '0';
        rd_dat_d0(1) <= configOnline_htSwitchingEnable_i;
        rd_dat_d0(3 downto 2) <= (others => '0');
        rd_dat_d0(6 downto 4) <= configOnline_mode_i;
        rd_dat_d0(15 downto 7) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0101" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg bValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOnline_i(63 downto 48);
      when "01" =>
        -- Reg bValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOnline_i(47 downto 32);
      when "10" =>
        -- Reg bValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOnline_i(31 downto 16);
      when "11" =>
        -- Reg bValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= bValueOnline_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0110" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg htValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOnline_i(63 downto 48);
      when "01" =>
        -- Reg htValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOnline_i(47 downto 32);
      when "10" =>
        -- Reg htValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOnline_i(31 downto 16);
      when "11" =>
        -- Reg htValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= htValueOnline_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "0111" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg wValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOnline_i(63 downto 48);
      when "01" =>
        -- Reg wValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOnline_i(47 downto 32);
      when "10" =>
        -- Reg wValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOnline_i(31 downto 16);
      when "11" =>
        -- Reg wValueOnline
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= wValueOnline_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1000" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg trigOHCDelay
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= trigOHCDelay_set_reg;
        rd_dat_d0(15 downto 1) <= (others => '0');
      when "01" =>
        -- Reg trigODelay
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(4 downto 0) <= trigODelay_delay_reg;
        rd_dat_d0(15 downto 5) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1001" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg TS_FirstTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_FirstTrigTAIsec_i(63 downto 48);
      when "01" =>
        -- Reg TS_FirstTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_FirstTrigTAIsec_i(47 downto 32);
      when "10" =>
        -- Reg TS_FirstTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_FirstTrigTAIsec_i(31 downto 16);
      when "11" =>
        -- Reg TS_FirstTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_FirstTrigTAIsec_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1010" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg TS_FirstTrigTAIcycles
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_FirstTrigTAIcycles_i(31 downto 16);
      when "01" =>
        -- Reg TS_FirstTrigTAIcycles
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_FirstTrigTAIcycles_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1011" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg TS_LastTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_LastTrigTAIsec_i(63 downto 48);
      when "01" =>
        -- Reg TS_LastTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_LastTrigTAIsec_i(47 downto 32);
      when "10" =>
        -- Reg TS_LastTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_LastTrigTAIsec_i(31 downto 16);
      when "11" =>
        -- Reg TS_LastTrigTAIsec
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_LastTrigTAIsec_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1100" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg TS_LastTrigTAIcycles
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_LastTrigTAIcycles_i(31 downto 16);
      when "01" =>
        -- Reg TS_LastTrigTAIcycles
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= TS_LastTrigTAIcycles_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1110" =>
      case adr_int(2 downto 2) is
      when "0" =>
        case adr_int(1 downto 1) is
        when "0" =>
          -- Reg trigdiag_control
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(2 downto 0) <= trigdiag_control_window_reg;
          rd_dat_d0(3) <= '0';
          rd_dat_d0(4) <= trigdiag_control_enable_reg;
          rd_dat_d0(15 downto 5) <= (others => '0');
        when "1" =>
          -- Reg trigdiag_generation
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= trigdiag_generation_i;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "1" =>
        case adr_int(1 downto 1) is
        when "0" =>
          -- Reg trigdiag_freq
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= trigdiag_freq_i(31 downto 16);
        when "1" =>
          -- Reg trigdiag_freq
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= trigdiag_freq_i(15 downto 0);
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1111" =>
      case adr_int(2 downto 1) is
      when "00" =>
        -- Reg trigdiag_counter
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= trigdiag_counter_i(31 downto 16);
      when "01" =>
        -- Reg trigdiag_counter
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= trigdiag_counter_i(15 downto 0);
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
