//  VCO input is 1Ghz OSC
//  REF input is 100Mhz OCXO
//
//  PECL3 (CLK_GTX_125M): 125Mhz
//  PECL2 (CLK_WR_FP): 125Mhz (among 500Mhz/250Mhz/125Mhz/62.5Mhz)
//  PECL1 (CLK_DDS): 1Ghz
//  PECL0 (CLK_IQDAC): 250Mhz
//  LVCM  (CLK_FPGA): 250Mhz
//
// this is the default bootstrap config for LTC6950:
// R divider = 1
// N divider = 10
// LV/CM output: LVDS

// SYNC => N/A (we don't use the sync feature).
// LKEN => 1 (we are interested in lock status).
// LKWIN, LKCT ?
// FILTV, FILTR ?


//  See register map p42

// REG, VAL
//{0x00, 0x00}, // RO (status)
{0x01, 0x33},   // STAT1 config: set on any error (no_vco, no_ref, thi, tlo)
{0x02, 0x04},   // STAT2 config: set when locked
{0x03, 0x08},   // PowerDown, LKEN=1
{0x04, 0x00},   // PowerDown
{0x05, 0x3b},   // ChargePump current = 11.2 mA, LKWIN = 0, LKCT = 3
{0x06, 0xc0},   // ChargePump clamp
{0x07, 0x00},   // Reset_R + R[9:8]
{0x08, 0x01},   // R[7:0] = 1
{0x09, 0x00},   // Reset_N + N[10:8]
{0x0a, 0x0a},   // N[7:0] = 10
{0x0b, 0xc4},   // disable FILTR for 100 MHz, LVCMS=1, SYNCMD=standalone
{0x0c, 0x80},   // DEL0 = 0, No sync, No filter
{0x0d, 0x84},   // M0 = 4
{0x0e, 0x80},   // DEL1
{0x0f, 0x81},   // M1 = 1
{0x10, 0x80},   // DEL2
{0x11, 0x88},   // M2 = 8
{0x12, 0x80},   // DEL3
{0x13, 0x88},   // M3 = 8
{0x14, 0x80},   // DEL4
{0x15, 0x10}    // M4 = 16, RDIVOUT = 0
