#ifndef __CHEBY__TRIGUNIT_REGS__H__
#define __CHEBY__TRIGUNIT_REGS__H__

#include "vtudiag_regs.h"
#define TRIGUNIT_REGS_SIZE 128 /* 0x80 */

/* VTU status */
#define TRIGUNIT_REGS_STATUS 0x0UL
#define TRIGUNIT_REGS_STATUS_STARTED 0x4000UL
#define TRIGUNIT_REGS_STATUS_IDLE 0x2000UL
#define TRIGUNIT_REGS_STATUS_RUNNING 0x1000UL
#define TRIGUNIT_REGS_STATUS_MISSIDLE 0x400UL
#define TRIGUNIT_REGS_STATUS_MISSVALID 0x200UL
#define TRIGUNIT_REGS_STATUS_MISSREADY 0x100UL
#define TRIGUNIT_REGS_STATUS_STARTREADY 0x10UL
#define TRIGUNIT_REGS_STATUS_WRONGBVALUE 0x8UL
#define TRIGUNIT_REGS_STATUS_WRONGHTVALUE 0x4UL
#define TRIGUNIT_REGS_STATUS_WRONGWVALUE 0x2UL

/* Behaviour flags */
#define TRIGUNIT_REGS_FLAGS 0x2UL
#define TRIGUNIT_REGS_FLAGS_FORCEVALIDOFFLINE 0x1UL
#define TRIGUNIT_REGS_FLAGS_STARTASSTOP 0x2UL

/* Control signals */
#define TRIGUNIT_REGS_CONTROL 0x4UL
#define TRIGUNIT_REGS_CONTROL_VTURESET 0x4UL
#define TRIGUNIT_REGS_CONTROL_STOPSOFTTRIGGER 0x2UL
#define TRIGUNIT_REGS_CONTROL_STARTSOFTTRIGGER 0x1UL

/* The offline registers defines the values for the next start.
 */
#define TRIGUNIT_REGS_CONFIGOFFLINE 0x6UL
#define TRIGUNIT_REGS_CONFIGOFFLINE_MODE_MASK 0x70UL
#define TRIGUNIT_REGS_CONFIGOFFLINE_MODE_SHIFT 4
#define TRIGUNIT_REGS_CONFIGOFFLINE_HTSWITCHINGENABLE 0x2UL
#define TRIGUNIT_REGS_CONFIGOFFLINE_VALID 0x1UL

/* Used in all modes.  The exact number of cycles depend on the mode, as there is additional constant delay.
 */
#define TRIGUNIT_REGS_BVALUEOFFLINE 0x8UL

/* Number of RF clock cycles to delay (HT) */
#define TRIGUNIT_REGS_HTVALUEOFFLINE 0x10UL

/* Window value: number of output pulses (W) */
#define TRIGUNIT_REGS_WVALUEOFFLINE 0x18UL

/* Control signals */
#define TRIGUNIT_REGS_CONFIGONLINE 0x20UL
#define TRIGUNIT_REGS_CONFIGONLINE_MODE_MASK 0x70UL
#define TRIGUNIT_REGS_CONFIGONLINE_MODE_SHIFT 4
#define TRIGUNIT_REGS_CONFIGONLINE_HTSWITCHINGENABLE 0x2UL

/* Number of RF clock cycles to delay (B) */
#define TRIGUNIT_REGS_BVALUEONLINE 0x28UL

/* Number of RF clock cycles to delay (HT) */
#define TRIGUNIT_REGS_HTVALUEONLINE 0x30UL

/* Window value: number of output pulses (W) */
#define TRIGUNIT_REGS_WVALUEONLINE 0x38UL

/* Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay */
#define TRIGUNIT_REGS_TRIGOHCDELAY 0x40UL
#define TRIGUNIT_REGS_TRIGOHCDELAY_SET 0x1UL

/* Delay on the trigger output */
#define TRIGUNIT_REGS_TRIGODELAY 0x42UL
#define TRIGUNIT_REGS_TRIGODELAY_DELAY_MASK 0x1fUL
#define TRIGUNIT_REGS_TRIGODELAY_DELAY_SHIFT 0

/* Timestamp TAI seconds of the first VTU output trigger after a start pulse */
#define TRIGUNIT_REGS_TS_FIRSTTRIGTAISEC 0x48UL

/* Timestamp TAI cycles of the first VTU output trigger after a start pulse */
#define TRIGUNIT_REGS_TS_FIRSTTRIGTAICYCLES 0x50UL

/* Timestamp TAI seconds of the last VTU output trigger */
#define TRIGUNIT_REGS_TS_LASTTRIGTAISEC 0x58UL

/* Timestamp TAI cycles of the last VTU output trigger */
#define TRIGUNIT_REGS_TS_LASTTRIGTAICYCLES 0x60UL

/* None */
#define TRIGUNIT_REGS_TRIGDIAG 0x70UL
#define ADDR_MASK_TRIGUNIT_REGS_TRIGDIAG 0x70UL
#define TRIGUNIT_REGS_TRIGDIAG_SIZE 16 /* 0x10 */

#ifndef __ASSEMBLER__
struct trigunit_regs {
  /* [0x0]: REG (ro) VTU status */
  uint16_t status;

  /* [0x2]: REG (rw) Behaviour flags */
  uint16_t flags;

  /* [0x4]: REG (rw) Control signals */
  uint16_t control;

  /* [0x6]: REG (rw) The offline registers defines the values for the next start.
 */
  uint16_t configOffline;

  /* [0x8]: REG (rw) Used in all modes.  The exact number of cycles depend on the mode, as there is additional constant delay.
 */
  uint64_t bValueOffline;

  /* [0x10]: REG (rw) Number of RF clock cycles to delay (HT) */
  uint64_t htValueOffline;

  /* [0x18]: REG (rw) Window value: number of output pulses (W) */
  uint64_t wValueOffline;

  /* [0x20]: REG (ro) Control signals */
  uint16_t configOnline;

  /* padding to: 40 words */
  uint8_t __padding_0[6];

  /* [0x28]: REG (ro) Number of RF clock cycles to delay (B) */
  uint64_t bValueOnline;

  /* [0x30]: REG (ro) Number of RF clock cycles to delay (HT) */
  uint64_t htValueOnline;

  /* [0x38]: REG (ro) Window value: number of output pulses (W) */
  uint64_t wValueOnline;

  /* [0x40]: REG (rw) Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay */
  uint16_t trigOHCDelay;

  /* [0x42]: REG (rw) Delay on the trigger output */
  uint16_t trigODelay;

  /* padding to: 18 words */
  uint32_t __padding_1[1];

  /* [0x48]: REG (ro) Timestamp TAI seconds of the first VTU output trigger after a start pulse */
  uint64_t TS_FirstTrigTAIsec;

  /* [0x50]: REG (ro) Timestamp TAI cycles of the first VTU output trigger after a start pulse */
  uint32_t TS_FirstTrigTAIcycles;

  /* padding to: 22 words */
  uint32_t __padding_2[1];

  /* [0x58]: REG (ro) Timestamp TAI seconds of the last VTU output trigger */
  uint64_t TS_LastTrigTAIsec;

  /* [0x60]: REG (ro) Timestamp TAI cycles of the last VTU output trigger */
  uint32_t TS_LastTrigTAIcycles;

  /* padding to: 28 words */
  uint32_t __padding_3[3];

  /* [0x70]: SUBMAP (no description) */
  struct vtudiag_regs trigdiag;
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__TRIGUNIT_REGS__H__ */
