#ifndef __CHEBY__OC_SPI16_REGS__H__
#define __CHEBY__OC_SPI16_REGS__H__
#define OC_SPI16_REGS_SIZE 26 /* 0x1a */

/* None */
#define OC_SPI16_REGS_RXTX0 0x0UL

/* None */
#define OC_SPI16_REGS_RXTX1 0x2UL

/* None */
#define OC_SPI16_REGS_RXTX2 0x4UL

/* None */
#define OC_SPI16_REGS_RXTX3 0x6UL

/* None */
#define OC_SPI16_REGS_RXTX4 0x8UL

/* None */
#define OC_SPI16_REGS_RXTX5 0xaUL

/* None */
#define OC_SPI16_REGS_RXTX6 0xcUL

/* None */
#define OC_SPI16_REGS_RXTX7 0xeUL

/* None */
#define OC_SPI16_REGS_CTRL 0x10UL

/* None */
#define OC_SPI16_REGS_DIVIDER 0x14UL

/* None */
#define OC_SPI16_REGS_SS 0x18UL

#ifndef __ASSEMBLER__
struct oc_spi16_regs {
  /* [0x0]: REG (rw) (no description) */
  uint16_t rxtx0;

  /* [0x2]: REG (rw) (no description) */
  uint16_t rxtx1;

  /* [0x4]: REG (rw) (no description) */
  uint16_t rxtx2;

  /* [0x6]: REG (rw) (no description) */
  uint16_t rxtx3;

  /* [0x8]: REG (rw) (no description) */
  uint16_t rxtx4;

  /* [0xa]: REG (rw) (no description) */
  uint16_t rxtx5;

  /* [0xc]: REG (rw) (no description) */
  uint16_t rxtx6;

  /* [0xe]: REG (rw) (no description) */
  uint16_t rxtx7;

  /* [0x10]: REG (rw) (no description) */
  uint16_t ctrl;

  /* padding to: 20 words */
  uint8_t __padding_0[2];

  /* [0x14]: REG (rw) (no description) */
  uint16_t divider;

  /* padding to: 24 words */
  uint8_t __padding_1[2];

  /* [0x18]: REG (rw) (no description) */
  uint16_t ss;
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__OC_SPI16_REGS__H__ */
