#ifndef __CHEBY__WR2RF_INIT_REGS__H__
#define __CHEBY__WR2RF_INIT_REGS__H__

#include "hwInfo.h"
#include "oc_spi16_regs.h"
#include "wr2rf_init_rf_regs.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */

/* RF indentification */
#define WR2RF_INIT_REGS_HWINFO 0x0UL
#define ADDR_MASK_WR2RF_INIT_REGS_HWINFO 0x3f00UL
#define WR2RF_INIT_REGS_HWINFO_SIZE 256 /* 0x100 */

/* Firmware update (FAR) */
#define WR2RF_INIT_REGS_FW_UPDATE 0x100UL
#define ADDR_MASK_WR2RF_INIT_REGS_FW_UPDATE 0x3ffeUL
#define WR2RF_INIT_REGS_FW_UPDATE_SIZE 2 /* 0x2 */

/* FPGA reconfiguration */
#define WR2RF_INIT_REGS_RECONFIGURE 0x102UL

/* Control register for the system clock */
#define WR2RF_INIT_REGS_CLOCK_CTRL 0x104UL
#define WR2RF_INIT_REGS_CLOCK_CTRL_CLK_SEL 0x1UL
#define WR2RF_INIT_REGS_CLOCK_CTRL_MMCM_RESET 0x2UL

/* Control register for wrcore */
#define WR2RF_INIT_REGS_WRCORE_CTRL 0x106UL
#define WR2RF_INIT_REGS_WRCORE_CTRL_RESET_N 0x1UL

/* Control register for iodelayctrl */
#define WR2RF_INIT_REGS_IODELAY_CTRL 0x108UL
#define WR2RF_INIT_REGS_IODELAY_CTRL_RESET 0x1UL

/* Adjust the mmcm shift for the 10Mhz external clock */
#define WR2RF_INIT_REGS_MMCM_SHIFT 0x10aUL
#define WR2RF_INIT_REGS_MMCM_SHIFT_INCDEC 0x1UL

/* Status register for system clock */
#define WR2RF_INIT_REGS_CLOCK_STATUS 0x10cUL
#define WR2RF_INIT_REGS_CLOCK_STATUS_MMCM_LOCKED 0x1UL
#define WR2RF_INIT_REGS_CLOCK_STATUS_SHIFT_BUSY 0x2UL

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_TMG 0x10eUL
#define WR2RF_INIT_REGS_TMG_IO_TERM_MASK 0xfUL
#define WR2RF_INIT_REGS_TMG_IO_TERM_SHIFT 0
#define WR2RF_INIT_REGS_TMG_IO_OE_MASK 0xf0UL
#define WR2RF_INIT_REGS_TMG_IO_OE_SHIFT 4
#define WR2RF_INIT_REGS_TMG_CLK_TERM_MASK 0x300UL
#define WR2RF_INIT_REGS_TMG_CLK_TERM_SHIFT 8
#define WR2RF_INIT_REGS_TMG_CLK_OE_MASK 0xc00UL
#define WR2RF_INIT_REGS_TMG_CLK_OE_SHIFT 10

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF1_T1_START 0x110UL
#define WR2RF_INIT_REGS_LEMO_RF1_T1_START_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF1_T1_START_SEL_SHIFT 1

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF1_T2_START 0x112UL
#define WR2RF_INIT_REGS_LEMO_RF1_T2_START_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF1_T2_START_SEL_SHIFT 1

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF2_T1_START 0x114UL
#define WR2RF_INIT_REGS_LEMO_RF2_T1_START_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF2_T1_START_SEL_SHIFT 1

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF2_T2_START 0x116UL
#define WR2RF_INIT_REGS_LEMO_RF2_T2_START_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF2_T2_START_SEL_SHIFT 1

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF1_T1_STOP 0x118UL
#define WR2RF_INIT_REGS_LEMO_RF1_T1_STOP_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF1_T1_STOP_SEL_SHIFT 1

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF1_T2_STOP 0x11aUL
#define WR2RF_INIT_REGS_LEMO_RF1_T2_STOP_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF1_T2_STOP_SEL_SHIFT 1

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_LEMO_RF2_T1_STOP 0x11cUL
#define WR2RF_INIT_REGS_LEMO_RF2_T1_STOP_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF2_T1_STOP_SEL_SHIFT 1

/* lemos */
#define WR2RF_INIT_REGS_LEMO_RF2_T2_STOP 0x11eUL
#define WR2RF_INIT_REGS_LEMO_RF2_T2_STOP_SEL_MASK 0x7eUL
#define WR2RF_INIT_REGS_LEMO_RF2_T2_STOP_SEL_SHIFT 1

/* lemo debug selection */
#define WR2RF_INIT_REGS_TMGIO1 0x120UL
#define WR2RF_INIT_REGS_TMGIO1_OSEL_MASK 0x3fffUL
#define WR2RF_INIT_REGS_TMGIO1_OSEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_TMGIO2 0x122UL
#define WR2RF_INIT_REGS_TMGIO2_OSEL_MASK 0x3fffUL
#define WR2RF_INIT_REGS_TMGIO2_OSEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_TMGIO3 0x124UL
#define WR2RF_INIT_REGS_TMGIO3_OSEL_MASK 0x3fffUL
#define WR2RF_INIT_REGS_TMGIO3_OSEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_TMGIO4 0x126UL
#define WR2RF_INIT_REGS_TMGIO4_OSEL_MASK 0x3fffUL
#define WR2RF_INIT_REGS_TMGIO4_OSEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_TMGCLK1 0x128UL
#define WR2RF_INIT_REGS_TMGCLK1_OSEL_MASK 0x3fffUL
#define WR2RF_INIT_REGS_TMGCLK1_OSEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_TMGCLK2 0x12aUL
#define WR2RF_INIT_REGS_TMGCLK2_OSEL_MASK 0x3fffUL
#define WR2RF_INIT_REGS_TMGCLK2_OSEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_LEMO 0x12cUL
#define WR2RF_INIT_REGS_LEMO_GPIO_MASK 0x3UL
#define WR2RF_INIT_REGS_LEMO_GPIO_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_LEMO_EXT 0x12eUL
#define WR2RF_INIT_REGS_LEMO_EXT_SEL_MASK 0x3fUL
#define WR2RF_INIT_REGS_LEMO_EXT_SEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_SOFTSTART 0x130UL
#define WR2RF_INIT_REGS_SOFTSTART_SEL_MASK 0xfUL
#define WR2RF_INIT_REGS_SOFTSTART_SEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_SOFTSTOP 0x132UL
#define WR2RF_INIT_REGS_SOFTSTOP_SEL_MASK 0xfUL
#define WR2RF_INIT_REGS_SOFTSTOP_SEL_SHIFT 0

/* lemo debug selection */
#define WR2RF_INIT_REGS_LEMO_PULSE 0x134UL
#define WR2RF_INIT_REGS_LEMO_PULSE_EXT_MASK 0x3fUL
#define WR2RF_INIT_REGS_LEMO_PULSE_EXT_SHIFT 0

/* timing io grouping of signals */
#define WR2RF_INIT_REGS_PIN_CTRL 0x136UL
#define WR2RF_INIT_REGS_PIN_CTRL_EXT_10M_DIR 0x1UL
#define WR2RF_INIT_REGS_PIN_CTRL_EXT_PPS_DIR 0x2UL

/* Status lines from the main PLL (LTC6950) */
#define WR2RF_INIT_REGS_PLL_STATUS 0x138UL
#define WR2RF_INIT_REGS_PLL_STATUS_ERROR 0x1UL
#define WR2RF_INIT_REGS_PLL_STATUS_LOCKED 0x2UL

/* Ctrl lines to the main PLL (LTC6950) */
#define WR2RF_INIT_REGS_PLL_CTRL 0x13aUL
#define WR2RF_INIT_REGS_PLL_CTRL_SYNC 0x1UL

/* dds (AD9910) control signals */
#define WR2RF_INIT_REGS_DDS_CTRL 0x13cUL
#define WR2RF_INIT_REGS_DDS_CTRL_RESET 0x1UL
#define WR2RF_INIT_REGS_DDS_CTRL_IOUPDATE 0x8UL
#define WR2RF_INIT_REGS_DDS_CTRL_PROFILE_MASK 0x70UL
#define WR2RF_INIT_REGS_DDS_CTRL_PROFILE_SHIFT 4

/* dds (AD9910) control signals */
#define WR2RF_INIT_REGS_DDS_IOUPDATE 0x13eUL
#define WR2RF_INIT_REGS_DDS_IOUPDATE_FDELAY_MASK 0xfUL
#define WR2RF_INIT_REGS_DDS_IOUPDATE_FDELAY_SHIFT 0
#define WR2RF_INIT_REGS_DDS_IOUPDATE_ODELAY_MASK 0x1f0UL
#define WR2RF_INIT_REGS_DDS_IOUPDATE_ODELAY_SHIFT 4

/* dds (AD9910) status signals */
#define WR2RF_INIT_REGS_DDS_STATUS 0x140UL
#define WR2RF_INIT_REGS_DDS_STATUS_SYNC_ERROR 0x1UL

/* ocxo configuration */
#define WR2RF_INIT_REGS_OCXO 0x144UL
#define WR2RF_INIT_REGS_OCXO_SIZE 4 /* 0x4 */

/* Enable the OCXO */
#define WR2RF_INIT_REGS_OCXO_CTRL 0x144UL
#define WR2RF_INIT_REGS_OCXO_CTRL_ENABLE 0x1UL

/* Records how long the ocxo has been enabled */
#define WR2RF_INIT_REGS_OCXO_UPTIME 0x146UL
#define WR2RF_INIT_REGS_OCXO_UPTIME_VAL_MASK 0xffffUL
#define WR2RF_INIT_REGS_OCXO_UPTIME_VAL_SHIFT 0

/* NCO control */
#define WR2RF_INIT_REGS_NCO 0x180UL
#define WR2RF_INIT_REGS_NCO_SIZE 64 /* 0x40 */

/* Adjust NCO output for azimuthal position */
#define WR2RF_INIT_REGS_NCO_AZIMUTHAL 0x180UL
#define WR2RF_INIT_REGS_NCO_AZIMUTHAL_VALUE_MASK 0xffffffffffffULL
#define WR2RF_INIT_REGS_NCO_AZIMUTHAL_VALUE_SHIFT 0

/* Adjust NCO output for cable delays */
#define WR2RF_INIT_REGS_NCO_CABLEDELAY 0x188UL
#define WR2RF_INIT_REGS_NCO_CABLEDELAY_VALUE_MASK 0xffffffffffffULL
#define WR2RF_INIT_REGS_NCO_CABLEDELAY_VALUE_SHIFT 0

/* harmonic factor */
#define WR2RF_INIT_REGS_NCO_HB 0x190UL
#define WR2RF_INIT_REGS_NCO_HB_VALUE_MASK 0x3ffUL
#define WR2RF_INIT_REGS_NCO_HB_VALUE_SHIFT 0

/* Adjust NCO increment per clock cycle */
#define WR2RF_INIT_REGS_NCO_H1_FTW 0x198UL
#define WR2RF_INIT_REGS_NCO_H1_FTW_VALUE_MASK 0xffffffffffffULL
#define WR2RF_INIT_REGS_NCO_H1_FTW_VALUE_SHIFT 0

/* Adjust NCO starting phase */
#define WR2RF_INIT_REGS_NCO_H1_PROG 0x1a0UL
#define WR2RF_INIT_REGS_NCO_H1_PROG_VALUE_MASK 0xffffffffffffULL
#define WR2RF_INIT_REGS_NCO_H1_PROG_VALUE_SHIFT 0

/* control */
#define WR2RF_INIT_REGS_NCO_CTRL 0x1a8UL
#define WR2RF_INIT_REGS_NCO_CTRL_RESET_NCO 0x1UL
#define WR2RF_INIT_REGS_NCO_CTRL_RESET_SLIP 0x2UL
#define WR2RF_INIT_REGS_NCO_CTRL_RESET_FSK 0x4UL
#define WR2RF_INIT_REGS_NCO_CTRL_RATE_MASK 0x70UL
#define WR2RF_INIT_REGS_NCO_CTRL_RATE_SHIFT 4

/* Used to signal that all parameters are valid and ready for use */
#define WR2RF_INIT_REGS_NCO_UPDATE 0x1aaUL
#define WR2RF_INIT_REGS_NCO_UPDATE_VALID 0x1UL

/* Used to determine if local registers (=1) or WRStreamer (=0) parameters are selected */
#define WR2RF_INIT_REGS_NCO_LOC_OR_WRS 0x1acUL
#define WR2RF_INIT_REGS_NCO_LOC_OR_WRS_PARAMS_SEL 0x1UL

/* SVEC mockup board registers */
#define WR2RF_INIT_REGS_SVEC_MUP 0x1c0UL
#define WR2RF_INIT_REGS_SVEC_MUP_SIZE 8 /* 0x8 */

/* Front panel select */
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL 0x1c0UL
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL_GPIO_SEL_MASK 0xfUL
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL_GPIO_SEL_SHIFT 0
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL_LED_SEL_MASK 0xf0UL
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL_LED_SEL_SHIFT 4
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL_BCLK_RFCLK_SEL 0x100UL
#define WR2RF_INIT_REGS_SVEC_MUP_CTRL_ILA_SEL 0x200UL

/* rf trigger mockup */
#define WR2RF_INIT_REGS_SVEC_MUP_RFTRIG 0x1c2UL
#define WR2RF_INIT_REGS_SVEC_MUP_RFTRIG_T1STOP 0x1UL
#define WR2RF_INIT_REGS_SVEC_MUP_RFTRIG_T1START 0x2UL
#define WR2RF_INIT_REGS_SVEC_MUP_RFTRIG_T2STOP 0x4UL
#define WR2RF_INIT_REGS_SVEC_MUP_RFTRIG_T2START 0x8UL

/* fmc dio */
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1 0x1c4UL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1_TERM_MASK 0x1fUL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1_TERM_SHIFT 0
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1_OE_N_MASK 0x3e0UL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1_OE_N_SHIFT 5
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1_LED_MASK 0xc00UL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC1_LED_SHIFT 10

/* fmc dio */
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2 0x1c6UL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_TERM_MASK 0x1fUL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_TERM_SHIFT 0
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_OE_N_MASK 0x3e0UL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_OE_N_SHIFT 5
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_LED_MASK 0xc00UL
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_LED_SHIFT 10

/* Last rx frame from WR */
#define WR2RF_INIT_REGS_WRS_RXFRAME 0x200UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_SIZE 64 /* 0x40 */

/* Last FTW received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW 0x200UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW_VALUE_MASK 0xffffffffffffULL
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW_VALUE_SHIFT 0

/* Last Control received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_CTRL 0x208UL

/* Number of RFFrameTransceiver frames received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_COUNTER 0x20aUL

/* Timestamp when the last frame was received from wr streamers */
#define WR2RF_INIT_REGS_WRS_RXFRAME_RXWRTIMESTAMP 0x20cUL

/* Timestamp when the last frame was transmitted from wr streamers */
#define WR2RF_INIT_REGS_WRS_RXFRAME_TXWRTIMESTAMP 0x210UL

/* Timestamp when the last frame was received from RFFrameTransceiver */
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFTIMESTAMP 0x214UL

/* Update the RF frame timestamps for readout */
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFFRAME_TS 0x218UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFFRAME_TS_UPDATE 0x1UL

/* Timestamp TAI for the last RFframe received that asserted nco_reset */
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI 0x220UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI_VAL_MASK 0xffffffffffULL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI_VAL_SHIFT 0

/* Timestamp TAI for the last RFframe received that asserted nco_reset */
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES 0x228UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES_VAL_MASK 0xfffffffUL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES_VAL_SHIFT 0

/* Timestamp TAI for the last RFframe received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_TAI 0x230UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_TAI_VAL_MASK 0xffffffffffULL
#define WR2RF_INIT_REGS_WRS_RXFRAME_TAI_VAL_SHIFT 0

/* Timestamp TAI for the last RFframe received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES 0x238UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES_VAL_MASK 0xfffffffUL
#define WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES_VAL_SHIFT 0

/* WR status and time */
#define WR2RF_INIT_REGS_WRC 0x240UL
#define WR2RF_INIT_REGS_WRC_SIZE 32 /* 0x20 */

/* Absolute time (in sec) */
#define WR2RF_INIT_REGS_WRC_TAI 0x240UL
#define WR2RF_INIT_REGS_WRC_TAI_VALUE_MASK 0xffffffffffULL
#define WR2RF_INIT_REGS_WRC_TAI_VALUE_SHIFT 0

/* Number of cycles */
#define WR2RF_INIT_REGS_WRC_CYCLES 0x248UL
#define WR2RF_INIT_REGS_WRC_CYCLES_VALUE_MASK 0xfffffffUL
#define WR2RF_INIT_REGS_WRC_CYCLES_VALUE_SHIFT 0

/* WR status */
#define WR2RF_INIT_REGS_WRC_STATUS 0x24cUL
#define WR2RF_INIT_REGS_WRC_STATUS_LINKUP 0x1UL
#define WR2RF_INIT_REGS_WRC_STATUS_TIME_VALID 0x2UL

/* Page 0 offset */
#define WR2RF_INIT_REGS_WRC_PAGE0 0x250UL
#define WR2RF_INIT_REGS_WRC_PAGE0_PRESET 0x40000UL

/* Page 1 offset */
#define WR2RF_INIT_REGS_WRC_PAGE1 0x254UL

/* Frame to be sent over WR (for testing purposes) */
#define WR2RF_INIT_REGS_TXFRAME 0x280UL
#define WR2RF_INIT_REGS_TXFRAME_SIZE 128 /* 0x80 */

/* None */
#define WR2RF_INIT_REGS_TXFRAME_FTW_H1_MAIN 0x280UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_FTW_H1_PROG 0x288UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_FTW_H1_ON 0x290UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_DFTW_H1_SLIP1 0x298UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_DFTW_H1_SLIP2 0x29cUL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT1 0x2a0UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT2 0x2a4UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT3 0x2a8UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT4 0x2acUL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT5 0x2b0UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT6 0x2b4UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT7 0x2b8UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_SETPOINT8 0x2bcUL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_NOISE 0x2c0UL

/* None */
#define WR2RF_INIT_REGS_TXFRAME_CONTROL 0x2c4UL

/* SPI master for the main PLL (LTC6950) */
#define WR2RF_INIT_REGS_PLL_SPI 0x300UL
#define ADDR_MASK_WR2RF_INIT_REGS_PLL_SPI 0x3fe0UL
#define WR2RF_INIT_REGS_PLL_SPI_SIZE 32 /* 0x20 */

/* SPI master for RF chips.
cs0: DDS
cs1: IQ DAC 1
cs2: IQ DAC 2
 */
#define WR2RF_INIT_REGS_RF_SPI 0x320UL
#define ADDR_MASK_WR2RF_INIT_REGS_RF_SPI 0x3fe0UL
#define WR2RF_INIT_REGS_RF_SPI_SIZE 32 /* 0x20 */

/* Register for RF components */
#define WR2RF_INIT_REGS_RF 0x340UL
#define ADDR_MASK_WR2RF_INIT_REGS_RF 0x3fc0UL
#define WR2RF_INIT_REGS_RF_SIZE 64 /* 0x40 */

/* RF Frame transceiver */
#define WR2RF_INIT_REGS_FRAMERXTX 0x380UL
#define ADDR_MASK_WR2RF_INIT_REGS_FRAMERXTX 0x3fc0UL
#define WR2RF_INIT_REGS_FRAMERXTX_SIZE 64 /* 0x40 */

/* Xilinx ADC */
#define WR2RF_INIT_REGS_XADC 0x400UL
#define ADDR_MASK_WR2RF_INIT_REGS_XADC 0x3f00UL
#define WR2RF_INIT_REGS_XADC_SIZE 256 /* 0x100 */

/* WR ptp core (peripheral only) */
#define WR2RF_INIT_REGS_WRPC 0x2000UL
#define ADDR_MASK_WR2RF_INIT_REGS_WRPC 0x2000UL
#define WR2RF_INIT_REGS_WRPC_SIZE 8192 /* 0x2000 = 8KB */

#ifndef __ASSEMBLER__
struct wr2rf_init_regs {
  /* [0x0]: SUBMAP RF indentification */
  struct hwInfo hwinfo;

  /* [0x100]: SUBMAP Firmware update (FAR) */
  uint8_t fw_update[2];

  /* [0x102]: REG (wo) FPGA reconfiguration */
  uint16_t reconfigure;

  /* [0x104]: REG (rw) Control register for the system clock */
  uint16_t clock_ctrl;

  /* [0x106]: REG (rw) Control register for wrcore */
  uint16_t wrcore_ctrl;

  /* [0x108]: REG (rw) Control register for iodelayctrl */
  uint16_t iodelay_ctrl;

  /* [0x10a]: REG (wo) Adjust the mmcm shift for the 10Mhz external clock */
  uint16_t mmcm_shift;

  /* [0x10c]: REG (ro) Status register for system clock */
  uint16_t clock_status;

  /* [0x10e]: REG (rw) timing io grouping of signals */
  uint16_t tmg;

  /* [0x110]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf1_t1_start;

  /* [0x112]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf1_t2_start;

  /* [0x114]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf2_t1_start;

  /* [0x116]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf2_t2_start;

  /* [0x118]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf1_t1_stop;

  /* [0x11a]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf1_t2_stop;

  /* [0x11c]: REG (rw) timing io grouping of signals */
  uint16_t lemo_rf2_t1_stop;

  /* [0x11e]: REG (rw) lemos */
  uint16_t lemo_rf2_t2_stop;

  /* [0x120]: REG (rw) lemo debug selection */
  uint16_t tmgio1;

  /* [0x122]: REG (rw) lemo debug selection */
  uint16_t tmgio2;

  /* [0x124]: REG (rw) lemo debug selection */
  uint16_t tmgio3;

  /* [0x126]: REG (rw) lemo debug selection */
  uint16_t tmgio4;

  /* [0x128]: REG (rw) lemo debug selection */
  uint16_t tmgclk1;

  /* [0x12a]: REG (rw) lemo debug selection */
  uint16_t tmgclk2;

  /* [0x12c]: REG (rw) lemo debug selection */
  uint16_t lemo;

  /* [0x12e]: REG (rw) lemo debug selection */
  uint16_t lemo_ext;

  /* [0x130]: REG (rw) lemo debug selection */
  uint16_t softstart;

  /* [0x132]: REG (rw) lemo debug selection */
  uint16_t softstop;

  /* [0x134]: REG (rw) lemo debug selection */
  uint16_t lemo_pulse;

  /* [0x136]: REG (rw) timing io grouping of signals */
  uint16_t pin_ctrl;

  /* [0x138]: REG (ro) Status lines from the main PLL (LTC6950) */
  uint16_t pll_status;

  /* [0x13a]: REG (rw) Ctrl lines to the main PLL (LTC6950) */
  uint16_t pll_ctrl;

  /* [0x13c]: REG (rw) dds (AD9910) control signals */
  uint16_t dds_ctrl;

  /* [0x13e]: REG (rw) dds (AD9910) control signals */
  uint16_t dds_ioupdate;

  /* [0x140]: REG (ro) dds (AD9910) status signals */
  uint16_t dds_status;

  /* padding to: 324 words */
  uint8_t __padding_0[2];

  /* [0x144]: BLOCK ocxo configuration */
  struct ocxo {
    /* [0x0]: REG (rw) Enable the OCXO */
    uint16_t ctrl;

    /* [0x2]: REG (ro) Records how long the ocxo has been enabled */
    uint16_t uptime;
  } ocxo;

  /* padding to: 96 words */
  uint32_t __padding_1[14];

  /* [0x180]: BLOCK NCO control */
  struct nco {
    /* [0x0]: REG (rw) Adjust NCO output for azimuthal position */
    uint64_t azimuthal;

    /* [0x8]: REG (rw) Adjust NCO output for cable delays */
    uint64_t cabledelay;

    /* [0x10]: REG (rw) harmonic factor */
    uint16_t hb;

    /* padding to: 24 words */
    uint8_t __padding_0[6];

    /* [0x18]: REG (rw) Adjust NCO increment per clock cycle */
    uint64_t h1_ftw;

    /* [0x20]: REG (rw) Adjust NCO starting phase */
    uint64_t h1_prog;

    /* [0x28]: REG (rw) control */
    uint16_t ctrl;

    /* [0x2a]: REG (rw) Used to signal that all parameters are valid and ready for use */
    uint16_t update;

    /* [0x2c]: REG (rw) Used to determine if local registers (=1) or WRStreamer (=0) parameters are selected */
    uint16_t loc_or_wrs;

    /* padding to: 44 words */
    uint8_t __padding_1[18];
  } nco;

  /* [0x1c0]: BLOCK SVEC mockup board registers */
  struct svec_mup {
    /* [0x0]: REG (rw) Front panel select */
    uint16_t ctrl;

    /* [0x2]: REG (rw) rf trigger mockup */
    uint16_t rftrig;

    /* [0x4]: REG (rw) fmc dio */
    uint16_t fmc1;

    /* [0x6]: REG (rw) fmc dio */
    uint16_t fmc2;
  } svec_mup;

  /* padding to: 128 words */
  uint32_t __padding_2[14];

  /* [0x200]: BLOCK Last rx frame from WR */
  struct wrs_rxframe {
    /* [0x0]: REG (ro) Last FTW received */
    uint64_t ftw;

    /* [0x8]: REG (ro) Last Control received */
    uint16_t ctrl;

    /* [0xa]: REG (ro) Number of RFFrameTransceiver frames received */
    uint16_t counter;

    /* [0xc]: REG (ro) Timestamp when the last frame was received from wr streamers */
    uint32_t rxwrtimestamp;

    /* [0x10]: REG (ro) Timestamp when the last frame was transmitted from wr streamers */
    uint32_t txwrtimestamp;

    /* [0x14]: REG (ro) Timestamp when the last frame was received from RFFrameTransceiver */
    uint32_t rftimestamp;

    /* [0x18]: REG (rw) Update the RF frame timestamps for readout */
    uint16_t rfframe_ts;

    /* padding to: 32 words */
    uint8_t __padding_0[6];

    /* [0x20]: REG (ro) Timestamp TAI for the last RFframe received that asserted nco_reset */
    uint64_t nco_reset_tai;

    /* [0x28]: REG (ro) Timestamp TAI for the last RFframe received that asserted nco_reset */
    uint32_t nco_reset_cycles;

    /* padding to: 12 words */
    uint32_t __padding_1[1];

    /* [0x30]: REG (ro) Timestamp TAI for the last RFframe received */
    uint64_t tai;

    /* [0x38]: REG (ro) Timestamp TAI for the last RFframe received */
    uint32_t cycles;

    /* padding to: 14 words */
    uint32_t __padding_2[1];
  } wrs_rxframe;

  /* [0x240]: BLOCK WR status and time */
  struct wrc {
    /* [0x0]: REG (ro) Absolute time (in sec) */
    uint64_t tai;

    /* [0x8]: REG (ro) Number of cycles */
    uint32_t cycles;

    /* [0xc]: REG (ro) WR status */
    uint16_t status;

    /* padding to: 16 words */
    uint8_t __padding_0[2];

    /* [0x10]: REG (rw) Page 0 offset */
    uint32_t page0;

    /* [0x14]: REG (rw) Page 1 offset */
    uint32_t page1;

    /* padding to: 5 words */
    uint32_t __padding_1[2];
  } wrc;

  /* padding to: 160 words */
  uint32_t __padding_3[8];

  /* [0x280]: BLOCK Frame to be sent over WR (for testing purposes) */
  struct txframe {
    /* [0x0]: REG (rw) (no description) */
    uint64_t ftw_h1_main;

    /* [0x8]: REG (rw) (no description) */
    uint64_t ftw_h1_prog;

    /* [0x10]: REG (rw) (no description) */
    uint64_t ftw_h1_on;

    /* [0x18]: REG (rw) (no description) */
    uint32_t dftw_h1_slip1;

    /* [0x1c]: REG (rw) (no description) */
    uint32_t dftw_h1_slip2;

    /* [0x20]: REG (rw) (no description) */
    uint32_t setpoint1;

    /* [0x24]: REG (rw) (no description) */
    uint32_t setpoint2;

    /* [0x28]: REG (rw) (no description) */
    uint32_t setpoint3;

    /* [0x2c]: REG (rw) (no description) */
    uint32_t setpoint4;

    /* [0x30]: REG (rw) (no description) */
    uint32_t setpoint5;

    /* [0x34]: REG (rw) (no description) */
    uint32_t setpoint6;

    /* [0x38]: REG (rw) (no description) */
    uint32_t setpoint7;

    /* [0x3c]: REG (rw) (no description) */
    uint32_t setpoint8;

    /* [0x40]: REG (rw) (no description) */
    uint32_t noise;

    /* [0x44]: REG (rw) (no description) */
    uint16_t control;

    /* padding to: 68 words */
    uint8_t __padding_0[58];
  } txframe;

  /* [0x300]: SUBMAP SPI master for the main PLL (LTC6950) */
  struct oc_spi16_regs pll_spi;

  /* padding to: 800 words */
  uint8_t __padding_4[6];

  /* [0x320]: SUBMAP SPI master for RF chips.
cs0: DDS
cs1: IQ DAC 1
cs2: IQ DAC 2
 */
  struct oc_spi16_regs rf_spi;

  /* padding to: 832 words */
  uint8_t __padding_5[6];

  /* [0x340]: SUBMAP Register for RF components */
  struct wr2rf_init_rf_regs rf;

  /* padding to: 224 words */
  uint32_t __padding_6[4];

  /* [0x380]: SUBMAP RF Frame transceiver */
  uint32_t framerxtx[16];

  /* padding to: 256 words */
  uint32_t __padding_7[16];

  /* [0x400]: SUBMAP Xilinx ADC */
  uint32_t xadc[64];

  /* padding to: 2048 words */
  uint32_t __padding_8[1728];

  /* [0x2000]: SUBMAP WR ptp core (peripheral only) */
  uint32_t wrpc[2048];
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__WR2RF_INIT_REGS__H__ */
