#ifndef __CHEBY__WR2RF_CTRL_REGS__H__
#define __CHEBY__WR2RF_CTRL_REGS__H__

#include "wr2rf_rftrigger_regs.h"
#define WR2RF_CTRL_REGS_SIZE 12356 /* 0x3044 */

/* Registers for rf1 vtus */
#define WR2RF_CTRL_REGS_RF1_VTUS 0x0UL
#define ADDR_MASK_WR2RF_CTRL_REGS_RF1_VTUS 0x3e00UL
#define WR2RF_CTRL_REGS_RF1_VTUS_SIZE 512 /* 0x200 */

/* Registers for rf2 vtus */
#define WR2RF_CTRL_REGS_RF2_VTUS 0x200UL
#define ADDR_MASK_WR2RF_CTRL_REGS_RF2_VTUS 0x3e00UL
#define WR2RF_CTRL_REGS_RF2_VTUS_SIZE 512 /* 0x200 */

/* Registers for rf1 rfnco */
#define WR2RF_CTRL_REGS_RF1_RFNCO 0x1000UL
#define ADDR_MASK_WR2RF_CTRL_REGS_RF1_RFNCO 0x3000UL
#define WR2RF_CTRL_REGS_RF1_RFNCO_SIZE 4096 /* 0x1000 = 4KB */

/* Registers for rf2 rfnco */
#define WR2RF_CTRL_REGS_RF2_RFNCO 0x2000UL
#define ADDR_MASK_WR2RF_CTRL_REGS_RF2_RFNCO 0x3000UL
#define WR2RF_CTRL_REGS_RF2_RFNCO_SIZE 4096 /* 0x1000 = 4KB */

/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE 0x3000UL

/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE 0x3002UL

/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE_UPDATE 0x3004UL
#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE_UPDATE_VALID 0x1UL

/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE_UPDATE 0x3006UL
#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE_UPDATE_VALID 0x1UL

/* I ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN_ARM 0x3008UL

/* Q ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN_ARM 0x300aUL

/* I ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN_ARM 0x300cUL

/* Q ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN_ARM 0x300eUL

/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN 0x3010UL

/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN 0x3012UL

/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN 0x3014UL

/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN 0x3016UL

/* Select iqdac I + Q sources */
#define WR2RF_CTRL_REGS_RF1_IQDAC_CTRL 0x3018UL

/* Select iqdac I + Q sources */
#define WR2RF_CTRL_REGS_RF2_IQDAC_CTRL 0x301aUL

/* Select iqdac ram address */
#define WR2RF_CTRL_REGS_IQDAC_RAM_ADDR 0x301cUL

/* iqdac ram data to be written at address iqdac_ram_addr */
#define WR2RF_CTRL_REGS_IQDAC_RAM_DATA 0x301eUL

/* Some magic controls bit tbd */
#define WR2RF_CTRL_REGS_IQDAC_RAM_WRITE 0x3020UL

/* Some magic controls bit tbd */
#define WR2RF_CTRL_REGS_IQDAC_RAM_PLAY 0x3022UL

/* None */
#define WR2RF_CTRL_REGS_RF1_DDS_FTW_VALID 0x3024UL

/* Phase increment value to xilinx dds core */
#define WR2RF_CTRL_REGS_RF1_DDS_FTW 0x3028UL

/* None */
#define WR2RF_CTRL_REGS_RF2_DDS_FTW_VALID 0x3030UL

/* Phase increment value to xilinx dds core */
#define WR2RF_CTRL_REGS_RF2_DDS_FTW 0x3038UL

/* Configures behaviour for how an nco_reset will operate */
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL 0x3040UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_DDS 0x1UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RFNCO_CH1 0x2UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RFNCO_CH2 0x4UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RF1_TRIG1 0x8UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RF2_TRIG1 0x10UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_SOFT 0x20UL

/* Global status register, write to clear. */
#define WR2RF_CTRL_REGS_GBL_STATUS 0x3042UL
#define WR2RF_CTRL_REGS_GBL_STATUS_RF1_T1_START 0x1UL
#define WR2RF_CTRL_REGS_GBL_STATUS_RF1_T2_START 0x2UL
#define WR2RF_CTRL_REGS_GBL_STATUS_RF2_T1_START 0x4UL
#define WR2RF_CTRL_REGS_GBL_STATUS_RF2_T2_START 0x8UL

#ifndef __ASSEMBLER__
struct wr2rf_ctrl_regs {
  /* [0x0]: SUBMAP Registers for rf1 vtus */
  struct wr2rf_rftrigger_regs rf1_vtus;

  /* padding to: 128 words */
  uint32_t __padding_0[60];

  /* [0x200]: SUBMAP Registers for rf2 vtus */
  struct wr2rf_rftrigger_regs rf2_vtus;

  /* padding to: 1024 words */
  uint32_t __padding_1[828];

  /* [0x1000]: SUBMAP Registers for rf1 rfnco */
  uint32_t rf1_rfnco[1024];

  /* [0x2000]: SUBMAP Registers for rf2 rfnco */
  uint32_t rf2_rfnco[1024];

  /* [0x3000]: REG (rw) phase represented as a signed integer */
  uint16_t rf1_iqdac_phase;

  /* [0x3002]: REG (rw) phase represented as a signed integer */
  uint16_t rf2_iqdac_phase;

  /* [0x3004]: REG (rw) phase represented as a signed integer */
  uint16_t rf1_iqdac_phase_update;

  /* [0x3006]: REG (rw) phase represented as a signed integer */
  uint16_t rf2_iqdac_phase_update;

  /* [0x3008]: REG (rw) I ampl/phase for IQ complex multiplier */
  uint16_t rf1_iqdac_igain_arm;

  /* [0x300a]: REG (rw) Q ampl/phase for IQ complex multiplier */
  uint16_t rf1_iqdac_qgain_arm;

  /* [0x300c]: REG (rw) I ampl/phase for IQ complex multiplier */
  uint16_t rf2_iqdac_igain_arm;

  /* [0x300e]: REG (rw) Q ampl/phase for IQ complex multiplier */
  uint16_t rf2_iqdac_qgain_arm;

  /* [0x3010]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf1_iqdac_igain;

  /* [0x3012]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf1_iqdac_qgain;

  /* [0x3014]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf2_iqdac_igain;

  /* [0x3016]: REG (ro) I gain for IQ complex multiplier */
  uint16_t rf2_iqdac_qgain;

  /* [0x3018]: REG (rw) Select iqdac I + Q sources */
  uint16_t rf1_iqdac_ctrl;

  /* [0x301a]: REG (rw) Select iqdac I + Q sources */
  uint16_t rf2_iqdac_ctrl;

  /* [0x301c]: REG (rw) Select iqdac ram address */
  uint16_t iqdac_ram_addr;

  /* [0x301e]: REG (rw) iqdac ram data to be written at address iqdac_ram_addr */
  uint16_t iqdac_ram_data;

  /* [0x3020]: REG (rw) Some magic controls bit tbd */
  uint16_t iqdac_ram_write;

  /* [0x3022]: REG (rw) Some magic controls bit tbd */
  uint16_t iqdac_ram_play;

  /* [0x3024]: REG (rw) (no description) */
  uint16_t rf1_dds_ftw_valid;

  /* padding to: 12328 words */
  uint8_t __padding_2[2];

  /* [0x3028]: REG (rw) Phase increment value to xilinx dds core */
  uint64_t rf1_dds_ftw;

  /* [0x3030]: REG (rw) (no description) */
  uint16_t rf2_dds_ftw_valid;

  /* padding to: 12344 words */
  uint8_t __padding_3[6];

  /* [0x3038]: REG (rw) Phase increment value to xilinx dds core */
  uint64_t rf2_dds_ftw;

  /* [0x3040]: REG (rw) Configures behaviour for how an nco_reset will operate */
  uint16_t nco_reset_ctrl;

  /* [0x3042]: REG (rw) Global status register, write to clear. */
  uint16_t gbl_status;
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__WR2RF_CTRL_REGS__H__ */
