--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- 
-- https://www.ohwr.org/projects/wr2rf-vme
--------------------------------------------------------------------------------
--
-- unit name:   wr2rf_vme_p0
--
-- description: Wapper for vme_p0 logic
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

library unisim;
use unisim.vcomponents.all;

entity wr2rf_vme_p0 is

    port (
        rf1_clk_bufg_i   : in  std_logic;
        rf2_clk_bufg_i   : in  std_logic;

        vme_p0_h1_bsb_o  : out std_logic_vector(7 downto 0);
        vme_p0_h1_c40_o  : out std_logic;
        vme_p0_h1_lbb_o : out std_logic_vector(7 downto 0);
        vme_p0_h1_hbb_o : out std_logic_vector(7 downto 0);
        vme_p0_h1_tc_o   : out std_logic;

        vme_p0_h2_bsb_o  : out std_logic_vector(7 downto 0);
        vme_p0_h2_c40_o  : out std_logic;
        vme_p0_h2_lbb_o : out std_logic_vector(7 downto 0);
        vme_p0_h2_hbb_o : out std_logic_vector(7 downto 0);
        vme_p0_h2_tc_o   : out std_logic;
        
        vme_p0_oen_o     : out std_logic );                
        
end entity;

architecture rtl of wr2rf_vme_p0 is

    signal h1_lfsr32          : std_logic_vector(31 downto 0);
    signal h1_lfsr32_r        : std_logic_vector(31 downto 0) := X"00000001";
    signal h2_lfsr32          : std_logic_vector(31 downto 0);
    signal h2_lfsr32_r        : std_logic_vector(31 downto 0) := X"10000001";

begin

    h1_lfsr32(0)           <= h1_lfsr32_r(31) xor h1_lfsr32_r(21) xor h1_lfsr32_r(1) xor h1_lfsr32_r(0);
    h1_lfsr32(31 downto 1) <= h1_lfsr32_r(30 downto 0);
    
    process (rf1_clk_bufg_i) is
    begin
        if rising_edge (rf1_clk_bufg_i) then
            h1_lfsr32_r        <= h1_lfsr32;                        
        end if;
    end process;
    

    h2_lfsr32(0)           <= h2_lfsr32_r(31) xor h2_lfsr32_r(21) xor h2_lfsr32_r(1) xor h2_lfsr32_r(0);
    h2_lfsr32(31 downto 1) <= h2_lfsr32_r(30 downto 0);
    
    process (rf1_clk_bufg_i) is
    begin
        if rising_edge (rf1_clk_bufg_i) then
            h2_lfsr32_r        <= h2_lfsr32;                        
        end if;
    end process;
    
    -- outputs
    vme_p0_oen_o     <= h1_lfsr32_r(31);
    
    vme_p0_h1_bsb_o  <= h1_lfsr32_r(7  downto  0);
    vme_p0_h1_lbb_o <= h1_lfsr32_r(15 downto  8);
    vme_p0_h1_hbb_o <= h1_lfsr32_r(23 downto 16);
    vme_p0_h1_tc_o   <= rf1_clk_bufg_i;
    vme_p0_h1_c40_o  <= rf1_clk_bufg_i;    

    vme_p0_h2_bsb_o  <= h2_lfsr32_r(7  downto  0);
    vme_p0_h2_lbb_o <= h2_lfsr32_r(15 downto  8);
    vme_p0_h2_hbb_o <= h2_lfsr32_r(23 downto 16);
    vme_p0_h2_tc_o   <= rf2_clk_bufg_i;
    vme_p0_h2_c40_o  <= rf2_clk_bufg_i;
                                        
end architecture;

