-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
-- Generated on Wed May 10 11:16:40 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

entity wr2rf_vme_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- HW serial number
    init_hwinfo_serialNumber_i : in    std_logic_vector(63 downto 0);

    -- Module ID code
    -- Hardware jumper setting, 1=Disable
    init_hwinfo_ident_jtagRemoteDisable_i : in    std_logic;
    -- Piggy-back module ID, if any
    init_hwinfo_ident_extendedID_i : in    std_logic_vector(6 downto 0);
    -- Main card ident code
    init_hwinfo_ident_cardID_i : in    std_logic_vector(7 downto 0);

    -- Firmware Version
    init_hwinfo_firmwareVersion_i : in    std_logic_vector(31 downto 0);

    -- Memory Map Version
    init_hwinfo_memMapVersion_i : in    std_logic_vector(31 downto 0);

    -- Echo register
    -- This version of the standard foresees only 8bits linked to real memory
    init_hwinfo_echo_echo_o : out   std_logic_vector(7 downto 0);

    -- Firmware update (FAR)
    init_fw_update_i     : in    t_wishbone_master_in;
    init_fw_update_o     : out   t_wishbone_master_out;

    -- FPGA reconfiguration
    init_reconfigure_o   : out   std_logic_vector(15 downto 0);
    init_reconfigure_wr_o : out   std_logic;

    -- Control register for the system clock
    -- 0: dmtd clock (initial); 1: pll (must be locked)
    init_clock_ctrl_clk_sel_o : out   std_logic;
    -- Reset the system pll
    init_clock_ctrl_mmcm_reset_o : out   std_logic;

    -- Control register for wrcore
    -- Reset the wrcore, active low
    init_wrcore_ctrl_reset_n_o : out   std_logic;

    -- Control register for iodelayctrl
    -- Reset the iodelay, must transition 0->1 (for > 50 ns) then 1->0
    init_iodelay_ctrl_reset_o : out   std_logic;

    -- Adjust the mmcm shift for the 10Mhz external clock
    -- 1: increase, 0: descrease.  Step: TBD
    init_mmcm_shift_incdec_o : out   std_logic;
    init_mmcm_shift_wr_o : out   std_logic;

    -- Status register for system clock
    -- lock status of the mmcm
    init_clock_status_mmcm_locked_i : in    std_logic;
    -- Shift adjustment in progress
    init_clock_status_shift_busy_i : in    std_logic;

    -- timing io grouping of signals
    -- terminations for UBT
    init_tmg_io_term_o   : out   std_logic_vector(3 downto 0);
    -- Output enable for general IO signals (not clocks)
    init_tmg_io_oe_o     : out   std_logic_vector(3 downto 0);
    -- terminations for UBT
    init_tmg_clk_term_o  : out   std_logic_vector(1 downto 0);
    -- independent bidirectional control for clock outputs
    init_tmg_clk_oe_o    : out   std_logic_vector(1 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit start
    init_lemo_rf1_t1_start_sel_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit start
    init_lemo_rf1_t2_start_sel_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit start
    init_lemo_rf2_t1_start_sel_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit start
    init_lemo_rf2_t2_start_sel_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit stop
    init_lemo_rf1_t1_stop_sel_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit stop
    init_lemo_rf1_t2_stop_sel_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- select which lemo is connected to the trigger unit stop
    init_lemo_rf2_t1_stop_sel_o : out   std_logic_vector(5 downto 0);

    -- lemos
    -- select which lemo is connected to the trigger unit stop
    init_lemo_rf2_t2_stop_sel_o : out   std_logic_vector(5 downto 0);

    -- lemo debug selection
    -- lemo debug selection
    init_tmgio1_osel_o   : out   std_logic_vector(13 downto 0);

    -- lemo debug selection
    -- lemo debug selection
    init_tmgio2_osel_o   : out   std_logic_vector(13 downto 0);

    -- lemo debug selection
    -- lemo debug selection
    init_tmgio3_osel_o   : out   std_logic_vector(13 downto 0);

    -- lemo debug selection
    -- lemo debug selection
    init_tmgio4_osel_o   : out   std_logic_vector(13 downto 0);

    -- lemo debug selection
    -- lemo debug selection
    init_tmgclk1_osel_o  : out   std_logic_vector(13 downto 0);

    -- lemo debug selection
    -- lemo debug selection
    init_tmgclk2_osel_o  : out   std_logic_vector(13 downto 0);

    -- lemo debug selection
    -- lemo gpio output signal
    init_lemo_gpio_o     : out   std_logic_vector(1 downto 0);

    -- lemo debug selection
    -- select which lemo outputs are pulse extended
    init_lemo_ext_sel_o  : out   std_logic_vector(5 downto 0);

    -- lemo debug selection
    -- select which vtu can be driven to a lemo output
    init_softstart_sel_o : out   std_logic_vector(3 downto 0);

    -- lemo debug selection
    -- select which vtu can be driven to a lemo output
    init_softstop_sel_o  : out   std_logic_vector(3 downto 0);

    -- lemo debug selection
    -- Hot-1 encoding for which lemo output is pulse extended
    init_lemo_pulse_ext_o : out   std_logic_vector(5 downto 0);

    -- timing io grouping of signals
    -- 0: input, 1 : output
    init_pin_ctrl_ext_10m_dir_o : out   std_logic;
    -- 0: input, 1 : output
    init_pin_ctrl_ext_pps_dir_o : out   std_logic;

    -- Status lines from the main PLL (LTC6950)
    -- read PLL status for details
    init_pll_status_error_i : in    std_logic;
    -- Set when locked
    init_pll_status_locked_i : in    std_logic;

    -- Ctrl lines to the main PLL (LTC6950)
    -- LTC6950 sync is activated by a 0->1 transition
    init_pll_ctrl_sync_o : out   std_logic;

    -- dds (AD9910) control signals
    -- Full chip reset (master reset)
    init_dds_ctrl_reset_o : out   std_logic;
    -- Activate register changed by SPI commands
    init_dds_ctrl_ioupdate_o : out   std_logic;
    -- Select dds profile
    init_dds_ctrl_profile_o : out   std_logic_vector(2 downto 0);

    -- dds (AD9910) control signals
    -- nanosecond delay of the dds_ioupdate signal
    init_dds_ioupdate_fdelay_o : out   std_logic_vector(3 downto 0);
    -- odelay value, steps of 78 ps
    init_dds_ioupdate_odelay_o : out   std_logic_vector(4 downto 0);

    -- dds (AD9910) status signals
    -- Set in case of synchronization error
    init_dds_status_sync_error_i : in    std_logic;

    -- Enable the OCXO
    init_ocxo_ctrl_enable_o : out   std_logic;

    -- Records how long the ocxo has been enabled
    init_ocxo_uptime_val_i : in    std_logic_vector(15 downto 0);

    -- Adjust NCO output for azimuthal position
    init_nco_azimuthal_value_o : out   std_logic_vector(47 downto 0);

    -- Adjust NCO output for cable delays
    init_nco_cabledelay_value_o : out   std_logic_vector(47 downto 0);

    -- harmonic factor
    init_nco_hb_value_o  : out   std_logic_vector(9 downto 0);

    -- Adjust NCO increment per clock cycle
    init_nco_h1_ftw_value_o : out   std_logic_vector(47 downto 0);

    -- Adjust NCO starting phase
    init_nco_h1_prog_value_o : out   std_logic_vector(47 downto 0);

    -- control
    -- reset the nco
    init_nco_ctrl_reset_nco_o : out   std_logic;
    -- reset slip_stacking
    init_nco_ctrl_reset_slip_o : out   std_logic;
    -- reset frequency shift keying
    init_nco_ctrl_reset_fsk_o : out   std_logic;
    -- rate
    init_nco_ctrl_rate_o : out   std_logic_vector(2 downto 0);

    -- Used to signal that all parameters are valid and ready for use
    init_nco_update_valid_o : out   std_logic;

    -- Used to determine if local registers (=1) or WRStreamer (=0) parameters are selected
    init_nco_loc_or_wrs_params_sel_o : out   std_logic;

    -- Front panel select
    init_svec_mup_ctrl_gpio_sel_o : out   std_logic_vector(3 downto 0);
    init_svec_mup_ctrl_led_sel_o : out   std_logic_vector(3 downto 0);
    init_svec_mup_ctrl_bclk_rfclk_sel_o : out   std_logic;
    init_svec_mup_ctrl_ila_sel_o : out   std_logic;

    -- rf trigger mockup
    init_svec_mup_rftrig_t1stop_o : out   std_logic;
    init_svec_mup_rftrig_t1start_o : out   std_logic;
    init_svec_mup_rftrig_t2stop_o : out   std_logic;
    init_svec_mup_rftrig_t2start_o : out   std_logic;

    -- fmc dio
    init_svec_mup_fmc1_term_o : out   std_logic_vector(4 downto 0);
    init_svec_mup_fmc1_oe_n_o : out   std_logic_vector(4 downto 0);
    init_svec_mup_fmc1_led_o : out   std_logic_vector(1 downto 0);

    -- fmc dio
    init_svec_mup_fmc2_term_o : out   std_logic_vector(4 downto 0);
    init_svec_mup_fmc2_oe_n_o : out   std_logic_vector(4 downto 0);
    init_svec_mup_fmc2_led_o : out   std_logic_vector(1 downto 0);

    -- Last FTW received
    init_wrs_rxframe_ftw_value_i : in    std_logic_vector(47 downto 0);

    -- Last Control received
    init_wrs_rxframe_ctrl_i : in    std_logic_vector(15 downto 0);

    -- Number of RFFrameTransceiver frames received
    init_wrs_rxframe_counter_i : in    std_logic_vector(15 downto 0);

    -- Timestamp when the last frame was received from wr streamers
    init_wrs_rxframe_rxwrtimestamp_i : in    std_logic_vector(31 downto 0);

    -- Timestamp when the last frame was transmitted from wr streamers
    init_wrs_rxframe_txwrtimestamp_i : in    std_logic_vector(31 downto 0);

    -- Timestamp when the last frame was received from RFFrameTransceiver
    init_wrs_rxframe_rftimestamp_i : in    std_logic_vector(31 downto 0);

    -- Update the RF frame timestamps for readout
    init_wrs_rxframe_rfframe_ts_update_o : out   std_logic;

    -- Timestamp TAI for the last RFframe received that asserted nco_reset
    init_wrs_rxframe_nco_reset_tai_val_i : in    std_logic_vector(39 downto 0);

    -- Timestamp TAI for the last RFframe received that asserted nco_reset
    init_wrs_rxframe_nco_reset_cycles_val_i : in    std_logic_vector(27 downto 0);

    -- Timestamp TAI for the last RFframe received
    init_wrs_rxframe_tai_val_i : in    std_logic_vector(39 downto 0);

    -- Timestamp TAI for the last RFframe received
    init_wrs_rxframe_cycles_val_i : in    std_logic_vector(27 downto 0);

    -- Absolute time (in sec)
    init_wrc_tai_value_i : in    std_logic_vector(39 downto 0);

    -- Number of cycles
    init_wrc_cycles_value_i : in    std_logic_vector(27 downto 0);

    -- WR status
    init_wrc_status_linkup_i : in    std_logic;
    init_wrc_status_time_valid_i : in    std_logic;

    -- Page 0 offset
    init_wrc_page0_o     : out   std_logic_vector(31 downto 0);

    -- Page 1 offset
    init_wrc_page1_o     : out   std_logic_vector(31 downto 0);

    -- REG ftw_h1_main
    init_txframe_ftw_h1_main_o : out   std_logic_vector(63 downto 0);

    -- REG ftw_h1_prog
    init_txframe_ftw_h1_prog_o : out   std_logic_vector(63 downto 0);

    -- REG ftw_h1_on
    init_txframe_ftw_h1_on_o : out   std_logic_vector(63 downto 0);

    -- REG dftw_h1_slip1
    init_txframe_dftw_h1_slip1_o : out   std_logic_vector(31 downto 0);

    -- REG dftw_h1_slip2
    init_txframe_dftw_h1_slip2_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint1
    init_txframe_setpoint1_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint2
    init_txframe_setpoint2_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint3
    init_txframe_setpoint3_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint4
    init_txframe_setpoint4_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint5
    init_txframe_setpoint5_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint6
    init_txframe_setpoint6_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint7
    init_txframe_setpoint7_o : out   std_logic_vector(31 downto 0);

    -- REG setpoint8
    init_txframe_setpoint8_o : out   std_logic_vector(31 downto 0);

    -- REG noise
    init_txframe_noise_o : out   std_logic_vector(31 downto 0);

    -- REG control
    init_txframe_control_o : out   std_logic_vector(15 downto 0);

    -- SPI master for the main PLL (LTC6950)
    init_pll_spi_i       : in    t_wishbone_master_in;
    init_pll_spi_o       : out   t_wishbone_master_out;

    -- SPI master for RF chips.
    -- cs0: DDS
    -- cs1: IQ DAC 1
    -- cs2: IQ DAC 2

    init_rf_spi_i        : in    t_wishbone_master_in;
    init_rf_spi_o        : out   t_wishbone_master_out;

    -- Register for RF components
    init_rf_i            : in    t_wishbone_master_in;
    init_rf_o            : out   t_wishbone_master_out;

    -- RF Frame transceiver
    init_framerxtx_i     : in    t_wishbone_master_in;
    init_framerxtx_o     : out   t_wishbone_master_out;

    -- Xilinx ADC
    init_xadc_i          : in    t_wishbone_master_in;
    init_xadc_o          : out   t_wishbone_master_out;

    -- WR ptp core (peripheral only)
    init_wrpc_i          : in    t_wishbone_master_in;
    init_wrpc_o          : out   t_wishbone_master_out;

    -- Registers for rf1 vtus
    ctrl_rf1_vtus_i      : in    t_wishbone_master_in;
    ctrl_rf1_vtus_o      : out   t_wishbone_master_out;

    -- Registers for rf2 vtus
    ctrl_rf2_vtus_i      : in    t_wishbone_master_in;
    ctrl_rf2_vtus_o      : out   t_wishbone_master_out;

    -- Registers for rf1 rfnco
    ctrl_rf1_rfnco_i     : in    t_wishbone_master_in;
    ctrl_rf1_rfnco_o     : out   t_wishbone_master_out;

    -- Registers for rf2 rfnco
    ctrl_rf2_rfnco_i     : in    t_wishbone_master_in;
    ctrl_rf2_rfnco_o     : out   t_wishbone_master_out;

    -- phase represented as a signed integer
    ctrl_rf1_iqdac_phase_o : out   std_logic_vector(15 downto 0);

    -- phase represented as a signed integer
    ctrl_rf2_iqdac_phase_o : out   std_logic_vector(15 downto 0);

    -- phase represented as a signed integer
    ctrl_rf1_iqdac_phase_update_valid_o : out   std_logic;

    -- phase represented as a signed integer
    ctrl_rf2_iqdac_phase_update_valid_o : out   std_logic;

    -- I ampl/phase for IQ complex multiplier
    ctrl_rf1_iqdac_igain_arm_o : out   std_logic_vector(15 downto 0);

    -- Q ampl/phase for IQ complex multiplier
    ctrl_rf1_iqdac_qgain_arm_o : out   std_logic_vector(15 downto 0);

    -- I ampl/phase for IQ complex multiplier
    ctrl_rf2_iqdac_igain_arm_o : out   std_logic_vector(15 downto 0);

    -- Q ampl/phase for IQ complex multiplier
    ctrl_rf2_iqdac_qgain_arm_o : out   std_logic_vector(15 downto 0);

    -- I gain for IQ complex multiplier
    ctrl_rf1_iqdac_igain_i : in    std_logic_vector(15 downto 0);

    -- I gain for IQ complex multiplier
    ctrl_rf1_iqdac_qgain_i : in    std_logic_vector(15 downto 0);

    -- I gain for IQ complex multiplier
    ctrl_rf2_iqdac_igain_i : in    std_logic_vector(15 downto 0);

    -- I gain for IQ complex multiplier
    ctrl_rf2_iqdac_qgain_i : in    std_logic_vector(15 downto 0);

    -- Select iqdac I + Q sources
    ctrl_rf1_iqdac_ctrl_o : out   std_logic_vector(15 downto 0);

    -- Select iqdac I + Q sources
    ctrl_rf2_iqdac_ctrl_o : out   std_logic_vector(15 downto 0);

    -- Select iqdac ram address
    ctrl_iqdac_ram_addr_o : out   std_logic_vector(15 downto 0);

    -- iqdac ram data to be written at address iqdac_ram_addr
    ctrl_iqdac_ram_data_o : out   std_logic_vector(15 downto 0);

    -- Some magic controls bit tbd
    ctrl_iqdac_ram_write_o : out   std_logic_vector(15 downto 0);

    -- Some magic controls bit tbd
    ctrl_iqdac_ram_play_o : out   std_logic_vector(15 downto 0);

    -- REG rf1_dds_ftw_valid
    ctrl_rf1_dds_ftw_valid_o : out   std_logic_vector(15 downto 0);

    -- Phase increment value to xilinx dds core
    ctrl_rf1_dds_ftw_o   : out   std_logic_vector(63 downto 0);

    -- REG rf2_dds_ftw_valid
    ctrl_rf2_dds_ftw_valid_o : out   std_logic_vector(15 downto 0);

    -- Phase increment value to xilinx dds core
    ctrl_rf2_dds_ftw_o   : out   std_logic_vector(63 downto 0);

    -- Configures behaviour for how an nco_reset will operate
    -- dds_nco_reset = nco_reset & mask_dds
    ctrl_nco_reset_ctrl_mask_dds_o : out   std_logic;
    -- rfnco_ch1_nco_reset = nco_reset & mask_rfnco_ch1
    ctrl_nco_reset_ctrl_mask_rfnco_ch1_o : out   std_logic;
    -- rfnco_ch2_nco_reset = nco_reset & mask_rfnco_ch2
    ctrl_nco_reset_ctrl_mask_rfnco_ch2_o : out   std_logic;
    -- rf1_trig1_nco_reset = nco_reset & mask_mask_rf1_trig1
    ctrl_nco_reset_ctrl_mask_rf1_trig1_o : out   std_logic;
    -- rf2_trig1_nco_reset = nco_reset & mask_mask_rf2_trig1
    ctrl_nco_reset_ctrl_mask_rf2_trig1_o : out   std_logic;
    -- forces an nco reset due to software
    ctrl_nco_reset_ctrl_soft_o : out   std_logic;

    -- Global status register, write to clear.
    -- rf1/t1 has started
    ctrl_gbl_status_rf1_t1_start_i : in    std_logic;
    -- rf1/t2 has started
    ctrl_gbl_status_rf1_t2_start_i : in    std_logic;
    -- rf2/t1 has started
    ctrl_gbl_status_rf2_t1_start_i : in    std_logic;
    -- rf2/t2 has started
    ctrl_gbl_status_rf2_t2_start_i : in    std_logic
  );
end wr2rf_vme_regs;

architecture syn of wr2rf_vme_regs is
  signal adr_int                        : std_logic_vector(14 downto 1);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal init_hwinfo_echo_echo_reg      : std_logic_vector(7 downto 0);
  signal init_hwinfo_echo_wreq          : std_logic_vector(1 downto 0);
  signal init_hwinfo_echo_wack          : std_logic_vector(1 downto 0);
  signal init_fw_update_re              : std_logic;
  signal init_fw_update_we              : std_logic;
  signal init_fw_update_wt              : std_logic;
  signal init_fw_update_rt              : std_logic;
  signal init_fw_update_tr              : std_logic;
  signal init_fw_update_wack            : std_logic;
  signal init_fw_update_rack            : std_logic;
  signal init_reconfigure_wreq          : std_logic;
  signal init_clock_ctrl_clk_sel_reg    : std_logic;
  signal init_clock_ctrl_mmcm_reset_reg : std_logic;
  signal init_clock_ctrl_wreq           : std_logic;
  signal init_clock_ctrl_wack           : std_logic;
  signal init_wrcore_ctrl_reset_n_reg   : std_logic;
  signal init_wrcore_ctrl_wreq          : std_logic;
  signal init_wrcore_ctrl_wack          : std_logic;
  signal init_iodelay_ctrl_reset_reg    : std_logic;
  signal init_iodelay_ctrl_wreq         : std_logic;
  signal init_iodelay_ctrl_wack         : std_logic;
  signal init_mmcm_shift_incdec_reg     : std_logic;
  signal init_mmcm_shift_wreq           : std_logic;
  signal init_mmcm_shift_wack           : std_logic;
  signal init_tmg_io_term_reg           : std_logic_vector(3 downto 0);
  signal init_tmg_io_oe_reg             : std_logic_vector(3 downto 0);
  signal init_tmg_clk_term_reg          : std_logic_vector(1 downto 0);
  signal init_tmg_clk_oe_reg            : std_logic_vector(1 downto 0);
  signal init_tmg_wreq                  : std_logic;
  signal init_tmg_wack                  : std_logic;
  signal init_lemo_rf1_t1_start_sel_reg : std_logic_vector(5 downto 0);
  signal init_lemo_rf1_t1_start_wreq    : std_logic;
  signal init_lemo_rf1_t1_start_wack    : std_logic;
  signal init_lemo_rf1_t2_start_sel_reg : std_logic_vector(5 downto 0);
  signal init_lemo_rf1_t2_start_wreq    : std_logic;
  signal init_lemo_rf1_t2_start_wack    : std_logic;
  signal init_lemo_rf2_t1_start_sel_reg : std_logic_vector(5 downto 0);
  signal init_lemo_rf2_t1_start_wreq    : std_logic;
  signal init_lemo_rf2_t1_start_wack    : std_logic;
  signal init_lemo_rf2_t2_start_sel_reg : std_logic_vector(5 downto 0);
  signal init_lemo_rf2_t2_start_wreq    : std_logic;
  signal init_lemo_rf2_t2_start_wack    : std_logic;
  signal init_lemo_rf1_t1_stop_sel_reg  : std_logic_vector(5 downto 0);
  signal init_lemo_rf1_t1_stop_wreq     : std_logic;
  signal init_lemo_rf1_t1_stop_wack     : std_logic;
  signal init_lemo_rf1_t2_stop_sel_reg  : std_logic_vector(5 downto 0);
  signal init_lemo_rf1_t2_stop_wreq     : std_logic;
  signal init_lemo_rf1_t2_stop_wack     : std_logic;
  signal init_lemo_rf2_t1_stop_sel_reg  : std_logic_vector(5 downto 0);
  signal init_lemo_rf2_t1_stop_wreq     : std_logic;
  signal init_lemo_rf2_t1_stop_wack     : std_logic;
  signal init_lemo_rf2_t2_stop_sel_reg  : std_logic_vector(5 downto 0);
  signal init_lemo_rf2_t2_stop_wreq     : std_logic;
  signal init_lemo_rf2_t2_stop_wack     : std_logic;
  signal init_tmgio1_osel_reg           : std_logic_vector(13 downto 0);
  signal init_tmgio1_wreq               : std_logic;
  signal init_tmgio1_wack               : std_logic;
  signal init_tmgio2_osel_reg           : std_logic_vector(13 downto 0);
  signal init_tmgio2_wreq               : std_logic;
  signal init_tmgio2_wack               : std_logic;
  signal init_tmgio3_osel_reg           : std_logic_vector(13 downto 0);
  signal init_tmgio3_wreq               : std_logic;
  signal init_tmgio3_wack               : std_logic;
  signal init_tmgio4_osel_reg           : std_logic_vector(13 downto 0);
  signal init_tmgio4_wreq               : std_logic;
  signal init_tmgio4_wack               : std_logic;
  signal init_tmgclk1_osel_reg          : std_logic_vector(13 downto 0);
  signal init_tmgclk1_wreq              : std_logic;
  signal init_tmgclk1_wack              : std_logic;
  signal init_tmgclk2_osel_reg          : std_logic_vector(13 downto 0);
  signal init_tmgclk2_wreq              : std_logic;
  signal init_tmgclk2_wack              : std_logic;
  signal init_lemo_gpio_reg             : std_logic_vector(1 downto 0);
  signal init_lemo_wreq                 : std_logic;
  signal init_lemo_wack                 : std_logic;
  signal init_lemo_ext_sel_reg          : std_logic_vector(5 downto 0);
  signal init_lemo_ext_wreq             : std_logic;
  signal init_lemo_ext_wack             : std_logic;
  signal init_softstart_sel_reg         : std_logic_vector(3 downto 0);
  signal init_softstart_wreq            : std_logic;
  signal init_softstart_wack            : std_logic;
  signal init_softstop_sel_reg          : std_logic_vector(3 downto 0);
  signal init_softstop_wreq             : std_logic;
  signal init_softstop_wack             : std_logic;
  signal init_lemo_pulse_ext_reg        : std_logic_vector(5 downto 0);
  signal init_lemo_pulse_wreq           : std_logic;
  signal init_lemo_pulse_wack           : std_logic;
  signal init_pin_ctrl_ext_10m_dir_reg  : std_logic;
  signal init_pin_ctrl_ext_pps_dir_reg  : std_logic;
  signal init_pin_ctrl_wreq             : std_logic;
  signal init_pin_ctrl_wack             : std_logic;
  signal init_pll_ctrl_sync_reg         : std_logic;
  signal init_pll_ctrl_wreq             : std_logic;
  signal init_pll_ctrl_wack             : std_logic;
  signal init_dds_ctrl_reset_reg        : std_logic;
  signal init_dds_ctrl_ioupdate_reg     : std_logic;
  signal init_dds_ctrl_profile_reg      : std_logic_vector(2 downto 0);
  signal init_dds_ctrl_wreq             : std_logic;
  signal init_dds_ctrl_wack             : std_logic;
  signal init_dds_ioupdate_fdelay_reg   : std_logic_vector(3 downto 0);
  signal init_dds_ioupdate_odelay_reg   : std_logic_vector(4 downto 0);
  signal init_dds_ioupdate_wreq         : std_logic;
  signal init_dds_ioupdate_wack         : std_logic;
  signal init_ocxo_ctrl_enable_reg      : std_logic;
  signal init_ocxo_ctrl_wreq            : std_logic;
  signal init_ocxo_ctrl_wack            : std_logic;
  signal init_nco_azimuthal_value_reg   : std_logic_vector(47 downto 0);
  signal init_nco_azimuthal_wreq        : std_logic_vector(3 downto 0);
  signal init_nco_azimuthal_wack        : std_logic_vector(3 downto 0);
  signal init_nco_cabledelay_value_reg  : std_logic_vector(47 downto 0);
  signal init_nco_cabledelay_wreq       : std_logic_vector(3 downto 0);
  signal init_nco_cabledelay_wack       : std_logic_vector(3 downto 0);
  signal init_nco_hb_value_reg          : std_logic_vector(9 downto 0);
  signal init_nco_hb_wreq               : std_logic;
  signal init_nco_hb_wack               : std_logic;
  signal init_nco_h1_ftw_value_reg      : std_logic_vector(47 downto 0);
  signal init_nco_h1_ftw_wreq           : std_logic_vector(3 downto 0);
  signal init_nco_h1_ftw_wack           : std_logic_vector(3 downto 0);
  signal init_nco_h1_prog_value_reg     : std_logic_vector(47 downto 0);
  signal init_nco_h1_prog_wreq          : std_logic_vector(3 downto 0);
  signal init_nco_h1_prog_wack          : std_logic_vector(3 downto 0);
  signal init_nco_ctrl_reset_nco_reg    : std_logic;
  signal init_nco_ctrl_reset_slip_reg   : std_logic;
  signal init_nco_ctrl_reset_fsk_reg    : std_logic;
  signal init_nco_ctrl_rate_reg         : std_logic_vector(2 downto 0);
  signal init_nco_ctrl_wreq             : std_logic;
  signal init_nco_ctrl_wack             : std_logic;
  signal init_nco_update_valid_reg      : std_logic;
  signal init_nco_update_wreq           : std_logic;
  signal init_nco_update_wack           : std_logic;
  signal init_nco_loc_or_wrs_params_sel_reg : std_logic;
  signal init_nco_loc_or_wrs_wreq       : std_logic;
  signal init_nco_loc_or_wrs_wack       : std_logic;
  signal init_svec_mup_ctrl_gpio_sel_reg : std_logic_vector(3 downto 0);
  signal init_svec_mup_ctrl_led_sel_reg : std_logic_vector(3 downto 0);
  signal init_svec_mup_ctrl_bclk_rfclk_sel_reg : std_logic;
  signal init_svec_mup_ctrl_ila_sel_reg : std_logic;
  signal init_svec_mup_ctrl_wreq        : std_logic;
  signal init_svec_mup_ctrl_wack        : std_logic;
  signal init_svec_mup_rftrig_t1stop_reg : std_logic;
  signal init_svec_mup_rftrig_t1start_reg : std_logic;
  signal init_svec_mup_rftrig_t2stop_reg : std_logic;
  signal init_svec_mup_rftrig_t2start_reg : std_logic;
  signal init_svec_mup_rftrig_wreq      : std_logic;
  signal init_svec_mup_rftrig_wack      : std_logic;
  signal init_svec_mup_fmc1_term_reg    : std_logic_vector(4 downto 0);
  signal init_svec_mup_fmc1_oe_n_reg    : std_logic_vector(4 downto 0);
  signal init_svec_mup_fmc1_led_reg     : std_logic_vector(1 downto 0);
  signal init_svec_mup_fmc1_wreq        : std_logic;
  signal init_svec_mup_fmc1_wack        : std_logic;
  signal init_svec_mup_fmc2_term_reg    : std_logic_vector(4 downto 0);
  signal init_svec_mup_fmc2_oe_n_reg    : std_logic_vector(4 downto 0);
  signal init_svec_mup_fmc2_led_reg     : std_logic_vector(1 downto 0);
  signal init_svec_mup_fmc2_wreq        : std_logic;
  signal init_svec_mup_fmc2_wack        : std_logic;
  signal init_wrs_rxframe_rfframe_ts_update_reg : std_logic;
  signal init_wrs_rxframe_rfframe_ts_wreq : std_logic;
  signal init_wrs_rxframe_rfframe_ts_wack : std_logic;
  signal init_wrc_page0_reg             : std_logic_vector(31 downto 0);
  signal init_wrc_page0_wreq            : std_logic_vector(1 downto 0);
  signal init_wrc_page0_wack            : std_logic_vector(1 downto 0);
  signal init_wrc_page1_reg             : std_logic_vector(31 downto 0);
  signal init_wrc_page1_wreq            : std_logic_vector(1 downto 0);
  signal init_wrc_page1_wack            : std_logic_vector(1 downto 0);
  signal init_txframe_ftw_h1_main_reg   : std_logic_vector(63 downto 0);
  signal init_txframe_ftw_h1_main_wreq  : std_logic_vector(3 downto 0);
  signal init_txframe_ftw_h1_main_wack  : std_logic_vector(3 downto 0);
  signal init_txframe_ftw_h1_prog_reg   : std_logic_vector(63 downto 0);
  signal init_txframe_ftw_h1_prog_wreq  : std_logic_vector(3 downto 0);
  signal init_txframe_ftw_h1_prog_wack  : std_logic_vector(3 downto 0);
  signal init_txframe_ftw_h1_on_reg     : std_logic_vector(63 downto 0);
  signal init_txframe_ftw_h1_on_wreq    : std_logic_vector(3 downto 0);
  signal init_txframe_ftw_h1_on_wack    : std_logic_vector(3 downto 0);
  signal init_txframe_dftw_h1_slip1_reg : std_logic_vector(31 downto 0);
  signal init_txframe_dftw_h1_slip1_wreq : std_logic_vector(1 downto 0);
  signal init_txframe_dftw_h1_slip1_wack : std_logic_vector(1 downto 0);
  signal init_txframe_dftw_h1_slip2_reg : std_logic_vector(31 downto 0);
  signal init_txframe_dftw_h1_slip2_wreq : std_logic_vector(1 downto 0);
  signal init_txframe_dftw_h1_slip2_wack : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint1_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint1_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint1_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint2_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint2_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint2_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint3_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint3_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint3_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint4_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint4_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint4_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint5_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint5_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint5_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint6_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint6_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint6_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint7_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint7_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint7_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint8_reg     : std_logic_vector(31 downto 0);
  signal init_txframe_setpoint8_wreq    : std_logic_vector(1 downto 0);
  signal init_txframe_setpoint8_wack    : std_logic_vector(1 downto 0);
  signal init_txframe_noise_reg         : std_logic_vector(31 downto 0);
  signal init_txframe_noise_wreq        : std_logic_vector(1 downto 0);
  signal init_txframe_noise_wack        : std_logic_vector(1 downto 0);
  signal init_txframe_control_reg       : std_logic_vector(15 downto 0);
  signal init_txframe_control_wreq      : std_logic;
  signal init_txframe_control_wack      : std_logic;
  signal init_pll_spi_re                : std_logic;
  signal init_pll_spi_we                : std_logic;
  signal init_pll_spi_wt                : std_logic;
  signal init_pll_spi_rt                : std_logic;
  signal init_pll_spi_tr                : std_logic;
  signal init_pll_spi_wack              : std_logic;
  signal init_pll_spi_rack              : std_logic;
  signal init_rf_spi_re                 : std_logic;
  signal init_rf_spi_we                 : std_logic;
  signal init_rf_spi_wt                 : std_logic;
  signal init_rf_spi_rt                 : std_logic;
  signal init_rf_spi_tr                 : std_logic;
  signal init_rf_spi_wack               : std_logic;
  signal init_rf_spi_rack               : std_logic;
  signal init_rf_re                     : std_logic;
  signal init_rf_we                     : std_logic;
  signal init_rf_wt                     : std_logic;
  signal init_rf_rt                     : std_logic;
  signal init_rf_tr                     : std_logic;
  signal init_rf_wack                   : std_logic;
  signal init_rf_rack                   : std_logic;
  signal init_framerxtx_re              : std_logic;
  signal init_framerxtx_we              : std_logic;
  signal init_framerxtx_wt              : std_logic;
  signal init_framerxtx_rt              : std_logic;
  signal init_framerxtx_tr              : std_logic;
  signal init_framerxtx_wack            : std_logic;
  signal init_framerxtx_rack            : std_logic;
  signal init_xadc_re                   : std_logic;
  signal init_xadc_we                   : std_logic;
  signal init_xadc_wt                   : std_logic;
  signal init_xadc_rt                   : std_logic;
  signal init_xadc_tr                   : std_logic;
  signal init_xadc_wack                 : std_logic;
  signal init_xadc_rack                 : std_logic;
  signal init_wrpc_re                   : std_logic;
  signal init_wrpc_we                   : std_logic;
  signal init_wrpc_wt                   : std_logic;
  signal init_wrpc_rt                   : std_logic;
  signal init_wrpc_tr                   : std_logic;
  signal init_wrpc_wack                 : std_logic;
  signal init_wrpc_rack                 : std_logic;
  signal ctrl_rf1_vtus_re               : std_logic;
  signal ctrl_rf1_vtus_we               : std_logic;
  signal ctrl_rf1_vtus_wt               : std_logic;
  signal ctrl_rf1_vtus_rt               : std_logic;
  signal ctrl_rf1_vtus_tr               : std_logic;
  signal ctrl_rf1_vtus_wack             : std_logic;
  signal ctrl_rf1_vtus_rack             : std_logic;
  signal ctrl_rf2_vtus_re               : std_logic;
  signal ctrl_rf2_vtus_we               : std_logic;
  signal ctrl_rf2_vtus_wt               : std_logic;
  signal ctrl_rf2_vtus_rt               : std_logic;
  signal ctrl_rf2_vtus_tr               : std_logic;
  signal ctrl_rf2_vtus_wack             : std_logic;
  signal ctrl_rf2_vtus_rack             : std_logic;
  signal ctrl_rf1_rfnco_re              : std_logic;
  signal ctrl_rf1_rfnco_we              : std_logic;
  signal ctrl_rf1_rfnco_wt              : std_logic;
  signal ctrl_rf1_rfnco_rt              : std_logic;
  signal ctrl_rf1_rfnco_tr              : std_logic;
  signal ctrl_rf1_rfnco_wack            : std_logic;
  signal ctrl_rf1_rfnco_rack            : std_logic;
  signal ctrl_rf2_rfnco_re              : std_logic;
  signal ctrl_rf2_rfnco_we              : std_logic;
  signal ctrl_rf2_rfnco_wt              : std_logic;
  signal ctrl_rf2_rfnco_rt              : std_logic;
  signal ctrl_rf2_rfnco_tr              : std_logic;
  signal ctrl_rf2_rfnco_wack            : std_logic;
  signal ctrl_rf2_rfnco_rack            : std_logic;
  signal ctrl_rf1_iqdac_phase_reg       : std_logic_vector(15 downto 0);
  signal ctrl_rf1_iqdac_phase_wreq      : std_logic;
  signal ctrl_rf1_iqdac_phase_wack      : std_logic;
  signal ctrl_rf2_iqdac_phase_reg       : std_logic_vector(15 downto 0);
  signal ctrl_rf2_iqdac_phase_wreq      : std_logic;
  signal ctrl_rf2_iqdac_phase_wack      : std_logic;
  signal ctrl_rf1_iqdac_phase_update_valid_reg : std_logic;
  signal ctrl_rf1_iqdac_phase_update_wreq : std_logic;
  signal ctrl_rf1_iqdac_phase_update_wack : std_logic;
  signal ctrl_rf2_iqdac_phase_update_valid_reg : std_logic;
  signal ctrl_rf2_iqdac_phase_update_wreq : std_logic;
  signal ctrl_rf2_iqdac_phase_update_wack : std_logic;
  signal ctrl_rf1_iqdac_igain_arm_reg   : std_logic_vector(15 downto 0);
  signal ctrl_rf1_iqdac_igain_arm_wreq  : std_logic;
  signal ctrl_rf1_iqdac_igain_arm_wack  : std_logic;
  signal ctrl_rf1_iqdac_qgain_arm_reg   : std_logic_vector(15 downto 0);
  signal ctrl_rf1_iqdac_qgain_arm_wreq  : std_logic;
  signal ctrl_rf1_iqdac_qgain_arm_wack  : std_logic;
  signal ctrl_rf2_iqdac_igain_arm_reg   : std_logic_vector(15 downto 0);
  signal ctrl_rf2_iqdac_igain_arm_wreq  : std_logic;
  signal ctrl_rf2_iqdac_igain_arm_wack  : std_logic;
  signal ctrl_rf2_iqdac_qgain_arm_reg   : std_logic_vector(15 downto 0);
  signal ctrl_rf2_iqdac_qgain_arm_wreq  : std_logic;
  signal ctrl_rf2_iqdac_qgain_arm_wack  : std_logic;
  signal ctrl_rf1_iqdac_ctrl_reg        : std_logic_vector(15 downto 0);
  signal ctrl_rf1_iqdac_ctrl_wreq       : std_logic;
  signal ctrl_rf1_iqdac_ctrl_wack       : std_logic;
  signal ctrl_rf2_iqdac_ctrl_reg        : std_logic_vector(15 downto 0);
  signal ctrl_rf2_iqdac_ctrl_wreq       : std_logic;
  signal ctrl_rf2_iqdac_ctrl_wack       : std_logic;
  signal ctrl_iqdac_ram_addr_reg        : std_logic_vector(15 downto 0);
  signal ctrl_iqdac_ram_addr_wreq       : std_logic;
  signal ctrl_iqdac_ram_addr_wack       : std_logic;
  signal ctrl_iqdac_ram_data_reg        : std_logic_vector(15 downto 0);
  signal ctrl_iqdac_ram_data_wreq       : std_logic;
  signal ctrl_iqdac_ram_data_wack       : std_logic;
  signal ctrl_iqdac_ram_write_reg       : std_logic_vector(15 downto 0);
  signal ctrl_iqdac_ram_write_wreq      : std_logic;
  signal ctrl_iqdac_ram_write_wack      : std_logic;
  signal ctrl_iqdac_ram_play_reg        : std_logic_vector(15 downto 0);
  signal ctrl_iqdac_ram_play_wreq       : std_logic;
  signal ctrl_iqdac_ram_play_wack       : std_logic;
  signal ctrl_rf1_dds_ftw_valid_reg     : std_logic_vector(15 downto 0);
  signal ctrl_rf1_dds_ftw_valid_wreq    : std_logic;
  signal ctrl_rf1_dds_ftw_valid_wack    : std_logic;
  signal ctrl_rf1_dds_ftw_reg           : std_logic_vector(63 downto 0);
  signal ctrl_rf1_dds_ftw_wreq          : std_logic_vector(3 downto 0);
  signal ctrl_rf1_dds_ftw_wack          : std_logic_vector(3 downto 0);
  signal ctrl_rf2_dds_ftw_valid_reg     : std_logic_vector(15 downto 0);
  signal ctrl_rf2_dds_ftw_valid_wreq    : std_logic;
  signal ctrl_rf2_dds_ftw_valid_wack    : std_logic;
  signal ctrl_rf2_dds_ftw_reg           : std_logic_vector(63 downto 0);
  signal ctrl_rf2_dds_ftw_wreq          : std_logic_vector(3 downto 0);
  signal ctrl_rf2_dds_ftw_wack          : std_logic_vector(3 downto 0);
  signal ctrl_nco_reset_ctrl_mask_dds_reg : std_logic;
  signal ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg : std_logic;
  signal ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg : std_logic;
  signal ctrl_nco_reset_ctrl_mask_rf1_trig1_reg : std_logic;
  signal ctrl_nco_reset_ctrl_mask_rf2_trig1_reg : std_logic;
  signal ctrl_nco_reset_ctrl_soft_reg   : std_logic;
  signal ctrl_nco_reset_ctrl_wreq       : std_logic;
  signal ctrl_nco_reset_ctrl_wack       : std_logic;
  signal ctrl_gbl_status_rf1_t1_start_reg : std_logic;
  signal ctrl_gbl_status_rf1_t2_start_reg : std_logic;
  signal ctrl_gbl_status_rf2_t1_start_reg : std_logic;
  signal ctrl_gbl_status_rf2_t2_start_reg : std_logic;
  signal ctrl_gbl_status_wreq           : std_logic;
  signal ctrl_gbl_status_wack           : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(15 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(14 downto 1);
  signal wr_dat_d0                      : std_logic_vector(15 downto 0);
  signal wr_sel_d0                      : std_logic_vector(1 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(14 downto 1);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat(15 downto 0) <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat(15 downto 0);
        wr_sel_d0 <= wb_i.sel(1 downto 0);
      end if;
    end if;
  end process;

  -- Register init_hwinfo_stdVersion

  -- Register init_hwinfo_serialNumber

  -- Register init_hwinfo_ident

  -- Register init_hwinfo_firmwareVersion

  -- Register init_hwinfo_memMapVersion

  -- Register init_hwinfo_echo
  init_hwinfo_echo_echo_o <= init_hwinfo_echo_echo_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_hwinfo_echo_echo_reg <= "00000000";
        init_hwinfo_echo_wack <= (others => '0');
      else
        if init_hwinfo_echo_wreq(0) = '1' then
          init_hwinfo_echo_echo_reg <= wr_dat_d0(7 downto 0);
        end if;
        init_hwinfo_echo_wack <= init_hwinfo_echo_wreq;
      end if;
    end if;
  end process;

  -- Register init_hwinfo_setStandard

  -- Interface init_fw_update
  init_fw_update_tr <= init_fw_update_wt or init_fw_update_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_fw_update_rt <= '0';
        init_fw_update_wt <= '0';
      else
        init_fw_update_rt <= (init_fw_update_rt or init_fw_update_re) and not init_fw_update_rack;
        init_fw_update_wt <= (init_fw_update_wt or init_fw_update_we) and not init_fw_update_wack;
      end if;
    end if;
  end process;
  init_fw_update_o.cyc <= init_fw_update_tr;
  init_fw_update_o.stb <= init_fw_update_tr;
  init_fw_update_wack <= init_fw_update_i.ack and init_fw_update_wt;
  init_fw_update_rack <= init_fw_update_i.ack and init_fw_update_rt;
  init_fw_update_o.adr <= ((30 downto 0 => '0') & adr_int(0 downto 1)) & (0 downto 0 => '0');
  init_fw_update_o.sel(1 downto 0) <= wr_sel_d0;
  init_fw_update_o.we <= init_fw_update_wt;
  init_fw_update_o.dat(15 downto 0) <= wr_dat_d0;

  -- Register init_reconfigure
  init_reconfigure_o <= wr_dat_d0;
  init_reconfigure_wr_o <= init_reconfigure_wreq;

  -- Register init_clock_ctrl
  init_clock_ctrl_clk_sel_o <= init_clock_ctrl_clk_sel_reg;
  init_clock_ctrl_mmcm_reset_o <= init_clock_ctrl_mmcm_reset_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_clock_ctrl_clk_sel_reg <= '0';
        init_clock_ctrl_mmcm_reset_reg <= '1';
        init_clock_ctrl_wack <= '0';
      else
        if init_clock_ctrl_wreq = '1' then
          init_clock_ctrl_clk_sel_reg <= wr_dat_d0(0);
          init_clock_ctrl_mmcm_reset_reg <= wr_dat_d0(1);
        end if;
        init_clock_ctrl_wack <= init_clock_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_wrcore_ctrl
  init_wrcore_ctrl_reset_n_o <= init_wrcore_ctrl_reset_n_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_wrcore_ctrl_reset_n_reg <= '0';
        init_wrcore_ctrl_wack <= '0';
      else
        if init_wrcore_ctrl_wreq = '1' then
          init_wrcore_ctrl_reset_n_reg <= wr_dat_d0(0);
        end if;
        init_wrcore_ctrl_wack <= init_wrcore_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_iodelay_ctrl
  init_iodelay_ctrl_reset_o <= init_iodelay_ctrl_reset_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_iodelay_ctrl_reset_reg <= '1';
        init_iodelay_ctrl_wack <= '0';
      else
        if init_iodelay_ctrl_wreq = '1' then
          init_iodelay_ctrl_reset_reg <= wr_dat_d0(0);
        end if;
        init_iodelay_ctrl_wack <= init_iodelay_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_mmcm_shift
  init_mmcm_shift_incdec_o <= init_mmcm_shift_incdec_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_mmcm_shift_incdec_reg <= '0';
        init_mmcm_shift_wack <= '0';
      else
        if init_mmcm_shift_wreq = '1' then
          init_mmcm_shift_incdec_reg <= wr_dat_d0(0);
        end if;
        init_mmcm_shift_wack <= init_mmcm_shift_wreq;
      end if;
    end if;
  end process;
  init_mmcm_shift_wr_o <= init_mmcm_shift_wack;

  -- Register init_clock_status

  -- Register init_tmg
  init_tmg_io_term_o <= init_tmg_io_term_reg;
  init_tmg_io_oe_o <= init_tmg_io_oe_reg;
  init_tmg_clk_term_o <= init_tmg_clk_term_reg;
  init_tmg_clk_oe_o <= init_tmg_clk_oe_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmg_io_term_reg <= "0000";
        init_tmg_io_oe_reg <= "0000";
        init_tmg_clk_term_reg <= "00";
        init_tmg_clk_oe_reg <= "00";
        init_tmg_wack <= '0';
      else
        if init_tmg_wreq = '1' then
          init_tmg_io_term_reg <= wr_dat_d0(3 downto 0);
          init_tmg_io_oe_reg <= wr_dat_d0(7 downto 4);
          init_tmg_clk_term_reg <= wr_dat_d0(9 downto 8);
          init_tmg_clk_oe_reg <= wr_dat_d0(11 downto 10);
        end if;
        init_tmg_wack <= init_tmg_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf1_t1_start
  init_lemo_rf1_t1_start_sel_o <= init_lemo_rf1_t1_start_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf1_t1_start_sel_reg <= "000000";
        init_lemo_rf1_t1_start_wack <= '0';
      else
        if init_lemo_rf1_t1_start_wreq = '1' then
          init_lemo_rf1_t1_start_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf1_t1_start_wack <= init_lemo_rf1_t1_start_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf1_t2_start
  init_lemo_rf1_t2_start_sel_o <= init_lemo_rf1_t2_start_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf1_t2_start_sel_reg <= "000000";
        init_lemo_rf1_t2_start_wack <= '0';
      else
        if init_lemo_rf1_t2_start_wreq = '1' then
          init_lemo_rf1_t2_start_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf1_t2_start_wack <= init_lemo_rf1_t2_start_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf2_t1_start
  init_lemo_rf2_t1_start_sel_o <= init_lemo_rf2_t1_start_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf2_t1_start_sel_reg <= "000000";
        init_lemo_rf2_t1_start_wack <= '0';
      else
        if init_lemo_rf2_t1_start_wreq = '1' then
          init_lemo_rf2_t1_start_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf2_t1_start_wack <= init_lemo_rf2_t1_start_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf2_t2_start
  init_lemo_rf2_t2_start_sel_o <= init_lemo_rf2_t2_start_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf2_t2_start_sel_reg <= "000000";
        init_lemo_rf2_t2_start_wack <= '0';
      else
        if init_lemo_rf2_t2_start_wreq = '1' then
          init_lemo_rf2_t2_start_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf2_t2_start_wack <= init_lemo_rf2_t2_start_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf1_t1_stop
  init_lemo_rf1_t1_stop_sel_o <= init_lemo_rf1_t1_stop_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf1_t1_stop_sel_reg <= "000000";
        init_lemo_rf1_t1_stop_wack <= '0';
      else
        if init_lemo_rf1_t1_stop_wreq = '1' then
          init_lemo_rf1_t1_stop_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf1_t1_stop_wack <= init_lemo_rf1_t1_stop_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf1_t2_stop
  init_lemo_rf1_t2_stop_sel_o <= init_lemo_rf1_t2_stop_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf1_t2_stop_sel_reg <= "000000";
        init_lemo_rf1_t2_stop_wack <= '0';
      else
        if init_lemo_rf1_t2_stop_wreq = '1' then
          init_lemo_rf1_t2_stop_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf1_t2_stop_wack <= init_lemo_rf1_t2_stop_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf2_t1_stop
  init_lemo_rf2_t1_stop_sel_o <= init_lemo_rf2_t1_stop_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf2_t1_stop_sel_reg <= "000000";
        init_lemo_rf2_t1_stop_wack <= '0';
      else
        if init_lemo_rf2_t1_stop_wreq = '1' then
          init_lemo_rf2_t1_stop_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf2_t1_stop_wack <= init_lemo_rf2_t1_stop_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_rf2_t2_stop
  init_lemo_rf2_t2_stop_sel_o <= init_lemo_rf2_t2_stop_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_rf2_t2_stop_sel_reg <= "000000";
        init_lemo_rf2_t2_stop_wack <= '0';
      else
        if init_lemo_rf2_t2_stop_wreq = '1' then
          init_lemo_rf2_t2_stop_sel_reg <= wr_dat_d0(6 downto 1);
        end if;
        init_lemo_rf2_t2_stop_wack <= init_lemo_rf2_t2_stop_wreq;
      end if;
    end if;
  end process;

  -- Register init_tmgio1
  init_tmgio1_osel_o <= init_tmgio1_osel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmgio1_osel_reg <= "00000000000000";
        init_tmgio1_wack <= '0';
      else
        if init_tmgio1_wreq = '1' then
          init_tmgio1_osel_reg <= wr_dat_d0(13 downto 0);
        end if;
        init_tmgio1_wack <= init_tmgio1_wreq;
      end if;
    end if;
  end process;

  -- Register init_tmgio2
  init_tmgio2_osel_o <= init_tmgio2_osel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmgio2_osel_reg <= "00000000000000";
        init_tmgio2_wack <= '0';
      else
        if init_tmgio2_wreq = '1' then
          init_tmgio2_osel_reg <= wr_dat_d0(13 downto 0);
        end if;
        init_tmgio2_wack <= init_tmgio2_wreq;
      end if;
    end if;
  end process;

  -- Register init_tmgio3
  init_tmgio3_osel_o <= init_tmgio3_osel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmgio3_osel_reg <= "00000000000000";
        init_tmgio3_wack <= '0';
      else
        if init_tmgio3_wreq = '1' then
          init_tmgio3_osel_reg <= wr_dat_d0(13 downto 0);
        end if;
        init_tmgio3_wack <= init_tmgio3_wreq;
      end if;
    end if;
  end process;

  -- Register init_tmgio4
  init_tmgio4_osel_o <= init_tmgio4_osel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmgio4_osel_reg <= "00000000000000";
        init_tmgio4_wack <= '0';
      else
        if init_tmgio4_wreq = '1' then
          init_tmgio4_osel_reg <= wr_dat_d0(13 downto 0);
        end if;
        init_tmgio4_wack <= init_tmgio4_wreq;
      end if;
    end if;
  end process;

  -- Register init_tmgclk1
  init_tmgclk1_osel_o <= init_tmgclk1_osel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmgclk1_osel_reg <= "00000000000000";
        init_tmgclk1_wack <= '0';
      else
        if init_tmgclk1_wreq = '1' then
          init_tmgclk1_osel_reg <= wr_dat_d0(13 downto 0);
        end if;
        init_tmgclk1_wack <= init_tmgclk1_wreq;
      end if;
    end if;
  end process;

  -- Register init_tmgclk2
  init_tmgclk2_osel_o <= init_tmgclk2_osel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_tmgclk2_osel_reg <= "00000000000000";
        init_tmgclk2_wack <= '0';
      else
        if init_tmgclk2_wreq = '1' then
          init_tmgclk2_osel_reg <= wr_dat_d0(13 downto 0);
        end if;
        init_tmgclk2_wack <= init_tmgclk2_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo
  init_lemo_gpio_o <= init_lemo_gpio_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_gpio_reg <= "00";
        init_lemo_wack <= '0';
      else
        if init_lemo_wreq = '1' then
          init_lemo_gpio_reg <= wr_dat_d0(1 downto 0);
        end if;
        init_lemo_wack <= init_lemo_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_ext
  init_lemo_ext_sel_o <= init_lemo_ext_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_ext_sel_reg <= "000000";
        init_lemo_ext_wack <= '0';
      else
        if init_lemo_ext_wreq = '1' then
          init_lemo_ext_sel_reg <= wr_dat_d0(5 downto 0);
        end if;
        init_lemo_ext_wack <= init_lemo_ext_wreq;
      end if;
    end if;
  end process;

  -- Register init_softstart
  init_softstart_sel_o <= init_softstart_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_softstart_sel_reg <= "0000";
        init_softstart_wack <= '0';
      else
        if init_softstart_wreq = '1' then
          init_softstart_sel_reg <= wr_dat_d0(3 downto 0);
        end if;
        init_softstart_wack <= init_softstart_wreq;
      end if;
    end if;
  end process;

  -- Register init_softstop
  init_softstop_sel_o <= init_softstop_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_softstop_sel_reg <= "0000";
        init_softstop_wack <= '0';
      else
        if init_softstop_wreq = '1' then
          init_softstop_sel_reg <= wr_dat_d0(3 downto 0);
        end if;
        init_softstop_wack <= init_softstop_wreq;
      end if;
    end if;
  end process;

  -- Register init_lemo_pulse
  init_lemo_pulse_ext_o <= init_lemo_pulse_ext_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_lemo_pulse_ext_reg <= "000000";
        init_lemo_pulse_wack <= '0';
      else
        if init_lemo_pulse_wreq = '1' then
          init_lemo_pulse_ext_reg <= wr_dat_d0(5 downto 0);
        end if;
        init_lemo_pulse_wack <= init_lemo_pulse_wreq;
      end if;
    end if;
  end process;

  -- Register init_pin_ctrl
  init_pin_ctrl_ext_10m_dir_o <= init_pin_ctrl_ext_10m_dir_reg;
  init_pin_ctrl_ext_pps_dir_o <= init_pin_ctrl_ext_pps_dir_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_pin_ctrl_ext_10m_dir_reg <= '1';
        init_pin_ctrl_ext_pps_dir_reg <= '1';
        init_pin_ctrl_wack <= '0';
      else
        if init_pin_ctrl_wreq = '1' then
          init_pin_ctrl_ext_10m_dir_reg <= wr_dat_d0(0);
          init_pin_ctrl_ext_pps_dir_reg <= wr_dat_d0(1);
        end if;
        init_pin_ctrl_wack <= init_pin_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_pll_status

  -- Register init_pll_ctrl
  init_pll_ctrl_sync_o <= init_pll_ctrl_sync_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_pll_ctrl_sync_reg <= '0';
        init_pll_ctrl_wack <= '0';
      else
        if init_pll_ctrl_wreq = '1' then
          init_pll_ctrl_sync_reg <= wr_dat_d0(0);
        end if;
        init_pll_ctrl_wack <= init_pll_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_dds_ctrl
  init_dds_ctrl_reset_o <= init_dds_ctrl_reset_reg;
  init_dds_ctrl_ioupdate_o <= init_dds_ctrl_ioupdate_reg;
  init_dds_ctrl_profile_o <= init_dds_ctrl_profile_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_dds_ctrl_reset_reg <= '0';
        init_dds_ctrl_ioupdate_reg <= '0';
        init_dds_ctrl_profile_reg <= "000";
        init_dds_ctrl_wack <= '0';
      else
        if init_dds_ctrl_wreq = '1' then
          init_dds_ctrl_reset_reg <= wr_dat_d0(0);
          init_dds_ctrl_ioupdate_reg <= wr_dat_d0(3);
          init_dds_ctrl_profile_reg <= wr_dat_d0(6 downto 4);
        else
          init_dds_ctrl_ioupdate_reg <= '0';
        end if;
        init_dds_ctrl_wack <= init_dds_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_dds_ioupdate
  init_dds_ioupdate_fdelay_o <= init_dds_ioupdate_fdelay_reg;
  init_dds_ioupdate_odelay_o <= init_dds_ioupdate_odelay_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_dds_ioupdate_fdelay_reg <= "0000";
        init_dds_ioupdate_odelay_reg <= "00000";
        init_dds_ioupdate_wack <= '0';
      else
        if init_dds_ioupdate_wreq = '1' then
          init_dds_ioupdate_fdelay_reg <= wr_dat_d0(3 downto 0);
          init_dds_ioupdate_odelay_reg <= wr_dat_d0(8 downto 4);
        end if;
        init_dds_ioupdate_wack <= init_dds_ioupdate_wreq;
      end if;
    end if;
  end process;

  -- Register init_dds_status

  -- Register init_ocxo_ctrl
  init_ocxo_ctrl_enable_o <= init_ocxo_ctrl_enable_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_ocxo_ctrl_enable_reg <= '0';
        init_ocxo_ctrl_wack <= '0';
      else
        if init_ocxo_ctrl_wreq = '1' then
          init_ocxo_ctrl_enable_reg <= wr_dat_d0(0);
        end if;
        init_ocxo_ctrl_wack <= init_ocxo_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_ocxo_uptime

  -- Register init_nco_azimuthal
  init_nco_azimuthal_value_o <= init_nco_azimuthal_value_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_azimuthal_value_reg <= "000000000000000000000000000000000000000000000000";
        init_nco_azimuthal_wack <= (others => '0');
      else
        if init_nco_azimuthal_wreq(0) = '1' then
          init_nco_azimuthal_value_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_nco_azimuthal_wreq(1) = '1' then
          init_nco_azimuthal_value_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_nco_azimuthal_wreq(2) = '1' then
          init_nco_azimuthal_value_reg(47 downto 32) <= wr_dat_d0;
        end if;
        init_nco_azimuthal_wack <= init_nco_azimuthal_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_cabledelay
  init_nco_cabledelay_value_o <= init_nco_cabledelay_value_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_cabledelay_value_reg <= "000000000000000000000000000000000000000000000000";
        init_nco_cabledelay_wack <= (others => '0');
      else
        if init_nco_cabledelay_wreq(0) = '1' then
          init_nco_cabledelay_value_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_nco_cabledelay_wreq(1) = '1' then
          init_nco_cabledelay_value_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_nco_cabledelay_wreq(2) = '1' then
          init_nco_cabledelay_value_reg(47 downto 32) <= wr_dat_d0;
        end if;
        init_nco_cabledelay_wack <= init_nco_cabledelay_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_hb
  init_nco_hb_value_o <= init_nco_hb_value_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_hb_value_reg <= "1110011100";
        init_nco_hb_wack <= '0';
      else
        if init_nco_hb_wreq = '1' then
          init_nco_hb_value_reg <= wr_dat_d0(9 downto 0);
        end if;
        init_nco_hb_wack <= init_nco_hb_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_h1_ftw
  init_nco_h1_ftw_value_o <= init_nco_h1_ftw_value_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_h1_ftw_value_reg <= "000000000001011010000111000000010010110010000100";
        init_nco_h1_ftw_wack <= (others => '0');
      else
        if init_nco_h1_ftw_wreq(0) = '1' then
          init_nco_h1_ftw_value_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_nco_h1_ftw_wreq(1) = '1' then
          init_nco_h1_ftw_value_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_nco_h1_ftw_wreq(2) = '1' then
          init_nco_h1_ftw_value_reg(47 downto 32) <= wr_dat_d0;
        end if;
        init_nco_h1_ftw_wack <= init_nco_h1_ftw_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_h1_prog
  init_nco_h1_prog_value_o <= init_nco_h1_prog_value_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_h1_prog_value_reg <= "000000000000000000000000000000000000000000000000";
        init_nco_h1_prog_wack <= (others => '0');
      else
        if init_nco_h1_prog_wreq(0) = '1' then
          init_nco_h1_prog_value_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_nco_h1_prog_wreq(1) = '1' then
          init_nco_h1_prog_value_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_nco_h1_prog_wreq(2) = '1' then
          init_nco_h1_prog_value_reg(47 downto 32) <= wr_dat_d0;
        end if;
        init_nco_h1_prog_wack <= init_nco_h1_prog_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_ctrl
  init_nco_ctrl_reset_nco_o <= init_nco_ctrl_reset_nco_reg;
  init_nco_ctrl_reset_slip_o <= init_nco_ctrl_reset_slip_reg;
  init_nco_ctrl_reset_fsk_o <= init_nco_ctrl_reset_fsk_reg;
  init_nco_ctrl_rate_o <= init_nco_ctrl_rate_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_ctrl_reset_nco_reg <= '1';
        init_nco_ctrl_reset_slip_reg <= '1';
        init_nco_ctrl_reset_fsk_reg <= '1';
        init_nco_ctrl_rate_reg <= "000";
        init_nco_ctrl_wack <= '0';
      else
        if init_nco_ctrl_wreq = '1' then
          init_nco_ctrl_reset_nco_reg <= wr_dat_d0(0);
          init_nco_ctrl_reset_slip_reg <= wr_dat_d0(1);
          init_nco_ctrl_reset_fsk_reg <= wr_dat_d0(2);
          init_nco_ctrl_rate_reg <= wr_dat_d0(6 downto 4);
        end if;
        init_nco_ctrl_wack <= init_nco_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_update
  init_nco_update_valid_o <= init_nco_update_valid_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_update_valid_reg <= '0';
        init_nco_update_wack <= '0';
      else
        if init_nco_update_wreq = '1' then
          init_nco_update_valid_reg <= wr_dat_d0(0);
        else
          init_nco_update_valid_reg <= '0';
        end if;
        init_nco_update_wack <= init_nco_update_wreq;
      end if;
    end if;
  end process;

  -- Register init_nco_loc_or_wrs
  init_nco_loc_or_wrs_params_sel_o <= init_nco_loc_or_wrs_params_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_nco_loc_or_wrs_params_sel_reg <= '1';
        init_nco_loc_or_wrs_wack <= '0';
      else
        if init_nco_loc_or_wrs_wreq = '1' then
          init_nco_loc_or_wrs_params_sel_reg <= wr_dat_d0(0);
        end if;
        init_nco_loc_or_wrs_wack <= init_nco_loc_or_wrs_wreq;
      end if;
    end if;
  end process;

  -- Register init_svec_mup_ctrl
  init_svec_mup_ctrl_gpio_sel_o <= init_svec_mup_ctrl_gpio_sel_reg;
  init_svec_mup_ctrl_led_sel_o <= init_svec_mup_ctrl_led_sel_reg;
  init_svec_mup_ctrl_bclk_rfclk_sel_o <= init_svec_mup_ctrl_bclk_rfclk_sel_reg;
  init_svec_mup_ctrl_ila_sel_o <= init_svec_mup_ctrl_ila_sel_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_svec_mup_ctrl_gpio_sel_reg <= "0000";
        init_svec_mup_ctrl_led_sel_reg <= "0000";
        init_svec_mup_ctrl_bclk_rfclk_sel_reg <= '1';
        init_svec_mup_ctrl_ila_sel_reg <= '1';
        init_svec_mup_ctrl_wack <= '0';
      else
        if init_svec_mup_ctrl_wreq = '1' then
          init_svec_mup_ctrl_gpio_sel_reg <= wr_dat_d0(3 downto 0);
          init_svec_mup_ctrl_led_sel_reg <= wr_dat_d0(7 downto 4);
          init_svec_mup_ctrl_bclk_rfclk_sel_reg <= wr_dat_d0(8);
          init_svec_mup_ctrl_ila_sel_reg <= wr_dat_d0(9);
        end if;
        init_svec_mup_ctrl_wack <= init_svec_mup_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register init_svec_mup_rftrig
  init_svec_mup_rftrig_t1stop_o <= init_svec_mup_rftrig_t1stop_reg;
  init_svec_mup_rftrig_t1start_o <= init_svec_mup_rftrig_t1start_reg;
  init_svec_mup_rftrig_t2stop_o <= init_svec_mup_rftrig_t2stop_reg;
  init_svec_mup_rftrig_t2start_o <= init_svec_mup_rftrig_t2start_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_svec_mup_rftrig_t1stop_reg <= '0';
        init_svec_mup_rftrig_t1start_reg <= '1';
        init_svec_mup_rftrig_t2stop_reg <= '0';
        init_svec_mup_rftrig_t2start_reg <= '1';
        init_svec_mup_rftrig_wack <= '0';
      else
        if init_svec_mup_rftrig_wreq = '1' then
          init_svec_mup_rftrig_t1stop_reg <= wr_dat_d0(0);
          init_svec_mup_rftrig_t1start_reg <= wr_dat_d0(1);
          init_svec_mup_rftrig_t2stop_reg <= wr_dat_d0(2);
          init_svec_mup_rftrig_t2start_reg <= wr_dat_d0(3);
        end if;
        init_svec_mup_rftrig_wack <= init_svec_mup_rftrig_wreq;
      end if;
    end if;
  end process;

  -- Register init_svec_mup_fmc1
  init_svec_mup_fmc1_term_o <= init_svec_mup_fmc1_term_reg;
  init_svec_mup_fmc1_oe_n_o <= init_svec_mup_fmc1_oe_n_reg;
  init_svec_mup_fmc1_led_o <= init_svec_mup_fmc1_led_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_svec_mup_fmc1_term_reg <= "11001";
        init_svec_mup_fmc1_oe_n_reg <= "11001";
        init_svec_mup_fmc1_led_reg <= "01";
        init_svec_mup_fmc1_wack <= '0';
      else
        if init_svec_mup_fmc1_wreq = '1' then
          init_svec_mup_fmc1_term_reg <= wr_dat_d0(4 downto 0);
          init_svec_mup_fmc1_oe_n_reg <= wr_dat_d0(9 downto 5);
          init_svec_mup_fmc1_led_reg <= wr_dat_d0(11 downto 10);
        end if;
        init_svec_mup_fmc1_wack <= init_svec_mup_fmc1_wreq;
      end if;
    end if;
  end process;

  -- Register init_svec_mup_fmc2
  init_svec_mup_fmc2_term_o <= init_svec_mup_fmc2_term_reg;
  init_svec_mup_fmc2_oe_n_o <= init_svec_mup_fmc2_oe_n_reg;
  init_svec_mup_fmc2_led_o <= init_svec_mup_fmc2_led_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_svec_mup_fmc2_term_reg <= "00101";
        init_svec_mup_fmc2_oe_n_reg <= "00101";
        init_svec_mup_fmc2_led_reg <= "01";
        init_svec_mup_fmc2_wack <= '0';
      else
        if init_svec_mup_fmc2_wreq = '1' then
          init_svec_mup_fmc2_term_reg <= wr_dat_d0(4 downto 0);
          init_svec_mup_fmc2_oe_n_reg <= wr_dat_d0(9 downto 5);
          init_svec_mup_fmc2_led_reg <= wr_dat_d0(11 downto 10);
        end if;
        init_svec_mup_fmc2_wack <= init_svec_mup_fmc2_wreq;
      end if;
    end if;
  end process;

  -- Register init_wrs_rxframe_ftw

  -- Register init_wrs_rxframe_ctrl

  -- Register init_wrs_rxframe_counter

  -- Register init_wrs_rxframe_rxwrtimestamp

  -- Register init_wrs_rxframe_txwrtimestamp

  -- Register init_wrs_rxframe_rftimestamp

  -- Register init_wrs_rxframe_rfframe_ts
  init_wrs_rxframe_rfframe_ts_update_o <= init_wrs_rxframe_rfframe_ts_update_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_wrs_rxframe_rfframe_ts_update_reg <= '0';
        init_wrs_rxframe_rfframe_ts_wack <= '0';
      else
        if init_wrs_rxframe_rfframe_ts_wreq = '1' then
          init_wrs_rxframe_rfframe_ts_update_reg <= wr_dat_d0(0);
        else
          init_wrs_rxframe_rfframe_ts_update_reg <= '0';
        end if;
        init_wrs_rxframe_rfframe_ts_wack <= init_wrs_rxframe_rfframe_ts_wreq;
      end if;
    end if;
  end process;

  -- Register init_wrs_rxframe_nco_reset_tai

  -- Register init_wrs_rxframe_nco_reset_cycles

  -- Register init_wrs_rxframe_tai

  -- Register init_wrs_rxframe_cycles

  -- Register init_wrc_tai

  -- Register init_wrc_cycles

  -- Register init_wrc_status

  -- Register init_wrc_page0
  init_wrc_page0_o <= init_wrc_page0_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_wrc_page0_reg <= "00000000000001000000000000000000";
        init_wrc_page0_wack <= (others => '0');
      else
        if init_wrc_page0_wreq(0) = '1' then
          init_wrc_page0_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_wrc_page0_wreq(1) = '1' then
          init_wrc_page0_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_wrc_page0_wack <= init_wrc_page0_wreq;
      end if;
    end if;
  end process;

  -- Register init_wrc_page1
  init_wrc_page1_o <= init_wrc_page1_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_wrc_page1_reg <= "00000000000000000000000000000000";
        init_wrc_page1_wack <= (others => '0');
      else
        if init_wrc_page1_wreq(0) = '1' then
          init_wrc_page1_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_wrc_page1_wreq(1) = '1' then
          init_wrc_page1_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_wrc_page1_wack <= init_wrc_page1_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_ftw_h1_main
  init_txframe_ftw_h1_main_o <= init_txframe_ftw_h1_main_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_ftw_h1_main_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        init_txframe_ftw_h1_main_wack <= (others => '0');
      else
        if init_txframe_ftw_h1_main_wreq(0) = '1' then
          init_txframe_ftw_h1_main_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_main_wreq(1) = '1' then
          init_txframe_ftw_h1_main_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_main_wreq(2) = '1' then
          init_txframe_ftw_h1_main_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_main_wreq(3) = '1' then
          init_txframe_ftw_h1_main_reg(63 downto 48) <= wr_dat_d0;
        end if;
        init_txframe_ftw_h1_main_wack <= init_txframe_ftw_h1_main_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_ftw_h1_prog
  init_txframe_ftw_h1_prog_o <= init_txframe_ftw_h1_prog_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_ftw_h1_prog_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        init_txframe_ftw_h1_prog_wack <= (others => '0');
      else
        if init_txframe_ftw_h1_prog_wreq(0) = '1' then
          init_txframe_ftw_h1_prog_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_prog_wreq(1) = '1' then
          init_txframe_ftw_h1_prog_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_prog_wreq(2) = '1' then
          init_txframe_ftw_h1_prog_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_prog_wreq(3) = '1' then
          init_txframe_ftw_h1_prog_reg(63 downto 48) <= wr_dat_d0;
        end if;
        init_txframe_ftw_h1_prog_wack <= init_txframe_ftw_h1_prog_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_ftw_h1_on
  init_txframe_ftw_h1_on_o <= init_txframe_ftw_h1_on_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_ftw_h1_on_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        init_txframe_ftw_h1_on_wack <= (others => '0');
      else
        if init_txframe_ftw_h1_on_wreq(0) = '1' then
          init_txframe_ftw_h1_on_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_on_wreq(1) = '1' then
          init_txframe_ftw_h1_on_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_on_wreq(2) = '1' then
          init_txframe_ftw_h1_on_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if init_txframe_ftw_h1_on_wreq(3) = '1' then
          init_txframe_ftw_h1_on_reg(63 downto 48) <= wr_dat_d0;
        end if;
        init_txframe_ftw_h1_on_wack <= init_txframe_ftw_h1_on_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_dftw_h1_slip1
  init_txframe_dftw_h1_slip1_o <= init_txframe_dftw_h1_slip1_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_dftw_h1_slip1_reg <= "00000000000000000000000000000000";
        init_txframe_dftw_h1_slip1_wack <= (others => '0');
      else
        if init_txframe_dftw_h1_slip1_wreq(0) = '1' then
          init_txframe_dftw_h1_slip1_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_dftw_h1_slip1_wreq(1) = '1' then
          init_txframe_dftw_h1_slip1_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_dftw_h1_slip1_wack <= init_txframe_dftw_h1_slip1_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_dftw_h1_slip2
  init_txframe_dftw_h1_slip2_o <= init_txframe_dftw_h1_slip2_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_dftw_h1_slip2_reg <= "00000000000000000000000000000000";
        init_txframe_dftw_h1_slip2_wack <= (others => '0');
      else
        if init_txframe_dftw_h1_slip2_wreq(0) = '1' then
          init_txframe_dftw_h1_slip2_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_dftw_h1_slip2_wreq(1) = '1' then
          init_txframe_dftw_h1_slip2_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_dftw_h1_slip2_wack <= init_txframe_dftw_h1_slip2_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint1
  init_txframe_setpoint1_o <= init_txframe_setpoint1_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint1_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint1_wack <= (others => '0');
      else
        if init_txframe_setpoint1_wreq(0) = '1' then
          init_txframe_setpoint1_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint1_wreq(1) = '1' then
          init_txframe_setpoint1_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint1_wack <= init_txframe_setpoint1_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint2
  init_txframe_setpoint2_o <= init_txframe_setpoint2_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint2_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint2_wack <= (others => '0');
      else
        if init_txframe_setpoint2_wreq(0) = '1' then
          init_txframe_setpoint2_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint2_wreq(1) = '1' then
          init_txframe_setpoint2_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint2_wack <= init_txframe_setpoint2_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint3
  init_txframe_setpoint3_o <= init_txframe_setpoint3_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint3_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint3_wack <= (others => '0');
      else
        if init_txframe_setpoint3_wreq(0) = '1' then
          init_txframe_setpoint3_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint3_wreq(1) = '1' then
          init_txframe_setpoint3_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint3_wack <= init_txframe_setpoint3_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint4
  init_txframe_setpoint4_o <= init_txframe_setpoint4_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint4_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint4_wack <= (others => '0');
      else
        if init_txframe_setpoint4_wreq(0) = '1' then
          init_txframe_setpoint4_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint4_wreq(1) = '1' then
          init_txframe_setpoint4_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint4_wack <= init_txframe_setpoint4_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint5
  init_txframe_setpoint5_o <= init_txframe_setpoint5_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint5_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint5_wack <= (others => '0');
      else
        if init_txframe_setpoint5_wreq(0) = '1' then
          init_txframe_setpoint5_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint5_wreq(1) = '1' then
          init_txframe_setpoint5_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint5_wack <= init_txframe_setpoint5_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint6
  init_txframe_setpoint6_o <= init_txframe_setpoint6_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint6_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint6_wack <= (others => '0');
      else
        if init_txframe_setpoint6_wreq(0) = '1' then
          init_txframe_setpoint6_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint6_wreq(1) = '1' then
          init_txframe_setpoint6_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint6_wack <= init_txframe_setpoint6_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint7
  init_txframe_setpoint7_o <= init_txframe_setpoint7_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint7_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint7_wack <= (others => '0');
      else
        if init_txframe_setpoint7_wreq(0) = '1' then
          init_txframe_setpoint7_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint7_wreq(1) = '1' then
          init_txframe_setpoint7_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint7_wack <= init_txframe_setpoint7_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_setpoint8
  init_txframe_setpoint8_o <= init_txframe_setpoint8_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_setpoint8_reg <= "00000000000000000000000000000000";
        init_txframe_setpoint8_wack <= (others => '0');
      else
        if init_txframe_setpoint8_wreq(0) = '1' then
          init_txframe_setpoint8_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_setpoint8_wreq(1) = '1' then
          init_txframe_setpoint8_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_setpoint8_wack <= init_txframe_setpoint8_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_noise
  init_txframe_noise_o <= init_txframe_noise_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_noise_reg <= "00000000000000000000000000000000";
        init_txframe_noise_wack <= (others => '0');
      else
        if init_txframe_noise_wreq(0) = '1' then
          init_txframe_noise_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if init_txframe_noise_wreq(1) = '1' then
          init_txframe_noise_reg(31 downto 16) <= wr_dat_d0;
        end if;
        init_txframe_noise_wack <= init_txframe_noise_wreq;
      end if;
    end if;
  end process;

  -- Register init_txframe_control
  init_txframe_control_o <= init_txframe_control_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_txframe_control_reg <= "0000000000000000";
        init_txframe_control_wack <= '0';
      else
        if init_txframe_control_wreq = '1' then
          init_txframe_control_reg <= wr_dat_d0;
        end if;
        init_txframe_control_wack <= init_txframe_control_wreq;
      end if;
    end if;
  end process;

  -- Interface init_pll_spi
  init_pll_spi_tr <= init_pll_spi_wt or init_pll_spi_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_pll_spi_rt <= '0';
        init_pll_spi_wt <= '0';
      else
        init_pll_spi_rt <= (init_pll_spi_rt or init_pll_spi_re) and not init_pll_spi_rack;
        init_pll_spi_wt <= (init_pll_spi_wt or init_pll_spi_we) and not init_pll_spi_wack;
      end if;
    end if;
  end process;
  init_pll_spi_o.cyc <= init_pll_spi_tr;
  init_pll_spi_o.stb <= init_pll_spi_tr;
  init_pll_spi_wack <= init_pll_spi_i.ack and init_pll_spi_wt;
  init_pll_spi_rack <= init_pll_spi_i.ack and init_pll_spi_rt;
  init_pll_spi_o.adr <= ((26 downto 0 => '0') & adr_int(4 downto 1)) & (0 downto 0 => '0');
  init_pll_spi_o.sel(1 downto 0) <= wr_sel_d0;
  init_pll_spi_o.we <= init_pll_spi_wt;
  init_pll_spi_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface init_rf_spi
  init_rf_spi_tr <= init_rf_spi_wt or init_rf_spi_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_rf_spi_rt <= '0';
        init_rf_spi_wt <= '0';
      else
        init_rf_spi_rt <= (init_rf_spi_rt or init_rf_spi_re) and not init_rf_spi_rack;
        init_rf_spi_wt <= (init_rf_spi_wt or init_rf_spi_we) and not init_rf_spi_wack;
      end if;
    end if;
  end process;
  init_rf_spi_o.cyc <= init_rf_spi_tr;
  init_rf_spi_o.stb <= init_rf_spi_tr;
  init_rf_spi_wack <= init_rf_spi_i.ack and init_rf_spi_wt;
  init_rf_spi_rack <= init_rf_spi_i.ack and init_rf_spi_rt;
  init_rf_spi_o.adr <= ((26 downto 0 => '0') & adr_int(4 downto 1)) & (0 downto 0 => '0');
  init_rf_spi_o.sel(1 downto 0) <= wr_sel_d0;
  init_rf_spi_o.we <= init_rf_spi_wt;
  init_rf_spi_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface init_rf
  init_rf_tr <= init_rf_wt or init_rf_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_rf_rt <= '0';
        init_rf_wt <= '0';
      else
        init_rf_rt <= (init_rf_rt or init_rf_re) and not init_rf_rack;
        init_rf_wt <= (init_rf_wt or init_rf_we) and not init_rf_wack;
      end if;
    end if;
  end process;
  init_rf_o.cyc <= init_rf_tr;
  init_rf_o.stb <= init_rf_tr;
  init_rf_wack <= init_rf_i.ack and init_rf_wt;
  init_rf_rack <= init_rf_i.ack and init_rf_rt;
  init_rf_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 1)) & (0 downto 0 => '0');
  init_rf_o.sel(1 downto 0) <= wr_sel_d0;
  init_rf_o.we <= init_rf_wt;
  init_rf_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface init_framerxtx
  init_framerxtx_tr <= init_framerxtx_wt or init_framerxtx_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_framerxtx_rt <= '0';
        init_framerxtx_wt <= '0';
      else
        init_framerxtx_rt <= (init_framerxtx_rt or init_framerxtx_re) and not init_framerxtx_rack;
        init_framerxtx_wt <= (init_framerxtx_wt or init_framerxtx_we) and not init_framerxtx_wack;
      end if;
    end if;
  end process;
  init_framerxtx_o.cyc <= init_framerxtx_tr;
  init_framerxtx_o.stb <= init_framerxtx_tr;
  init_framerxtx_wack <= init_framerxtx_i.ack and init_framerxtx_wt;
  init_framerxtx_rack <= init_framerxtx_i.ack and init_framerxtx_rt;
  init_framerxtx_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 1)) & (0 downto 0 => '0');
  init_framerxtx_o.sel(1 downto 0) <= wr_sel_d0;
  init_framerxtx_o.we <= init_framerxtx_wt;
  init_framerxtx_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface init_xadc
  init_xadc_tr <= init_xadc_wt or init_xadc_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_xadc_rt <= '0';
        init_xadc_wt <= '0';
      else
        init_xadc_rt <= (init_xadc_rt or init_xadc_re) and not init_xadc_rack;
        init_xadc_wt <= (init_xadc_wt or init_xadc_we) and not init_xadc_wack;
      end if;
    end if;
  end process;
  init_xadc_o.cyc <= init_xadc_tr;
  init_xadc_o.stb <= init_xadc_tr;
  init_xadc_wack <= init_xadc_i.ack and init_xadc_wt;
  init_xadc_rack <= init_xadc_i.ack and init_xadc_rt;
  init_xadc_o.adr <= ((23 downto 0 => '0') & adr_int(7 downto 1)) & (0 downto 0 => '0');
  init_xadc_o.sel(1 downto 0) <= wr_sel_d0;
  init_xadc_o.we <= init_xadc_wt;
  init_xadc_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface init_wrpc
  init_wrpc_tr <= init_wrpc_wt or init_wrpc_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        init_wrpc_rt <= '0';
        init_wrpc_wt <= '0';
      else
        init_wrpc_rt <= (init_wrpc_rt or init_wrpc_re) and not init_wrpc_rack;
        init_wrpc_wt <= (init_wrpc_wt or init_wrpc_we) and not init_wrpc_wack;
      end if;
    end if;
  end process;
  init_wrpc_o.cyc <= init_wrpc_tr;
  init_wrpc_o.stb <= init_wrpc_tr;
  init_wrpc_wack <= init_wrpc_i.ack and init_wrpc_wt;
  init_wrpc_rack <= init_wrpc_i.ack and init_wrpc_rt;
  init_wrpc_o.adr <= ((18 downto 0 => '0') & adr_int(12 downto 1)) & (0 downto 0 => '0');
  init_wrpc_o.sel(1 downto 0) <= wr_sel_d0;
  init_wrpc_o.we <= init_wrpc_wt;
  init_wrpc_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface ctrl_rf1_vtus
  ctrl_rf1_vtus_tr <= ctrl_rf1_vtus_wt or ctrl_rf1_vtus_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_vtus_rt <= '0';
        ctrl_rf1_vtus_wt <= '0';
      else
        ctrl_rf1_vtus_rt <= (ctrl_rf1_vtus_rt or ctrl_rf1_vtus_re) and not ctrl_rf1_vtus_rack;
        ctrl_rf1_vtus_wt <= (ctrl_rf1_vtus_wt or ctrl_rf1_vtus_we) and not ctrl_rf1_vtus_wack;
      end if;
    end if;
  end process;
  ctrl_rf1_vtus_o.cyc <= ctrl_rf1_vtus_tr;
  ctrl_rf1_vtus_o.stb <= ctrl_rf1_vtus_tr;
  ctrl_rf1_vtus_wack <= ctrl_rf1_vtus_i.ack and ctrl_rf1_vtus_wt;
  ctrl_rf1_vtus_rack <= ctrl_rf1_vtus_i.ack and ctrl_rf1_vtus_rt;
  ctrl_rf1_vtus_o.adr <= ((22 downto 0 => '0') & adr_int(8 downto 1)) & (0 downto 0 => '0');
  ctrl_rf1_vtus_o.sel(1 downto 0) <= wr_sel_d0;
  ctrl_rf1_vtus_o.we <= ctrl_rf1_vtus_wt;
  ctrl_rf1_vtus_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface ctrl_rf2_vtus
  ctrl_rf2_vtus_tr <= ctrl_rf2_vtus_wt or ctrl_rf2_vtus_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_vtus_rt <= '0';
        ctrl_rf2_vtus_wt <= '0';
      else
        ctrl_rf2_vtus_rt <= (ctrl_rf2_vtus_rt or ctrl_rf2_vtus_re) and not ctrl_rf2_vtus_rack;
        ctrl_rf2_vtus_wt <= (ctrl_rf2_vtus_wt or ctrl_rf2_vtus_we) and not ctrl_rf2_vtus_wack;
      end if;
    end if;
  end process;
  ctrl_rf2_vtus_o.cyc <= ctrl_rf2_vtus_tr;
  ctrl_rf2_vtus_o.stb <= ctrl_rf2_vtus_tr;
  ctrl_rf2_vtus_wack <= ctrl_rf2_vtus_i.ack and ctrl_rf2_vtus_wt;
  ctrl_rf2_vtus_rack <= ctrl_rf2_vtus_i.ack and ctrl_rf2_vtus_rt;
  ctrl_rf2_vtus_o.adr <= ((22 downto 0 => '0') & adr_int(8 downto 1)) & (0 downto 0 => '0');
  ctrl_rf2_vtus_o.sel(1 downto 0) <= wr_sel_d0;
  ctrl_rf2_vtus_o.we <= ctrl_rf2_vtus_wt;
  ctrl_rf2_vtus_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface ctrl_rf1_rfnco
  ctrl_rf1_rfnco_tr <= ctrl_rf1_rfnco_wt or ctrl_rf1_rfnco_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_rfnco_rt <= '0';
        ctrl_rf1_rfnco_wt <= '0';
      else
        ctrl_rf1_rfnco_rt <= (ctrl_rf1_rfnco_rt or ctrl_rf1_rfnco_re) and not ctrl_rf1_rfnco_rack;
        ctrl_rf1_rfnco_wt <= (ctrl_rf1_rfnco_wt or ctrl_rf1_rfnco_we) and not ctrl_rf1_rfnco_wack;
      end if;
    end if;
  end process;
  ctrl_rf1_rfnco_o.cyc <= ctrl_rf1_rfnco_tr;
  ctrl_rf1_rfnco_o.stb <= ctrl_rf1_rfnco_tr;
  ctrl_rf1_rfnco_wack <= ctrl_rf1_rfnco_i.ack and ctrl_rf1_rfnco_wt;
  ctrl_rf1_rfnco_rack <= ctrl_rf1_rfnco_i.ack and ctrl_rf1_rfnco_rt;
  ctrl_rf1_rfnco_o.adr <= ((19 downto 0 => '0') & adr_int(11 downto 1)) & (0 downto 0 => '0');
  ctrl_rf1_rfnco_o.sel(1 downto 0) <= wr_sel_d0;
  ctrl_rf1_rfnco_o.we <= ctrl_rf1_rfnco_wt;
  ctrl_rf1_rfnco_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface ctrl_rf2_rfnco
  ctrl_rf2_rfnco_tr <= ctrl_rf2_rfnco_wt or ctrl_rf2_rfnco_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_rfnco_rt <= '0';
        ctrl_rf2_rfnco_wt <= '0';
      else
        ctrl_rf2_rfnco_rt <= (ctrl_rf2_rfnco_rt or ctrl_rf2_rfnco_re) and not ctrl_rf2_rfnco_rack;
        ctrl_rf2_rfnco_wt <= (ctrl_rf2_rfnco_wt or ctrl_rf2_rfnco_we) and not ctrl_rf2_rfnco_wack;
      end if;
    end if;
  end process;
  ctrl_rf2_rfnco_o.cyc <= ctrl_rf2_rfnco_tr;
  ctrl_rf2_rfnco_o.stb <= ctrl_rf2_rfnco_tr;
  ctrl_rf2_rfnco_wack <= ctrl_rf2_rfnco_i.ack and ctrl_rf2_rfnco_wt;
  ctrl_rf2_rfnco_rack <= ctrl_rf2_rfnco_i.ack and ctrl_rf2_rfnco_rt;
  ctrl_rf2_rfnco_o.adr <= ((19 downto 0 => '0') & adr_int(11 downto 1)) & (0 downto 0 => '0');
  ctrl_rf2_rfnco_o.sel(1 downto 0) <= wr_sel_d0;
  ctrl_rf2_rfnco_o.we <= ctrl_rf2_rfnco_wt;
  ctrl_rf2_rfnco_o.dat(15 downto 0) <= wr_dat_d0;

  -- Register ctrl_rf1_iqdac_phase
  ctrl_rf1_iqdac_phase_o <= ctrl_rf1_iqdac_phase_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_iqdac_phase_reg <= "0000000000000000";
        ctrl_rf1_iqdac_phase_wack <= '0';
      else
        if ctrl_rf1_iqdac_phase_wreq = '1' then
          ctrl_rf1_iqdac_phase_reg <= wr_dat_d0;
        end if;
        ctrl_rf1_iqdac_phase_wack <= ctrl_rf1_iqdac_phase_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_iqdac_phase
  ctrl_rf2_iqdac_phase_o <= ctrl_rf2_iqdac_phase_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_iqdac_phase_reg <= "0000000000000000";
        ctrl_rf2_iqdac_phase_wack <= '0';
      else
        if ctrl_rf2_iqdac_phase_wreq = '1' then
          ctrl_rf2_iqdac_phase_reg <= wr_dat_d0;
        end if;
        ctrl_rf2_iqdac_phase_wack <= ctrl_rf2_iqdac_phase_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf1_iqdac_phase_update
  ctrl_rf1_iqdac_phase_update_valid_o <= ctrl_rf1_iqdac_phase_update_valid_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_iqdac_phase_update_valid_reg <= '0';
        ctrl_rf1_iqdac_phase_update_wack <= '0';
      else
        if ctrl_rf1_iqdac_phase_update_wreq = '1' then
          ctrl_rf1_iqdac_phase_update_valid_reg <= wr_dat_d0(0);
        else
          ctrl_rf1_iqdac_phase_update_valid_reg <= '0';
        end if;
        ctrl_rf1_iqdac_phase_update_wack <= ctrl_rf1_iqdac_phase_update_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_iqdac_phase_update
  ctrl_rf2_iqdac_phase_update_valid_o <= ctrl_rf2_iqdac_phase_update_valid_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_iqdac_phase_update_valid_reg <= '0';
        ctrl_rf2_iqdac_phase_update_wack <= '0';
      else
        if ctrl_rf2_iqdac_phase_update_wreq = '1' then
          ctrl_rf2_iqdac_phase_update_valid_reg <= wr_dat_d0(0);
        else
          ctrl_rf2_iqdac_phase_update_valid_reg <= '0';
        end if;
        ctrl_rf2_iqdac_phase_update_wack <= ctrl_rf2_iqdac_phase_update_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf1_iqdac_igain_arm
  ctrl_rf1_iqdac_igain_arm_o <= ctrl_rf1_iqdac_igain_arm_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_iqdac_igain_arm_reg <= "0000000000000000";
        ctrl_rf1_iqdac_igain_arm_wack <= '0';
      else
        if ctrl_rf1_iqdac_igain_arm_wreq = '1' then
          ctrl_rf1_iqdac_igain_arm_reg <= wr_dat_d0;
        end if;
        ctrl_rf1_iqdac_igain_arm_wack <= ctrl_rf1_iqdac_igain_arm_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf1_iqdac_qgain_arm
  ctrl_rf1_iqdac_qgain_arm_o <= ctrl_rf1_iqdac_qgain_arm_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_iqdac_qgain_arm_reg <= "0000000000000000";
        ctrl_rf1_iqdac_qgain_arm_wack <= '0';
      else
        if ctrl_rf1_iqdac_qgain_arm_wreq = '1' then
          ctrl_rf1_iqdac_qgain_arm_reg <= wr_dat_d0;
        end if;
        ctrl_rf1_iqdac_qgain_arm_wack <= ctrl_rf1_iqdac_qgain_arm_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_iqdac_igain_arm
  ctrl_rf2_iqdac_igain_arm_o <= ctrl_rf2_iqdac_igain_arm_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_iqdac_igain_arm_reg <= "0000000000000000";
        ctrl_rf2_iqdac_igain_arm_wack <= '0';
      else
        if ctrl_rf2_iqdac_igain_arm_wreq = '1' then
          ctrl_rf2_iqdac_igain_arm_reg <= wr_dat_d0;
        end if;
        ctrl_rf2_iqdac_igain_arm_wack <= ctrl_rf2_iqdac_igain_arm_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_iqdac_qgain_arm
  ctrl_rf2_iqdac_qgain_arm_o <= ctrl_rf2_iqdac_qgain_arm_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_iqdac_qgain_arm_reg <= "0000000000000000";
        ctrl_rf2_iqdac_qgain_arm_wack <= '0';
      else
        if ctrl_rf2_iqdac_qgain_arm_wreq = '1' then
          ctrl_rf2_iqdac_qgain_arm_reg <= wr_dat_d0;
        end if;
        ctrl_rf2_iqdac_qgain_arm_wack <= ctrl_rf2_iqdac_qgain_arm_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf1_iqdac_igain

  -- Register ctrl_rf1_iqdac_qgain

  -- Register ctrl_rf2_iqdac_igain

  -- Register ctrl_rf2_iqdac_qgain

  -- Register ctrl_rf1_iqdac_ctrl
  ctrl_rf1_iqdac_ctrl_o <= ctrl_rf1_iqdac_ctrl_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_iqdac_ctrl_reg <= "0000000000000000";
        ctrl_rf1_iqdac_ctrl_wack <= '0';
      else
        if ctrl_rf1_iqdac_ctrl_wreq = '1' then
          ctrl_rf1_iqdac_ctrl_reg <= wr_dat_d0;
        end if;
        ctrl_rf1_iqdac_ctrl_wack <= ctrl_rf1_iqdac_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_iqdac_ctrl
  ctrl_rf2_iqdac_ctrl_o <= ctrl_rf2_iqdac_ctrl_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_iqdac_ctrl_reg <= "0000000000000000";
        ctrl_rf2_iqdac_ctrl_wack <= '0';
      else
        if ctrl_rf2_iqdac_ctrl_wreq = '1' then
          ctrl_rf2_iqdac_ctrl_reg <= wr_dat_d0;
        end if;
        ctrl_rf2_iqdac_ctrl_wack <= ctrl_rf2_iqdac_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_iqdac_ram_addr
  ctrl_iqdac_ram_addr_o <= ctrl_iqdac_ram_addr_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_iqdac_ram_addr_reg <= "0000000000000000";
        ctrl_iqdac_ram_addr_wack <= '0';
      else
        if ctrl_iqdac_ram_addr_wreq = '1' then
          ctrl_iqdac_ram_addr_reg <= wr_dat_d0;
        end if;
        ctrl_iqdac_ram_addr_wack <= ctrl_iqdac_ram_addr_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_iqdac_ram_data
  ctrl_iqdac_ram_data_o <= ctrl_iqdac_ram_data_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_iqdac_ram_data_reg <= "0000000000000000";
        ctrl_iqdac_ram_data_wack <= '0';
      else
        if ctrl_iqdac_ram_data_wreq = '1' then
          ctrl_iqdac_ram_data_reg <= wr_dat_d0;
        end if;
        ctrl_iqdac_ram_data_wack <= ctrl_iqdac_ram_data_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_iqdac_ram_write
  ctrl_iqdac_ram_write_o <= ctrl_iqdac_ram_write_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_iqdac_ram_write_reg <= "0000000000000000";
        ctrl_iqdac_ram_write_wack <= '0';
      else
        if ctrl_iqdac_ram_write_wreq = '1' then
          ctrl_iqdac_ram_write_reg <= wr_dat_d0;
        end if;
        ctrl_iqdac_ram_write_wack <= ctrl_iqdac_ram_write_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_iqdac_ram_play
  ctrl_iqdac_ram_play_o <= ctrl_iqdac_ram_play_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_iqdac_ram_play_reg <= "0000000000000000";
        ctrl_iqdac_ram_play_wack <= '0';
      else
        if ctrl_iqdac_ram_play_wreq = '1' then
          ctrl_iqdac_ram_play_reg <= wr_dat_d0;
        end if;
        ctrl_iqdac_ram_play_wack <= ctrl_iqdac_ram_play_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf1_dds_ftw_valid
  ctrl_rf1_dds_ftw_valid_o <= ctrl_rf1_dds_ftw_valid_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_dds_ftw_valid_reg <= "0000000000000000";
        ctrl_rf1_dds_ftw_valid_wack <= '0';
      else
        if ctrl_rf1_dds_ftw_valid_wreq = '1' then
          ctrl_rf1_dds_ftw_valid_reg <= wr_dat_d0;
        end if;
        ctrl_rf1_dds_ftw_valid_wack <= ctrl_rf1_dds_ftw_valid_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf1_dds_ftw
  ctrl_rf1_dds_ftw_o <= ctrl_rf1_dds_ftw_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf1_dds_ftw_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        ctrl_rf1_dds_ftw_wack <= (others => '0');
      else
        if ctrl_rf1_dds_ftw_wreq(0) = '1' then
          ctrl_rf1_dds_ftw_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if ctrl_rf1_dds_ftw_wreq(1) = '1' then
          ctrl_rf1_dds_ftw_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if ctrl_rf1_dds_ftw_wreq(2) = '1' then
          ctrl_rf1_dds_ftw_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if ctrl_rf1_dds_ftw_wreq(3) = '1' then
          ctrl_rf1_dds_ftw_reg(63 downto 48) <= wr_dat_d0;
        end if;
        ctrl_rf1_dds_ftw_wack <= ctrl_rf1_dds_ftw_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_dds_ftw_valid
  ctrl_rf2_dds_ftw_valid_o <= ctrl_rf2_dds_ftw_valid_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_dds_ftw_valid_reg <= "0000000000000000";
        ctrl_rf2_dds_ftw_valid_wack <= '0';
      else
        if ctrl_rf2_dds_ftw_valid_wreq = '1' then
          ctrl_rf2_dds_ftw_valid_reg <= wr_dat_d0;
        end if;
        ctrl_rf2_dds_ftw_valid_wack <= ctrl_rf2_dds_ftw_valid_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_rf2_dds_ftw
  ctrl_rf2_dds_ftw_o <= ctrl_rf2_dds_ftw_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_rf2_dds_ftw_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
        ctrl_rf2_dds_ftw_wack <= (others => '0');
      else
        if ctrl_rf2_dds_ftw_wreq(0) = '1' then
          ctrl_rf2_dds_ftw_reg(15 downto 0) <= wr_dat_d0;
        end if;
        if ctrl_rf2_dds_ftw_wreq(1) = '1' then
          ctrl_rf2_dds_ftw_reg(31 downto 16) <= wr_dat_d0;
        end if;
        if ctrl_rf2_dds_ftw_wreq(2) = '1' then
          ctrl_rf2_dds_ftw_reg(47 downto 32) <= wr_dat_d0;
        end if;
        if ctrl_rf2_dds_ftw_wreq(3) = '1' then
          ctrl_rf2_dds_ftw_reg(63 downto 48) <= wr_dat_d0;
        end if;
        ctrl_rf2_dds_ftw_wack <= ctrl_rf2_dds_ftw_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_nco_reset_ctrl
  ctrl_nco_reset_ctrl_mask_dds_o <= ctrl_nco_reset_ctrl_mask_dds_reg;
  ctrl_nco_reset_ctrl_mask_rfnco_ch1_o <= ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg;
  ctrl_nco_reset_ctrl_mask_rfnco_ch2_o <= ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg;
  ctrl_nco_reset_ctrl_mask_rf1_trig1_o <= ctrl_nco_reset_ctrl_mask_rf1_trig1_reg;
  ctrl_nco_reset_ctrl_mask_rf2_trig1_o <= ctrl_nco_reset_ctrl_mask_rf2_trig1_reg;
  ctrl_nco_reset_ctrl_soft_o <= ctrl_nco_reset_ctrl_soft_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_nco_reset_ctrl_mask_dds_reg <= '0';
        ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg <= '0';
        ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg <= '0';
        ctrl_nco_reset_ctrl_mask_rf1_trig1_reg <= '0';
        ctrl_nco_reset_ctrl_mask_rf2_trig1_reg <= '0';
        ctrl_nco_reset_ctrl_soft_reg <= '0';
        ctrl_nco_reset_ctrl_wack <= '0';
      else
        if ctrl_nco_reset_ctrl_wreq = '1' then
          ctrl_nco_reset_ctrl_mask_dds_reg <= wr_dat_d0(0);
          ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg <= wr_dat_d0(1);
          ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg <= wr_dat_d0(2);
          ctrl_nco_reset_ctrl_mask_rf1_trig1_reg <= wr_dat_d0(3);
          ctrl_nco_reset_ctrl_mask_rf2_trig1_reg <= wr_dat_d0(4);
          ctrl_nco_reset_ctrl_soft_reg <= wr_dat_d0(5);
        else
          ctrl_nco_reset_ctrl_soft_reg <= '0';
        end if;
        ctrl_nco_reset_ctrl_wack <= ctrl_nco_reset_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register ctrl_gbl_status
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        ctrl_gbl_status_rf1_t1_start_reg <= '0';
        ctrl_gbl_status_rf1_t2_start_reg <= '0';
        ctrl_gbl_status_rf2_t1_start_reg <= '0';
        ctrl_gbl_status_rf2_t2_start_reg <= '0';
        ctrl_gbl_status_wack <= '0';
      else
        if ctrl_gbl_status_wreq = '1' then
          ctrl_gbl_status_rf1_t1_start_reg <= ctrl_gbl_status_rf1_t1_start_i or (ctrl_gbl_status_rf1_t1_start_reg and not wr_dat_d0(0));
          ctrl_gbl_status_rf1_t2_start_reg <= ctrl_gbl_status_rf1_t2_start_i or (ctrl_gbl_status_rf1_t2_start_reg and not wr_dat_d0(1));
          ctrl_gbl_status_rf2_t1_start_reg <= ctrl_gbl_status_rf2_t1_start_i or (ctrl_gbl_status_rf2_t1_start_reg and not wr_dat_d0(2));
          ctrl_gbl_status_rf2_t2_start_reg <= ctrl_gbl_status_rf2_t2_start_i or (ctrl_gbl_status_rf2_t2_start_reg and not wr_dat_d0(3));
        else
          ctrl_gbl_status_rf1_t1_start_reg <= ctrl_gbl_status_rf1_t1_start_i or ctrl_gbl_status_rf1_t1_start_reg;
          ctrl_gbl_status_rf1_t2_start_reg <= ctrl_gbl_status_rf1_t2_start_i or ctrl_gbl_status_rf1_t2_start_reg;
          ctrl_gbl_status_rf2_t1_start_reg <= ctrl_gbl_status_rf2_t1_start_i or ctrl_gbl_status_rf2_t1_start_reg;
          ctrl_gbl_status_rf2_t2_start_reg <= ctrl_gbl_status_rf2_t2_start_i or ctrl_gbl_status_rf2_t2_start_reg;
        end if;
        ctrl_gbl_status_wack <= ctrl_gbl_status_wreq;
      end if;
    end if;
  end process;

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, init_hwinfo_echo_wack, init_fw_update_wack,
           init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack,
           init_mmcm_shift_wack, init_tmg_wack, init_lemo_rf1_t1_start_wack,
           init_lemo_rf1_t2_start_wack, init_lemo_rf2_t1_start_wack,
           init_lemo_rf2_t2_start_wack, init_lemo_rf1_t1_stop_wack,
           init_lemo_rf1_t2_stop_wack, init_lemo_rf2_t1_stop_wack,
           init_lemo_rf2_t2_stop_wack, init_tmgio1_wack, init_tmgio2_wack,
           init_tmgio3_wack, init_tmgio4_wack, init_tmgclk1_wack,
           init_tmgclk2_wack, init_lemo_wack, init_lemo_ext_wack,
           init_softstart_wack, init_softstop_wack, init_lemo_pulse_wack,
           init_pin_ctrl_wack, init_pll_ctrl_wack, init_dds_ctrl_wack,
           init_dds_ioupdate_wack, init_ocxo_ctrl_wack,
           init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack,
           init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack,
           init_nco_update_wack, init_nco_loc_or_wrs_wack,
           init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack,
           init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack,
           init_wrs_rxframe_rfframe_ts_wack, init_wrc_page0_wack,
           init_wrc_page1_wack, init_txframe_ftw_h1_main_wack,
           init_txframe_ftw_h1_prog_wack, init_txframe_ftw_h1_on_wack,
           init_txframe_dftw_h1_slip1_wack, init_txframe_dftw_h1_slip2_wack,
           init_txframe_setpoint1_wack, init_txframe_setpoint2_wack,
           init_txframe_setpoint3_wack, init_txframe_setpoint4_wack,
           init_txframe_setpoint5_wack, init_txframe_setpoint6_wack,
           init_txframe_setpoint7_wack, init_txframe_setpoint8_wack,
           init_txframe_noise_wack, init_txframe_control_wack,
           init_pll_spi_wack, init_rf_spi_wack, init_rf_wack,
           init_framerxtx_wack, init_xadc_wack, init_wrpc_wack,
           ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_rf1_rfnco_wack,
           ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_phase_wack,
           ctrl_rf2_iqdac_phase_wack, ctrl_rf1_iqdac_phase_update_wack,
           ctrl_rf2_iqdac_phase_update_wack, ctrl_rf1_iqdac_igain_arm_wack,
           ctrl_rf1_iqdac_qgain_arm_wack, ctrl_rf2_iqdac_igain_arm_wack,
           ctrl_rf2_iqdac_qgain_arm_wack, ctrl_rf1_iqdac_ctrl_wack,
           ctrl_rf2_iqdac_ctrl_wack, ctrl_iqdac_ram_addr_wack,
           ctrl_iqdac_ram_data_wack, ctrl_iqdac_ram_write_wack,
           ctrl_iqdac_ram_play_wack, ctrl_rf1_dds_ftw_valid_wack,
           ctrl_rf1_dds_ftw_wack, ctrl_rf2_dds_ftw_valid_wack,
           ctrl_rf2_dds_ftw_wack, ctrl_nco_reset_ctrl_wack,
           ctrl_gbl_status_wack) begin
    init_hwinfo_echo_wreq <= (others => '0');
    init_fw_update_we <= '0';
    init_reconfigure_wreq <= '0';
    init_clock_ctrl_wreq <= '0';
    init_wrcore_ctrl_wreq <= '0';
    init_iodelay_ctrl_wreq <= '0';
    init_mmcm_shift_wreq <= '0';
    init_tmg_wreq <= '0';
    init_lemo_rf1_t1_start_wreq <= '0';
    init_lemo_rf1_t2_start_wreq <= '0';
    init_lemo_rf2_t1_start_wreq <= '0';
    init_lemo_rf2_t2_start_wreq <= '0';
    init_lemo_rf1_t1_stop_wreq <= '0';
    init_lemo_rf1_t2_stop_wreq <= '0';
    init_lemo_rf2_t1_stop_wreq <= '0';
    init_lemo_rf2_t2_stop_wreq <= '0';
    init_tmgio1_wreq <= '0';
    init_tmgio2_wreq <= '0';
    init_tmgio3_wreq <= '0';
    init_tmgio4_wreq <= '0';
    init_tmgclk1_wreq <= '0';
    init_tmgclk2_wreq <= '0';
    init_lemo_wreq <= '0';
    init_lemo_ext_wreq <= '0';
    init_softstart_wreq <= '0';
    init_softstop_wreq <= '0';
    init_lemo_pulse_wreq <= '0';
    init_pin_ctrl_wreq <= '0';
    init_pll_ctrl_wreq <= '0';
    init_dds_ctrl_wreq <= '0';
    init_dds_ioupdate_wreq <= '0';
    init_ocxo_ctrl_wreq <= '0';
    init_nco_azimuthal_wreq <= (others => '0');
    init_nco_cabledelay_wreq <= (others => '0');
    init_nco_hb_wreq <= '0';
    init_nco_h1_ftw_wreq <= (others => '0');
    init_nco_h1_prog_wreq <= (others => '0');
    init_nco_ctrl_wreq <= '0';
    init_nco_update_wreq <= '0';
    init_nco_loc_or_wrs_wreq <= '0';
    init_svec_mup_ctrl_wreq <= '0';
    init_svec_mup_rftrig_wreq <= '0';
    init_svec_mup_fmc1_wreq <= '0';
    init_svec_mup_fmc2_wreq <= '0';
    init_wrs_rxframe_rfframe_ts_wreq <= '0';
    init_wrc_page0_wreq <= (others => '0');
    init_wrc_page1_wreq <= (others => '0');
    init_txframe_ftw_h1_main_wreq <= (others => '0');
    init_txframe_ftw_h1_prog_wreq <= (others => '0');
    init_txframe_ftw_h1_on_wreq <= (others => '0');
    init_txframe_dftw_h1_slip1_wreq <= (others => '0');
    init_txframe_dftw_h1_slip2_wreq <= (others => '0');
    init_txframe_setpoint1_wreq <= (others => '0');
    init_txframe_setpoint2_wreq <= (others => '0');
    init_txframe_setpoint3_wreq <= (others => '0');
    init_txframe_setpoint4_wreq <= (others => '0');
    init_txframe_setpoint5_wreq <= (others => '0');
    init_txframe_setpoint6_wreq <= (others => '0');
    init_txframe_setpoint7_wreq <= (others => '0');
    init_txframe_setpoint8_wreq <= (others => '0');
    init_txframe_noise_wreq <= (others => '0');
    init_txframe_control_wreq <= '0';
    init_pll_spi_we <= '0';
    init_rf_spi_we <= '0';
    init_rf_we <= '0';
    init_framerxtx_we <= '0';
    init_xadc_we <= '0';
    init_wrpc_we <= '0';
    ctrl_rf1_vtus_we <= '0';
    ctrl_rf2_vtus_we <= '0';
    ctrl_rf1_rfnco_we <= '0';
    ctrl_rf2_rfnco_we <= '0';
    ctrl_rf1_iqdac_phase_wreq <= '0';
    ctrl_rf2_iqdac_phase_wreq <= '0';
    ctrl_rf1_iqdac_phase_update_wreq <= '0';
    ctrl_rf2_iqdac_phase_update_wreq <= '0';
    ctrl_rf1_iqdac_igain_arm_wreq <= '0';
    ctrl_rf1_iqdac_qgain_arm_wreq <= '0';
    ctrl_rf2_iqdac_igain_arm_wreq <= '0';
    ctrl_rf2_iqdac_qgain_arm_wreq <= '0';
    ctrl_rf1_iqdac_ctrl_wreq <= '0';
    ctrl_rf2_iqdac_ctrl_wreq <= '0';
    ctrl_iqdac_ram_addr_wreq <= '0';
    ctrl_iqdac_ram_data_wreq <= '0';
    ctrl_iqdac_ram_write_wreq <= '0';
    ctrl_iqdac_ram_play_wreq <= '0';
    ctrl_rf1_dds_ftw_valid_wreq <= '0';
    ctrl_rf1_dds_ftw_wreq <= (others => '0');
    ctrl_rf2_dds_ftw_valid_wreq <= '0';
    ctrl_rf2_dds_ftw_wreq <= (others => '0');
    ctrl_nco_reset_ctrl_wreq <= '0';
    ctrl_gbl_status_wreq <= '0';
    case wr_adr_d0(14 downto 13) is
    when "00" =>
      case wr_adr_d0(12 downto 8) is
      when "00000" =>
        case wr_adr_d0(7 downto 1) is
        when "0000000" =>
          -- Reg init_hwinfo_stdVersion
          wr_ack_int <= wr_req_d0;
        when "0000001" =>
          -- Reg init_hwinfo_stdVersion
          wr_ack_int <= wr_req_d0;
        when "0000100" =>
          -- Reg init_hwinfo_serialNumber
          wr_ack_int <= wr_req_d0;
        when "0000101" =>
          -- Reg init_hwinfo_serialNumber
          wr_ack_int <= wr_req_d0;
        when "0000110" =>
          -- Reg init_hwinfo_serialNumber
          wr_ack_int <= wr_req_d0;
        when "0000111" =>
          -- Reg init_hwinfo_serialNumber
          wr_ack_int <= wr_req_d0;
        when "0001000" =>
          -- Reg init_hwinfo_ident
          wr_ack_int <= wr_req_d0;
        when "0001010" =>
          -- Reg init_hwinfo_firmwareVersion
          wr_ack_int <= wr_req_d0;
        when "0001011" =>
          -- Reg init_hwinfo_firmwareVersion
          wr_ack_int <= wr_req_d0;
        when "0001100" =>
          -- Reg init_hwinfo_memMapVersion
          wr_ack_int <= wr_req_d0;
        when "0001101" =>
          -- Reg init_hwinfo_memMapVersion
          wr_ack_int <= wr_req_d0;
        when "0001110" =>
          -- Reg init_hwinfo_echo
          init_hwinfo_echo_wreq(1) <= wr_req_d0;
          wr_ack_int <= init_hwinfo_echo_wack(1);
        when "0001111" =>
          -- Reg init_hwinfo_echo
          init_hwinfo_echo_wreq(0) <= wr_req_d0;
          wr_ack_int <= init_hwinfo_echo_wack(0);
        when "1111110" =>
          -- Reg init_hwinfo_setStandard
          wr_ack_int <= wr_req_d0;
        when "1111111" =>
          -- Reg init_hwinfo_setStandard
          wr_ack_int <= wr_req_d0;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "00001" =>
        case wr_adr_d0(7 downto 3) is
        when "00000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Submap init_fw_update
            init_fw_update_we <= wr_req_d0;
            wr_ack_int <= init_fw_update_wack;
          when "01" =>
            -- Reg init_reconfigure
            init_reconfigure_wreq <= wr_req_d0;
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg init_clock_ctrl
            init_clock_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_clock_ctrl_wack;
          when "11" =>
            -- Reg init_wrcore_ctrl
            init_wrcore_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_wrcore_ctrl_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00001" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_iodelay_ctrl
            init_iodelay_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_iodelay_ctrl_wack;
          when "01" =>
            -- Reg init_mmcm_shift
            init_mmcm_shift_wreq <= wr_req_d0;
            wr_ack_int <= init_mmcm_shift_wack;
          when "10" =>
            -- Reg init_clock_status
            wr_ack_int <= wr_req_d0;
          when "11" =>
            -- Reg init_tmg
            init_tmg_wreq <= wr_req_d0;
            wr_ack_int <= init_tmg_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00010" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_lemo_rf1_t1_start
            init_lemo_rf1_t1_start_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf1_t1_start_wack;
          when "01" =>
            -- Reg init_lemo_rf1_t2_start
            init_lemo_rf1_t2_start_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf1_t2_start_wack;
          when "10" =>
            -- Reg init_lemo_rf2_t1_start
            init_lemo_rf2_t1_start_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf2_t1_start_wack;
          when "11" =>
            -- Reg init_lemo_rf2_t2_start
            init_lemo_rf2_t2_start_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf2_t2_start_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00011" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_lemo_rf1_t1_stop
            init_lemo_rf1_t1_stop_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf1_t1_stop_wack;
          when "01" =>
            -- Reg init_lemo_rf1_t2_stop
            init_lemo_rf1_t2_stop_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf1_t2_stop_wack;
          when "10" =>
            -- Reg init_lemo_rf2_t1_stop
            init_lemo_rf2_t1_stop_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf2_t1_stop_wack;
          when "11" =>
            -- Reg init_lemo_rf2_t2_stop
            init_lemo_rf2_t2_stop_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_rf2_t2_stop_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00100" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_tmgio1
            init_tmgio1_wreq <= wr_req_d0;
            wr_ack_int <= init_tmgio1_wack;
          when "01" =>
            -- Reg init_tmgio2
            init_tmgio2_wreq <= wr_req_d0;
            wr_ack_int <= init_tmgio2_wack;
          when "10" =>
            -- Reg init_tmgio3
            init_tmgio3_wreq <= wr_req_d0;
            wr_ack_int <= init_tmgio3_wack;
          when "11" =>
            -- Reg init_tmgio4
            init_tmgio4_wreq <= wr_req_d0;
            wr_ack_int <= init_tmgio4_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00101" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_tmgclk1
            init_tmgclk1_wreq <= wr_req_d0;
            wr_ack_int <= init_tmgclk1_wack;
          when "01" =>
            -- Reg init_tmgclk2
            init_tmgclk2_wreq <= wr_req_d0;
            wr_ack_int <= init_tmgclk2_wack;
          when "10" =>
            -- Reg init_lemo
            init_lemo_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_wack;
          when "11" =>
            -- Reg init_lemo_ext
            init_lemo_ext_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_ext_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00110" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_softstart
            init_softstart_wreq <= wr_req_d0;
            wr_ack_int <= init_softstart_wack;
          when "01" =>
            -- Reg init_softstop
            init_softstop_wreq <= wr_req_d0;
            wr_ack_int <= init_softstop_wack;
          when "10" =>
            -- Reg init_lemo_pulse
            init_lemo_pulse_wreq <= wr_req_d0;
            wr_ack_int <= init_lemo_pulse_wack;
          when "11" =>
            -- Reg init_pin_ctrl
            init_pin_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_pin_ctrl_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00111" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_pll_status
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_pll_ctrl
            init_pll_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_pll_ctrl_wack;
          when "10" =>
            -- Reg init_dds_ctrl
            init_dds_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_dds_ctrl_wack;
          when "11" =>
            -- Reg init_dds_ioupdate
            init_dds_ioupdate_wreq <= wr_req_d0;
            wr_ack_int <= init_dds_ioupdate_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "01000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_dds_status
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg init_ocxo_ctrl
            init_ocxo_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_ocxo_ctrl_wack;
          when "11" =>
            -- Reg init_ocxo_uptime
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_nco_azimuthal
            init_nco_azimuthal_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_nco_azimuthal_wack(3);
          when "01" =>
            -- Reg init_nco_azimuthal
            init_nco_azimuthal_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_nco_azimuthal_wack(2);
          when "10" =>
            -- Reg init_nco_azimuthal
            init_nco_azimuthal_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_nco_azimuthal_wack(1);
          when "11" =>
            -- Reg init_nco_azimuthal
            init_nco_azimuthal_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_nco_azimuthal_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10001" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_nco_cabledelay
            init_nco_cabledelay_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_nco_cabledelay_wack(3);
          when "01" =>
            -- Reg init_nco_cabledelay
            init_nco_cabledelay_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_nco_cabledelay_wack(2);
          when "10" =>
            -- Reg init_nco_cabledelay
            init_nco_cabledelay_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_nco_cabledelay_wack(1);
          when "11" =>
            -- Reg init_nco_cabledelay
            init_nco_cabledelay_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_nco_cabledelay_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10010" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_nco_hb
            init_nco_hb_wreq <= wr_req_d0;
            wr_ack_int <= init_nco_hb_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10011" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_nco_h1_ftw
            init_nco_h1_ftw_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_ftw_wack(3);
          when "01" =>
            -- Reg init_nco_h1_ftw
            init_nco_h1_ftw_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_ftw_wack(2);
          when "10" =>
            -- Reg init_nco_h1_ftw
            init_nco_h1_ftw_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_ftw_wack(1);
          when "11" =>
            -- Reg init_nco_h1_ftw
            init_nco_h1_ftw_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_ftw_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10100" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_nco_h1_prog
            init_nco_h1_prog_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_prog_wack(3);
          when "01" =>
            -- Reg init_nco_h1_prog
            init_nco_h1_prog_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_prog_wack(2);
          when "10" =>
            -- Reg init_nco_h1_prog
            init_nco_h1_prog_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_prog_wack(1);
          when "11" =>
            -- Reg init_nco_h1_prog
            init_nco_h1_prog_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_nco_h1_prog_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10101" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_nco_ctrl
            init_nco_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_nco_ctrl_wack;
          when "01" =>
            -- Reg init_nco_update
            init_nco_update_wreq <= wr_req_d0;
            wr_ack_int <= init_nco_update_wack;
          when "10" =>
            -- Reg init_nco_loc_or_wrs
            init_nco_loc_or_wrs_wreq <= wr_req_d0;
            wr_ack_int <= init_nco_loc_or_wrs_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "11000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_svec_mup_ctrl
            init_svec_mup_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= init_svec_mup_ctrl_wack;
          when "01" =>
            -- Reg init_svec_mup_rftrig
            init_svec_mup_rftrig_wreq <= wr_req_d0;
            wr_ack_int <= init_svec_mup_rftrig_wack;
          when "10" =>
            -- Reg init_svec_mup_fmc1
            init_svec_mup_fmc1_wreq <= wr_req_d0;
            wr_ack_int <= init_svec_mup_fmc1_wack;
          when "11" =>
            -- Reg init_svec_mup_fmc2
            init_svec_mup_fmc2_wreq <= wr_req_d0;
            wr_ack_int <= init_svec_mup_fmc2_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "00010" =>
        case wr_adr_d0(7 downto 3) is
        when "00000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_ftw
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_wrs_rxframe_ftw
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg init_wrs_rxframe_ftw
            wr_ack_int <= wr_req_d0;
          when "11" =>
            -- Reg init_wrs_rxframe_ftw
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00001" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_ctrl
              wr_ack_int <= wr_req_d0;
            when "1" =>
              -- Reg init_wrs_rxframe_counter
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_rxwrtimestamp
              wr_ack_int <= wr_req_d0;
            when "1" =>
              -- Reg init_wrs_rxframe_rxwrtimestamp
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00010" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_txwrtimestamp
              wr_ack_int <= wr_req_d0;
            when "1" =>
              -- Reg init_wrs_rxframe_txwrtimestamp
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_rftimestamp
              wr_ack_int <= wr_req_d0;
            when "1" =>
              -- Reg init_wrs_rxframe_rftimestamp
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00011" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_rfframe_ts
            init_wrs_rxframe_rfframe_ts_wreq <= wr_req_d0;
            wr_ack_int <= init_wrs_rxframe_rfframe_ts_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00100" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            wr_ack_int <= wr_req_d0;
          when "11" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00101" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_nco_reset_cycles
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_wrs_rxframe_nco_reset_cycles
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00110" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_tai
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_wrs_rxframe_tai
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg init_wrs_rxframe_tai
            wr_ack_int <= wr_req_d0;
          when "11" =>
            -- Reg init_wrs_rxframe_tai
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "00111" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_cycles
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_wrs_rxframe_cycles
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "01000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_wrc_tai
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg init_wrc_tai
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg init_wrc_tai
            wr_ack_int <= wr_req_d0;
          when "11" =>
            -- Reg init_wrc_tai
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "01001" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_cycles
              wr_ack_int <= wr_req_d0;
            when "1" =>
              -- Reg init_wrc_cycles
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_status
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "01010" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_page0
              init_wrc_page0_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_wrc_page0_wack(1);
            when "1" =>
              -- Reg init_wrc_page0
              init_wrc_page0_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_wrc_page0_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_page1
              init_wrc_page1_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_wrc_page1_wack(1);
            when "1" =>
              -- Reg init_wrc_page1
              init_wrc_page1_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_wrc_page1_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_txframe_ftw_h1_main
            init_txframe_ftw_h1_main_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_main_wack(3);
          when "01" =>
            -- Reg init_txframe_ftw_h1_main
            init_txframe_ftw_h1_main_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_main_wack(2);
          when "10" =>
            -- Reg init_txframe_ftw_h1_main
            init_txframe_ftw_h1_main_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_main_wack(1);
          when "11" =>
            -- Reg init_txframe_ftw_h1_main
            init_txframe_ftw_h1_main_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_main_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10001" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_txframe_ftw_h1_prog
            init_txframe_ftw_h1_prog_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_prog_wack(3);
          when "01" =>
            -- Reg init_txframe_ftw_h1_prog
            init_txframe_ftw_h1_prog_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_prog_wack(2);
          when "10" =>
            -- Reg init_txframe_ftw_h1_prog
            init_txframe_ftw_h1_prog_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_prog_wack(1);
          when "11" =>
            -- Reg init_txframe_ftw_h1_prog
            init_txframe_ftw_h1_prog_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_prog_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10010" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg init_txframe_ftw_h1_on
            init_txframe_ftw_h1_on_wreq(3) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_on_wack(3);
          when "01" =>
            -- Reg init_txframe_ftw_h1_on
            init_txframe_ftw_h1_on_wreq(2) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_on_wack(2);
          when "10" =>
            -- Reg init_txframe_ftw_h1_on
            init_txframe_ftw_h1_on_wreq(1) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_on_wack(1);
          when "11" =>
            -- Reg init_txframe_ftw_h1_on
            init_txframe_ftw_h1_on_wreq(0) <= wr_req_d0;
            wr_ack_int <= init_txframe_ftw_h1_on_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10011" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_dftw_h1_slip1
              init_txframe_dftw_h1_slip1_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_dftw_h1_slip1_wack(1);
            when "1" =>
              -- Reg init_txframe_dftw_h1_slip1
              init_txframe_dftw_h1_slip1_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_dftw_h1_slip1_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_dftw_h1_slip2
              init_txframe_dftw_h1_slip2_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_dftw_h1_slip2_wack(1);
            when "1" =>
              -- Reg init_txframe_dftw_h1_slip2
              init_txframe_dftw_h1_slip2_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_dftw_h1_slip2_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10100" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint1
              init_txframe_setpoint1_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint1_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint1
              init_txframe_setpoint1_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint1_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint2
              init_txframe_setpoint2_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint2_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint2
              init_txframe_setpoint2_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint2_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10101" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint3
              init_txframe_setpoint3_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint3_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint3
              init_txframe_setpoint3_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint3_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint4
              init_txframe_setpoint4_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint4_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint4
              init_txframe_setpoint4_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint4_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10110" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint5
              init_txframe_setpoint5_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint5_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint5
              init_txframe_setpoint5_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint5_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint6
              init_txframe_setpoint6_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint6_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint6
              init_txframe_setpoint6_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint6_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "10111" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint7
              init_txframe_setpoint7_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint7_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint7
              init_txframe_setpoint7_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint7_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint8
              init_txframe_setpoint8_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint8_wack(1);
            when "1" =>
              -- Reg init_txframe_setpoint8
              init_txframe_setpoint8_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_setpoint8_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "11000" =>
          case wr_adr_d0(2 downto 2) is
          when "0" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_noise
              init_txframe_noise_wreq(1) <= wr_req_d0;
              wr_ack_int <= init_txframe_noise_wack(1);
            when "1" =>
              -- Reg init_txframe_noise
              init_txframe_noise_wreq(0) <= wr_req_d0;
              wr_ack_int <= init_txframe_noise_wack(0);
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "1" =>
            case wr_adr_d0(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_control
              init_txframe_control_wreq <= wr_req_d0;
              wr_ack_int <= init_txframe_control_wack;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "00011" =>
        case wr_adr_d0(7 downto 6) is
        when "00" =>
          case wr_adr_d0(5 downto 5) is
          when "0" =>
            -- Submap init_pll_spi
            init_pll_spi_we <= wr_req_d0;
            wr_ack_int <= init_pll_spi_wack;
          when "1" =>
            -- Submap init_rf_spi
            init_rf_spi_we <= wr_req_d0;
            wr_ack_int <= init_rf_spi_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "01" =>
          -- Submap init_rf
          init_rf_we <= wr_req_d0;
          wr_ack_int <= init_rf_wack;
        when "10" =>
          -- Submap init_framerxtx
          init_framerxtx_we <= wr_req_d0;
          wr_ack_int <= init_framerxtx_wack;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "00100" =>
        -- Submap init_xadc
        init_xadc_we <= wr_req_d0;
        wr_ack_int <= init_xadc_wack;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "01" =>
      -- Submap init_wrpc
      init_wrpc_we <= wr_req_d0;
      wr_ack_int <= init_wrpc_wack;
    when "10" =>
      case wr_adr_d0(12 downto 12) is
      when "0" =>
        case wr_adr_d0(11 downto 9) is
        when "000" =>
          -- Submap ctrl_rf1_vtus
          ctrl_rf1_vtus_we <= wr_req_d0;
          wr_ack_int <= ctrl_rf1_vtus_wack;
        when "001" =>
          -- Submap ctrl_rf2_vtus
          ctrl_rf2_vtus_we <= wr_req_d0;
          wr_ack_int <= ctrl_rf2_vtus_wack;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "1" =>
        -- Submap ctrl_rf1_rfnco
        ctrl_rf1_rfnco_we <= wr_req_d0;
        wr_ack_int <= ctrl_rf1_rfnco_wack;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "11" =>
      case wr_adr_d0(12 downto 12) is
      when "0" =>
        -- Submap ctrl_rf2_rfnco
        ctrl_rf2_rfnco_we <= wr_req_d0;
        wr_ack_int <= ctrl_rf2_rfnco_wack;
      when "1" =>
        case wr_adr_d0(11 downto 3) is
        when "000000000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_phase
            ctrl_rf1_iqdac_phase_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_iqdac_phase_wack;
          when "01" =>
            -- Reg ctrl_rf2_iqdac_phase
            ctrl_rf2_iqdac_phase_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_iqdac_phase_wack;
          when "10" =>
            -- Reg ctrl_rf1_iqdac_phase_update
            ctrl_rf1_iqdac_phase_update_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_iqdac_phase_update_wack;
          when "11" =>
            -- Reg ctrl_rf2_iqdac_phase_update
            ctrl_rf2_iqdac_phase_update_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_iqdac_phase_update_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000001" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_igain_arm
            ctrl_rf1_iqdac_igain_arm_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_iqdac_igain_arm_wack;
          when "01" =>
            -- Reg ctrl_rf1_iqdac_qgain_arm
            ctrl_rf1_iqdac_qgain_arm_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_iqdac_qgain_arm_wack;
          when "10" =>
            -- Reg ctrl_rf2_iqdac_igain_arm
            ctrl_rf2_iqdac_igain_arm_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_iqdac_igain_arm_wack;
          when "11" =>
            -- Reg ctrl_rf2_iqdac_qgain_arm
            ctrl_rf2_iqdac_qgain_arm_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_iqdac_qgain_arm_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000010" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_igain
            wr_ack_int <= wr_req_d0;
          when "01" =>
            -- Reg ctrl_rf1_iqdac_qgain
            wr_ack_int <= wr_req_d0;
          when "10" =>
            -- Reg ctrl_rf2_iqdac_igain
            wr_ack_int <= wr_req_d0;
          when "11" =>
            -- Reg ctrl_rf2_iqdac_qgain
            wr_ack_int <= wr_req_d0;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000011" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_ctrl
            ctrl_rf1_iqdac_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_iqdac_ctrl_wack;
          when "01" =>
            -- Reg ctrl_rf2_iqdac_ctrl
            ctrl_rf2_iqdac_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_iqdac_ctrl_wack;
          when "10" =>
            -- Reg ctrl_iqdac_ram_addr
            ctrl_iqdac_ram_addr_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_iqdac_ram_addr_wack;
          when "11" =>
            -- Reg ctrl_iqdac_ram_data
            ctrl_iqdac_ram_data_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_iqdac_ram_data_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000100" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_iqdac_ram_write
            ctrl_iqdac_ram_write_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_iqdac_ram_write_wack;
          when "01" =>
            -- Reg ctrl_iqdac_ram_play
            ctrl_iqdac_ram_play_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_iqdac_ram_play_wack;
          when "10" =>
            -- Reg ctrl_rf1_dds_ftw_valid
            ctrl_rf1_dds_ftw_valid_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_dds_ftw_valid_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000101" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_dds_ftw
            ctrl_rf1_dds_ftw_wreq(3) <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_dds_ftw_wack(3);
          when "01" =>
            -- Reg ctrl_rf1_dds_ftw
            ctrl_rf1_dds_ftw_wreq(2) <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_dds_ftw_wack(2);
          when "10" =>
            -- Reg ctrl_rf1_dds_ftw
            ctrl_rf1_dds_ftw_wreq(1) <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_dds_ftw_wack(1);
          when "11" =>
            -- Reg ctrl_rf1_dds_ftw
            ctrl_rf1_dds_ftw_wreq(0) <= wr_req_d0;
            wr_ack_int <= ctrl_rf1_dds_ftw_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000110" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf2_dds_ftw_valid
            ctrl_rf2_dds_ftw_valid_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_dds_ftw_valid_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000000111" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf2_dds_ftw
            ctrl_rf2_dds_ftw_wreq(3) <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_dds_ftw_wack(3);
          when "01" =>
            -- Reg ctrl_rf2_dds_ftw
            ctrl_rf2_dds_ftw_wreq(2) <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_dds_ftw_wack(2);
          when "10" =>
            -- Reg ctrl_rf2_dds_ftw
            ctrl_rf2_dds_ftw_wreq(1) <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_dds_ftw_wack(1);
          when "11" =>
            -- Reg ctrl_rf2_dds_ftw
            ctrl_rf2_dds_ftw_wreq(0) <= wr_req_d0;
            wr_ack_int <= ctrl_rf2_dds_ftw_wack(0);
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "000001000" =>
          case wr_adr_d0(2 downto 1) is
          when "00" =>
            -- Reg ctrl_nco_reset_ctrl
            ctrl_nco_reset_ctrl_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_nco_reset_ctrl_wack;
          when "01" =>
            -- Reg ctrl_gbl_status
            ctrl_gbl_status_wreq <= wr_req_d0;
            wr_ack_int <= ctrl_gbl_status_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, init_hwinfo_serialNumber_i,
           init_hwinfo_ident_cardID_i, init_hwinfo_ident_extendedID_i,
           init_hwinfo_ident_jtagRemoteDisable_i,
           init_hwinfo_firmwareVersion_i, init_hwinfo_memMapVersion_i,
           init_hwinfo_echo_echo_reg, init_fw_update_i.dat,
           init_fw_update_rack, init_clock_ctrl_clk_sel_reg,
           init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg,
           init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i,
           init_clock_status_shift_busy_i, init_tmg_io_term_reg,
           init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg,
           init_lemo_rf1_t1_start_sel_reg, init_lemo_rf1_t2_start_sel_reg,
           init_lemo_rf2_t1_start_sel_reg, init_lemo_rf2_t2_start_sel_reg,
           init_lemo_rf1_t1_stop_sel_reg, init_lemo_rf1_t2_stop_sel_reg,
           init_lemo_rf2_t1_stop_sel_reg, init_lemo_rf2_t2_stop_sel_reg,
           init_tmgio1_osel_reg, init_tmgio2_osel_reg, init_tmgio3_osel_reg,
           init_tmgio4_osel_reg, init_tmgclk1_osel_reg, init_tmgclk2_osel_reg,
           init_lemo_gpio_reg, init_lemo_ext_sel_reg, init_softstart_sel_reg,
           init_softstop_sel_reg, init_lemo_pulse_ext_reg,
           init_pin_ctrl_ext_10m_dir_reg, init_pin_ctrl_ext_pps_dir_reg,
           init_pll_status_error_i, init_pll_status_locked_i,
           init_pll_ctrl_sync_reg, init_dds_ctrl_reset_reg,
           init_dds_ctrl_profile_reg, init_dds_ioupdate_fdelay_reg,
           init_dds_ioupdate_odelay_reg, init_dds_status_sync_error_i,
           init_ocxo_ctrl_enable_reg, init_ocxo_uptime_val_i,
           init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg,
           init_nco_hb_value_reg, init_nco_h1_ftw_value_reg,
           init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg,
           init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg,
           init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg,
           init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg,
           init_svec_mup_ctrl_bclk_rfclk_sel_reg,
           init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg,
           init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg,
           init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg,
           init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg,
           init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg,
           init_svec_mup_fmc2_led_reg, init_wrs_rxframe_ftw_value_i,
           init_wrs_rxframe_ctrl_i, init_wrs_rxframe_counter_i,
           init_wrs_rxframe_rxwrtimestamp_i,
           init_wrs_rxframe_txwrtimestamp_i, init_wrs_rxframe_rftimestamp_i,
           init_wrs_rxframe_nco_reset_tai_val_i,
           init_wrs_rxframe_nco_reset_cycles_val_i,
           init_wrs_rxframe_tai_val_i, init_wrs_rxframe_cycles_val_i,
           init_wrc_tai_value_i, init_wrc_cycles_value_i,
           init_wrc_status_linkup_i, init_wrc_status_time_valid_i,
           init_wrc_page0_reg, init_wrc_page1_reg,
           init_txframe_ftw_h1_main_reg, init_txframe_ftw_h1_prog_reg,
           init_txframe_ftw_h1_on_reg, init_txframe_dftw_h1_slip1_reg,
           init_txframe_dftw_h1_slip2_reg, init_txframe_setpoint1_reg,
           init_txframe_setpoint2_reg, init_txframe_setpoint3_reg,
           init_txframe_setpoint4_reg, init_txframe_setpoint5_reg,
           init_txframe_setpoint6_reg, init_txframe_setpoint7_reg,
           init_txframe_setpoint8_reg, init_txframe_noise_reg,
           init_txframe_control_reg, init_pll_spi_i.dat, init_pll_spi_rack,
           init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack,
           init_framerxtx_i.dat, init_framerxtx_rack, init_xadc_i.dat,
           init_xadc_rack, init_wrpc_i.dat, init_wrpc_rack, ctrl_rf1_vtus_i.dat,
           ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack,
           ctrl_rf1_rfnco_i.dat, ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat,
           ctrl_rf2_rfnco_rack, ctrl_rf1_iqdac_phase_reg,
           ctrl_rf2_iqdac_phase_reg, ctrl_rf1_iqdac_igain_arm_reg,
           ctrl_rf1_iqdac_qgain_arm_reg, ctrl_rf2_iqdac_igain_arm_reg,
           ctrl_rf2_iqdac_qgain_arm_reg, ctrl_rf1_iqdac_igain_i,
           ctrl_rf1_iqdac_qgain_i, ctrl_rf2_iqdac_igain_i,
           ctrl_rf2_iqdac_qgain_i, ctrl_rf1_iqdac_ctrl_reg,
           ctrl_rf2_iqdac_ctrl_reg, ctrl_iqdac_ram_addr_reg,
           ctrl_iqdac_ram_data_reg, ctrl_iqdac_ram_write_reg,
           ctrl_iqdac_ram_play_reg, ctrl_rf1_dds_ftw_valid_reg,
           ctrl_rf1_dds_ftw_reg, ctrl_rf2_dds_ftw_valid_reg,
           ctrl_rf2_dds_ftw_reg, ctrl_nco_reset_ctrl_mask_dds_reg,
           ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg,
           ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg,
           ctrl_nco_reset_ctrl_mask_rf1_trig1_reg,
           ctrl_nco_reset_ctrl_mask_rf2_trig1_reg,
           ctrl_gbl_status_rf1_t1_start_reg,
           ctrl_gbl_status_rf1_t2_start_reg,
           ctrl_gbl_status_rf2_t1_start_reg,
           ctrl_gbl_status_rf2_t2_start_reg) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    init_fw_update_re <= '0';
    init_pll_spi_re <= '0';
    init_rf_spi_re <= '0';
    init_rf_re <= '0';
    init_framerxtx_re <= '0';
    init_xadc_re <= '0';
    init_wrpc_re <= '0';
    ctrl_rf1_vtus_re <= '0';
    ctrl_rf2_vtus_re <= '0';
    ctrl_rf1_rfnco_re <= '0';
    ctrl_rf2_rfnco_re <= '0';
    case adr_int(14 downto 13) is
    when "00" =>
      case adr_int(12 downto 8) is
      when "00000" =>
        case adr_int(7 downto 1) is
        when "0000000" =>
          -- Reg init_hwinfo_stdVersion
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= "00000010";
          rd_dat_d0(15 downto 8) <= "00000010";
        when "0000001" =>
          -- Reg init_hwinfo_stdVersion
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= "00000000";
          rd_dat_d0(15 downto 8) <= "00000000";
        when "0000100" =>
          -- Reg init_hwinfo_serialNumber
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= init_hwinfo_serialNumber_i(63 downto 48);
        when "0000101" =>
          -- Reg init_hwinfo_serialNumber
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= init_hwinfo_serialNumber_i(47 downto 32);
        when "0000110" =>
          -- Reg init_hwinfo_serialNumber
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= init_hwinfo_serialNumber_i(31 downto 16);
        when "0000111" =>
          -- Reg init_hwinfo_serialNumber
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= init_hwinfo_serialNumber_i(15 downto 0);
        when "0001000" =>
          -- Reg init_hwinfo_ident
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= init_hwinfo_ident_cardID_i;
          rd_dat_d0(14 downto 8) <= init_hwinfo_ident_extendedID_i;
          rd_dat_d0(15) <= init_hwinfo_ident_jtagRemoteDisable_i;
        when "0001010" =>
          -- Reg init_hwinfo_firmwareVersion
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= init_hwinfo_firmwareVersion_i(23 downto 16);
          rd_dat_d0(15 downto 8) <= (others => '0');
        when "0001011" =>
          -- Reg init_hwinfo_firmwareVersion
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= init_hwinfo_firmwareVersion_i(7 downto 0);
          rd_dat_d0(15 downto 8) <= init_hwinfo_firmwareVersion_i(15 downto 8);
        when "0001100" =>
          -- Reg init_hwinfo_memMapVersion
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= init_hwinfo_memMapVersion_i(23 downto 16);
          rd_dat_d0(15 downto 8) <= (others => '0');
        when "0001101" =>
          -- Reg init_hwinfo_memMapVersion
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= init_hwinfo_memMapVersion_i(7 downto 0);
          rd_dat_d0(15 downto 8) <= init_hwinfo_memMapVersion_i(15 downto 8);
        when "0001110" =>
          -- Reg init_hwinfo_echo
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(15 downto 0) <= (others => '0');
        when "0001111" =>
          -- Reg init_hwinfo_echo
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(7 downto 0) <= init_hwinfo_echo_echo_reg;
          rd_dat_d0(15 downto 8) <= (others => '0');
        when "1111110" =>
          -- Reg init_hwinfo_setStandard
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(13 downto 0) <= (others => '0');
          rd_dat_d0(15 downto 14) <= "10";
        when "1111111" =>
          -- Reg init_hwinfo_setStandard
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(15 downto 0) <= (others => '0');
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "00001" =>
        case adr_int(7 downto 3) is
        when "00000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Submap init_fw_update
            init_fw_update_re <= rd_req_int;
            rd_dat_d0 <= init_fw_update_i.dat(15 downto 0);
            rd_ack_d0 <= init_fw_update_rack;
          when "01" =>
            -- Reg init_reconfigure
            rd_ack_d0 <= rd_req_int;
          when "10" =>
            -- Reg init_clock_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_clock_ctrl_clk_sel_reg;
            rd_dat_d0(1) <= init_clock_ctrl_mmcm_reset_reg;
            rd_dat_d0(15 downto 2) <= (others => '0');
          when "11" =>
            -- Reg init_wrcore_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_wrcore_ctrl_reset_n_reg;
            rd_dat_d0(15 downto 1) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00001" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_iodelay_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_iodelay_ctrl_reset_reg;
            rd_dat_d0(15 downto 1) <= (others => '0');
          when "01" =>
            -- Reg init_mmcm_shift
            rd_ack_d0 <= rd_req_int;
          when "10" =>
            -- Reg init_clock_status
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_clock_status_mmcm_locked_i;
            rd_dat_d0(1) <= init_clock_status_shift_busy_i;
            rd_dat_d0(15 downto 2) <= (others => '0');
          when "11" =>
            -- Reg init_tmg
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(3 downto 0) <= init_tmg_io_term_reg;
            rd_dat_d0(7 downto 4) <= init_tmg_io_oe_reg;
            rd_dat_d0(9 downto 8) <= init_tmg_clk_term_reg;
            rd_dat_d0(11 downto 10) <= init_tmg_clk_oe_reg;
            rd_dat_d0(15 downto 12) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00010" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_lemo_rf1_t1_start
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf1_t1_start_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "01" =>
            -- Reg init_lemo_rf1_t2_start
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf1_t2_start_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "10" =>
            -- Reg init_lemo_rf2_t1_start
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf2_t1_start_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "11" =>
            -- Reg init_lemo_rf2_t2_start
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf2_t2_start_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00011" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_lemo_rf1_t1_stop
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf1_t1_stop_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "01" =>
            -- Reg init_lemo_rf1_t2_stop
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf1_t2_stop_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "10" =>
            -- Reg init_lemo_rf2_t1_stop
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf2_t1_stop_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "11" =>
            -- Reg init_lemo_rf2_t2_stop
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(6 downto 1) <= init_lemo_rf2_t2_stop_sel_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00100" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_tmgio1
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(13 downto 0) <= init_tmgio1_osel_reg;
            rd_dat_d0(15 downto 14) <= (others => '0');
          when "01" =>
            -- Reg init_tmgio2
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(13 downto 0) <= init_tmgio2_osel_reg;
            rd_dat_d0(15 downto 14) <= (others => '0');
          when "10" =>
            -- Reg init_tmgio3
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(13 downto 0) <= init_tmgio3_osel_reg;
            rd_dat_d0(15 downto 14) <= (others => '0');
          when "11" =>
            -- Reg init_tmgio4
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(13 downto 0) <= init_tmgio4_osel_reg;
            rd_dat_d0(15 downto 14) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00101" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_tmgclk1
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(13 downto 0) <= init_tmgclk1_osel_reg;
            rd_dat_d0(15 downto 14) <= (others => '0');
          when "01" =>
            -- Reg init_tmgclk2
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(13 downto 0) <= init_tmgclk2_osel_reg;
            rd_dat_d0(15 downto 14) <= (others => '0');
          when "10" =>
            -- Reg init_lemo
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(1 downto 0) <= init_lemo_gpio_reg;
            rd_dat_d0(15 downto 2) <= (others => '0');
          when "11" =>
            -- Reg init_lemo_ext
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(5 downto 0) <= init_lemo_ext_sel_reg;
            rd_dat_d0(15 downto 6) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00110" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_softstart
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(3 downto 0) <= init_softstart_sel_reg;
            rd_dat_d0(15 downto 4) <= (others => '0');
          when "01" =>
            -- Reg init_softstop
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(3 downto 0) <= init_softstop_sel_reg;
            rd_dat_d0(15 downto 4) <= (others => '0');
          when "10" =>
            -- Reg init_lemo_pulse
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(5 downto 0) <= init_lemo_pulse_ext_reg;
            rd_dat_d0(15 downto 6) <= (others => '0');
          when "11" =>
            -- Reg init_pin_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_pin_ctrl_ext_10m_dir_reg;
            rd_dat_d0(1) <= init_pin_ctrl_ext_pps_dir_reg;
            rd_dat_d0(15 downto 2) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00111" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_pll_status
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_pll_status_error_i;
            rd_dat_d0(1) <= init_pll_status_locked_i;
            rd_dat_d0(15 downto 2) <= (others => '0');
          when "01" =>
            -- Reg init_pll_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_pll_ctrl_sync_reg;
            rd_dat_d0(15 downto 1) <= (others => '0');
          when "10" =>
            -- Reg init_dds_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_dds_ctrl_reset_reg;
            rd_dat_d0(2 downto 1) <= (others => '0');
            rd_dat_d0(3) <= '0';
            rd_dat_d0(6 downto 4) <= init_dds_ctrl_profile_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "11" =>
            -- Reg init_dds_ioupdate
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(3 downto 0) <= init_dds_ioupdate_fdelay_reg;
            rd_dat_d0(8 downto 4) <= init_dds_ioupdate_odelay_reg;
            rd_dat_d0(15 downto 9) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "01000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_dds_status
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_dds_status_sync_error_i;
            rd_dat_d0(15 downto 1) <= (others => '0');
          when "10" =>
            -- Reg init_ocxo_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_ocxo_ctrl_enable_reg;
            rd_dat_d0(15 downto 1) <= (others => '0');
          when "11" =>
            -- Reg init_ocxo_uptime
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_ocxo_uptime_val_i;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_nco_azimuthal
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_nco_azimuthal
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_azimuthal_value_reg(47 downto 32);
          when "10" =>
            -- Reg init_nco_azimuthal
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_azimuthal_value_reg(31 downto 16);
          when "11" =>
            -- Reg init_nco_azimuthal
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_azimuthal_value_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10001" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_nco_cabledelay
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_nco_cabledelay
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_cabledelay_value_reg(47 downto 32);
          when "10" =>
            -- Reg init_nco_cabledelay
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_cabledelay_value_reg(31 downto 16);
          when "11" =>
            -- Reg init_nco_cabledelay
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_cabledelay_value_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10010" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_nco_hb
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(9 downto 0) <= init_nco_hb_value_reg;
            rd_dat_d0(15 downto 10) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10011" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_nco_h1_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_nco_h1_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_h1_ftw_value_reg(47 downto 32);
          when "10" =>
            -- Reg init_nco_h1_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_h1_ftw_value_reg(31 downto 16);
          when "11" =>
            -- Reg init_nco_h1_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_h1_ftw_value_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10100" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_nco_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_nco_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_h1_prog_value_reg(47 downto 32);
          when "10" =>
            -- Reg init_nco_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_h1_prog_value_reg(31 downto 16);
          when "11" =>
            -- Reg init_nco_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_nco_h1_prog_value_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10101" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_nco_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_nco_ctrl_reset_nco_reg;
            rd_dat_d0(1) <= init_nco_ctrl_reset_slip_reg;
            rd_dat_d0(2) <= init_nco_ctrl_reset_fsk_reg;
            rd_dat_d0(3) <= '0';
            rd_dat_d0(6 downto 4) <= init_nco_ctrl_rate_reg;
            rd_dat_d0(15 downto 7) <= (others => '0');
          when "01" =>
            -- Reg init_nco_update
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(15 downto 1) <= (others => '0');
          when "10" =>
            -- Reg init_nco_loc_or_wrs
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_nco_loc_or_wrs_params_sel_reg;
            rd_dat_d0(15 downto 1) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "11000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_svec_mup_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(3 downto 0) <= init_svec_mup_ctrl_gpio_sel_reg;
            rd_dat_d0(7 downto 4) <= init_svec_mup_ctrl_led_sel_reg;
            rd_dat_d0(8) <= init_svec_mup_ctrl_bclk_rfclk_sel_reg;
            rd_dat_d0(9) <= init_svec_mup_ctrl_ila_sel_reg;
            rd_dat_d0(15 downto 10) <= (others => '0');
          when "01" =>
            -- Reg init_svec_mup_rftrig
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= init_svec_mup_rftrig_t1stop_reg;
            rd_dat_d0(1) <= init_svec_mup_rftrig_t1start_reg;
            rd_dat_d0(2) <= init_svec_mup_rftrig_t2stop_reg;
            rd_dat_d0(3) <= init_svec_mup_rftrig_t2start_reg;
            rd_dat_d0(15 downto 4) <= (others => '0');
          when "10" =>
            -- Reg init_svec_mup_fmc1
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(4 downto 0) <= init_svec_mup_fmc1_term_reg;
            rd_dat_d0(9 downto 5) <= init_svec_mup_fmc1_oe_n_reg;
            rd_dat_d0(11 downto 10) <= init_svec_mup_fmc1_led_reg;
            rd_dat_d0(15 downto 12) <= (others => '0');
          when "11" =>
            -- Reg init_svec_mup_fmc2
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(4 downto 0) <= init_svec_mup_fmc2_term_reg;
            rd_dat_d0(9 downto 5) <= init_svec_mup_fmc2_oe_n_reg;
            rd_dat_d0(11 downto 10) <= init_svec_mup_fmc2_led_reg;
            rd_dat_d0(15 downto 12) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "00010" =>
        case adr_int(7 downto 3) is
        when "00000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_wrs_rxframe_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_ftw_value_i(47 downto 32);
          when "10" =>
            -- Reg init_wrs_rxframe_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_ftw_value_i(31 downto 16);
          when "11" =>
            -- Reg init_wrs_rxframe_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_ftw_value_i(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00001" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_ctrl
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_ctrl_i;
            when "1" =>
              -- Reg init_wrs_rxframe_counter
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_counter_i;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_rxwrtimestamp
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_rxwrtimestamp_i(31 downto 16);
            when "1" =>
              -- Reg init_wrs_rxframe_rxwrtimestamp
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_rxwrtimestamp_i(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00010" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_txwrtimestamp
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_txwrtimestamp_i(31 downto 16);
            when "1" =>
              -- Reg init_wrs_rxframe_txwrtimestamp
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_txwrtimestamp_i(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrs_rxframe_rftimestamp
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_rftimestamp_i(31 downto 16);
            when "1" =>
              -- Reg init_wrs_rxframe_rftimestamp
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrs_rxframe_rftimestamp_i(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00011" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_rfframe_ts
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(15 downto 1) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00100" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(7 downto 0) <= init_wrs_rxframe_nco_reset_tai_val_i(39 downto 32);
            rd_dat_d0(15 downto 8) <= (others => '0');
          when "10" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_nco_reset_tai_val_i(31 downto 16);
          when "11" =>
            -- Reg init_wrs_rxframe_nco_reset_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_nco_reset_tai_val_i(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00101" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_nco_reset_cycles
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(11 downto 0) <= init_wrs_rxframe_nco_reset_cycles_val_i(27 downto 16);
            rd_dat_d0(15 downto 12) <= (others => '0');
          when "01" =>
            -- Reg init_wrs_rxframe_nco_reset_cycles
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_nco_reset_cycles_val_i(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00110" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_wrs_rxframe_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(7 downto 0) <= init_wrs_rxframe_tai_val_i(39 downto 32);
            rd_dat_d0(15 downto 8) <= (others => '0');
          when "10" =>
            -- Reg init_wrs_rxframe_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_tai_val_i(31 downto 16);
          when "11" =>
            -- Reg init_wrs_rxframe_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_tai_val_i(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "00111" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrs_rxframe_cycles
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(11 downto 0) <= init_wrs_rxframe_cycles_val_i(27 downto 16);
            rd_dat_d0(15 downto 12) <= (others => '0');
          when "01" =>
            -- Reg init_wrs_rxframe_cycles
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrs_rxframe_cycles_val_i(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "01000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_wrc_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(15 downto 0) <= (others => '0');
          when "01" =>
            -- Reg init_wrc_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(7 downto 0) <= init_wrc_tai_value_i(39 downto 32);
            rd_dat_d0(15 downto 8) <= (others => '0');
          when "10" =>
            -- Reg init_wrc_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrc_tai_value_i(31 downto 16);
          when "11" =>
            -- Reg init_wrc_tai
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_wrc_tai_value_i(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "01001" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_cycles
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(11 downto 0) <= init_wrc_cycles_value_i(27 downto 16);
              rd_dat_d0(15 downto 12) <= (others => '0');
            when "1" =>
              -- Reg init_wrc_cycles
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrc_cycles_value_i(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_status
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= init_wrc_status_linkup_i;
              rd_dat_d0(1) <= init_wrc_status_time_valid_i;
              rd_dat_d0(15 downto 2) <= (others => '0');
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "01010" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_page0
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrc_page0_reg(31 downto 16);
            when "1" =>
              -- Reg init_wrc_page0
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrc_page0_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_wrc_page1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrc_page1_reg(31 downto 16);
            when "1" =>
              -- Reg init_wrc_page1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_wrc_page1_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_txframe_ftw_h1_main
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_main_reg(63 downto 48);
          when "01" =>
            -- Reg init_txframe_ftw_h1_main
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_main_reg(47 downto 32);
          when "10" =>
            -- Reg init_txframe_ftw_h1_main
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_main_reg(31 downto 16);
          when "11" =>
            -- Reg init_txframe_ftw_h1_main
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_main_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10001" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_txframe_ftw_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_prog_reg(63 downto 48);
          when "01" =>
            -- Reg init_txframe_ftw_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_prog_reg(47 downto 32);
          when "10" =>
            -- Reg init_txframe_ftw_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_prog_reg(31 downto 16);
          when "11" =>
            -- Reg init_txframe_ftw_h1_prog
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_prog_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10010" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg init_txframe_ftw_h1_on
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_on_reg(63 downto 48);
          when "01" =>
            -- Reg init_txframe_ftw_h1_on
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_on_reg(47 downto 32);
          when "10" =>
            -- Reg init_txframe_ftw_h1_on
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_on_reg(31 downto 16);
          when "11" =>
            -- Reg init_txframe_ftw_h1_on
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= init_txframe_ftw_h1_on_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10011" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_dftw_h1_slip1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_dftw_h1_slip1_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_dftw_h1_slip1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_dftw_h1_slip1_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_dftw_h1_slip2
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_dftw_h1_slip2_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_dftw_h1_slip2
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_dftw_h1_slip2_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10100" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint1_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint1_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint2
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint2_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint2
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint2_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10101" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint3
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint3_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint3
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint3_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint4
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint4_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint4
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint4_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10110" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint5
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint5_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint5
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint5_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint6
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint6_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint6
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint6_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "10111" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint7
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint7_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint7
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint7_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_setpoint8
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint8_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_setpoint8
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_setpoint8_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "11000" =>
          case adr_int(2 downto 2) is
          when "0" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_noise
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_noise_reg(31 downto 16);
            when "1" =>
              -- Reg init_txframe_noise
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_noise_reg(15 downto 0);
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "1" =>
            case adr_int(1 downto 1) is
            when "0" =>
              -- Reg init_txframe_control
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= init_txframe_control_reg;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "00011" =>
        case adr_int(7 downto 6) is
        when "00" =>
          case adr_int(5 downto 5) is
          when "0" =>
            -- Submap init_pll_spi
            init_pll_spi_re <= rd_req_int;
            rd_dat_d0 <= init_pll_spi_i.dat(15 downto 0);
            rd_ack_d0 <= init_pll_spi_rack;
          when "1" =>
            -- Submap init_rf_spi
            init_rf_spi_re <= rd_req_int;
            rd_dat_d0 <= init_rf_spi_i.dat(15 downto 0);
            rd_ack_d0 <= init_rf_spi_rack;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "01" =>
          -- Submap init_rf
          init_rf_re <= rd_req_int;
          rd_dat_d0 <= init_rf_i.dat(15 downto 0);
          rd_ack_d0 <= init_rf_rack;
        when "10" =>
          -- Submap init_framerxtx
          init_framerxtx_re <= rd_req_int;
          rd_dat_d0 <= init_framerxtx_i.dat(15 downto 0);
          rd_ack_d0 <= init_framerxtx_rack;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "00100" =>
        -- Submap init_xadc
        init_xadc_re <= rd_req_int;
        rd_dat_d0 <= init_xadc_i.dat(15 downto 0);
        rd_ack_d0 <= init_xadc_rack;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "01" =>
      -- Submap init_wrpc
      init_wrpc_re <= rd_req_int;
      rd_dat_d0 <= init_wrpc_i.dat(15 downto 0);
      rd_ack_d0 <= init_wrpc_rack;
    when "10" =>
      case adr_int(12 downto 12) is
      when "0" =>
        case adr_int(11 downto 9) is
        when "000" =>
          -- Submap ctrl_rf1_vtus
          ctrl_rf1_vtus_re <= rd_req_int;
          rd_dat_d0 <= ctrl_rf1_vtus_i.dat(15 downto 0);
          rd_ack_d0 <= ctrl_rf1_vtus_rack;
        when "001" =>
          -- Submap ctrl_rf2_vtus
          ctrl_rf2_vtus_re <= rd_req_int;
          rd_dat_d0 <= ctrl_rf2_vtus_i.dat(15 downto 0);
          rd_ack_d0 <= ctrl_rf2_vtus_rack;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "1" =>
        -- Submap ctrl_rf1_rfnco
        ctrl_rf1_rfnco_re <= rd_req_int;
        rd_dat_d0 <= ctrl_rf1_rfnco_i.dat(15 downto 0);
        rd_ack_d0 <= ctrl_rf1_rfnco_rack;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "11" =>
      case adr_int(12 downto 12) is
      when "0" =>
        -- Submap ctrl_rf2_rfnco
        ctrl_rf2_rfnco_re <= rd_req_int;
        rd_dat_d0 <= ctrl_rf2_rfnco_i.dat(15 downto 0);
        rd_ack_d0 <= ctrl_rf2_rfnco_rack;
      when "1" =>
        case adr_int(11 downto 3) is
        when "000000000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_phase
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_iqdac_phase_reg;
          when "01" =>
            -- Reg ctrl_rf2_iqdac_phase
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_iqdac_phase_reg;
          when "10" =>
            -- Reg ctrl_rf1_iqdac_phase_update
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(15 downto 1) <= (others => '0');
          when "11" =>
            -- Reg ctrl_rf2_iqdac_phase_update
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= '0';
            rd_dat_d0(15 downto 1) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000001" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_igain_arm
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_iqdac_igain_arm_reg;
          when "01" =>
            -- Reg ctrl_rf1_iqdac_qgain_arm
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_iqdac_qgain_arm_reg;
          when "10" =>
            -- Reg ctrl_rf2_iqdac_igain_arm
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_iqdac_igain_arm_reg;
          when "11" =>
            -- Reg ctrl_rf2_iqdac_qgain_arm
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_iqdac_qgain_arm_reg;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000010" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_igain
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_iqdac_igain_i;
          when "01" =>
            -- Reg ctrl_rf1_iqdac_qgain
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_iqdac_qgain_i;
          when "10" =>
            -- Reg ctrl_rf2_iqdac_igain
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_iqdac_igain_i;
          when "11" =>
            -- Reg ctrl_rf2_iqdac_qgain
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_iqdac_qgain_i;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000011" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_iqdac_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_iqdac_ctrl_reg;
          when "01" =>
            -- Reg ctrl_rf2_iqdac_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_iqdac_ctrl_reg;
          when "10" =>
            -- Reg ctrl_iqdac_ram_addr
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_iqdac_ram_addr_reg;
          when "11" =>
            -- Reg ctrl_iqdac_ram_data
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_iqdac_ram_data_reg;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000100" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_iqdac_ram_write
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_iqdac_ram_write_reg;
          when "01" =>
            -- Reg ctrl_iqdac_ram_play
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_iqdac_ram_play_reg;
          when "10" =>
            -- Reg ctrl_rf1_dds_ftw_valid
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_dds_ftw_valid_reg;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000101" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf1_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_dds_ftw_reg(63 downto 48);
          when "01" =>
            -- Reg ctrl_rf1_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_dds_ftw_reg(47 downto 32);
          when "10" =>
            -- Reg ctrl_rf1_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_dds_ftw_reg(31 downto 16);
          when "11" =>
            -- Reg ctrl_rf1_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf1_dds_ftw_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000110" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf2_dds_ftw_valid
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_dds_ftw_valid_reg;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000000111" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_rf2_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_dds_ftw_reg(63 downto 48);
          when "01" =>
            -- Reg ctrl_rf2_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_dds_ftw_reg(47 downto 32);
          when "10" =>
            -- Reg ctrl_rf2_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_dds_ftw_reg(31 downto 16);
          when "11" =>
            -- Reg ctrl_rf2_dds_ftw
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0 <= ctrl_rf2_dds_ftw_reg(15 downto 0);
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "000001000" =>
          case adr_int(2 downto 1) is
          when "00" =>
            -- Reg ctrl_nco_reset_ctrl
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= ctrl_nco_reset_ctrl_mask_dds_reg;
            rd_dat_d0(1) <= ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg;
            rd_dat_d0(2) <= ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg;
            rd_dat_d0(3) <= ctrl_nco_reset_ctrl_mask_rf1_trig1_reg;
            rd_dat_d0(4) <= ctrl_nco_reset_ctrl_mask_rf2_trig1_reg;
            rd_dat_d0(5) <= '0';
            rd_dat_d0(15 downto 6) <= (others => '0');
          when "01" =>
            -- Reg ctrl_gbl_status
            rd_ack_d0 <= rd_req_int;
            rd_dat_d0(0) <= ctrl_gbl_status_rf1_t1_start_reg;
            rd_dat_d0(1) <= ctrl_gbl_status_rf1_t2_start_reg;
            rd_dat_d0(2) <= ctrl_gbl_status_rf2_t1_start_reg;
            rd_dat_d0(3) <= ctrl_gbl_status_rf2_t2_start_reg;
            rd_dat_d0(15 downto 4) <= (others => '0');
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
