#ifndef __CHEBY__WR2RF_INIT_RF_CH_REGS__H__
#define __CHEBY__WR2RF_INIT_RF_CH_REGS__H__
#define WR2RF_INIT_RF_CH_REGS_SIZE 12 /* 0xc */

/* Control register for both channels */
#define WR2RF_INIT_RF_CH_REGS_COMMON 0x0UL
#define WR2RF_INIT_RF_CH_REGS_COMMON_MIXER_EN 0x1UL
#define WR2RF_INIT_RF_CH_REGS_COMMON_MUX_SEL_MASK 0x6UL
#define WR2RF_INIT_RF_CH_REGS_COMMON_MUX_SEL_SHIFT 1
#define WR2RF_INIT_RF_CH_REGS_COMMON_IQDAC_RESET 0x8UL
#define WR2RF_INIT_RF_CH_REGS_COMMON_START_LPBK 0x10UL

/* Determines for how many sys-cycles (16 ns) cdelay, and slipped by fdelay (1 ns) the nco_reset will be delayed before reaching the primary trigger unit. */
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY 0x2UL
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_CDELAY_MASK 0x7fUL
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_CDELAY_SHIFT 0
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_FDELAY_MASK 0x780UL
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_FDELAY_SHIFT 7
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_ODELAY_MASK 0xf800UL
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_ODELAY_SHIFT 11

/* How many sys-cycles is the rst applied less than cdelay */
#define WR2RF_INIT_RF_CH_REGS_RST_CDELAY 0x4UL
#define WR2RF_INIT_RF_CH_REGS_RST_CDELAY_OFFSET_MASK 0x7fUL
#define WR2RF_INIT_RF_CH_REGS_RST_CDELAY_OFFSET_SHIFT 0

/* None */
#define WR2RF_INIT_RF_CH_REGS_CH 0x8UL
#define WR2RF_INIT_RF_CH_REGS_CH_SIZE 2 /* 0x2 */

/* None */
#define WR2RF_INIT_RF_CH_REGS_CH_CSR 0x0UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_DELAY_OEN 0x1UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_MUX_SEL 0x2UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_TRIG_RST 0x4UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_DELAY_LATCH 0x8UL

#ifndef __ASSEMBLER__
struct wr2rf_init_rf_ch_regs {
  /* [0x0]: REG (rw) Control register for both channels */
  uint16_t common;

  /* [0x2]: REG (rw) Determines for how many sys-cycles (16 ns) cdelay, and slipped by fdelay (1 ns) the nco_reset will be delayed before reaching the primary trigger unit. */
  uint16_t t1_sync_progdelay;

  /* [0x4]: REG (rw) How many sys-cycles is the rst applied less than cdelay */
  uint16_t rst_cdelay;

  /* padding to: 8 words */
  uint8_t __padding_0[2];

  /* [0x8]: REPEAT (no description) */
  struct ch {
    /* [0x0]: REG (rw) (no description) */
    uint16_t csr;
  } ch[2];
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__WR2RF_INIT_RF_CH_REGS__H__ */
