action = "simulation"
target = "xilinx"
sim_tool = "modelsim"
sim_top = "tb_svec_wr2rf_vme"
vcom_opt = "-93 -mixedsvvh"

svec_template_ucf = []
syn_device = "xc6slx150t"  # For rams.
board = "svec"
ctrls = ["bank4_64b_32b"]

# Allow the user to override fetchto using:
#  hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
  fetchto = "../../ip_cores"

#include_dirs=[fetchto + "/vme64x-core/hdl/sim/vme64x_bfm",
#              fetchto + "/general-cores/sim"]

files = [ "tb_svec_wr2rf_vme.vhd"]

modules = {
  "local" :  [
    "../../rtl",
    "../../top/svec",
    "../../../../svec/hdl/sim/vhdl_sim"],
  "git" : [
      "https://ohwr.org/project/general-cores.git",
      "https://ohwr.org/project/vme64x-core.git",
  ],
  "system" : ["xilinx"]
}
