#ifndef __BOARD_H_
#define __BOARD_H_

#include "io.h"

/* For ocxo */
int libwr2rf_get_ocxo_current_ma(struct libwr2rf_dev *dev);

/* For the main pll (ltc6950).  */
void libwr2rf_pll_spi_init(struct libwr2rf_dev *dev);
uint8_t libwr2rf_pll_read(struct libwr2rf_dev *dev, unsigned reg);
void libwr2rf_pll_write(struct libwr2rf_dev *dev, unsigned reg, uint8_t value);

/* For the dds (ad9910).  */
void libwr2rf_dds_spi_init(struct libwr2rf_dev *dev);  /* Note: common to dds and dac.  */
int libwr2rf_dds_init(struct libwr2rf_dev *dev, unsigned io_update);  /* In ad9910_init.c  */
void libwr2rf_dds_reset(struct libwr2rf_dev *dev, unsigned reset);
void libwr2rf_dds_reset_pulse(struct libwr2rf_dev *dev);
void libwr2rf_dds_configure_sync(struct libwr2rf_dev *dev, int sync_receiver_enable,
                                 int sync_receiver_delay, int sync_validation_delay);
void libwr2rf_dds_sync_calibrate (struct libwr2rf_dev *dev, int verbose);

/* For initialising the IODELAY_CONTROLLERS */
void libwr2rf_iodelay_init(struct libwr2rf_dev *dev);

/* Write and read a DDS register (using spi).  */
void libwr2rf_dds_write(struct libwr2rf_dev *dev, unsigned reg,
                          uint64_t value, unsigned nbits);
uint64_t libwr2rf_dds_read(struct libwr2rf_dev *dev, unsigned reg, unsigned nbits);

int libwr2rf_dds_freq_init(struct libwr2rf_dev *dev,
                           uint64_t freq, unsigned io_update);

/* Trigger ioupdate.  */
void libwr2rf_dds_ioupdate(struct libwr2rf_dev *dev);

/* Read the sync_error input.  */
unsigned libwr2rf_dds_sync_error(struct libwr2rf_dev *dev);

/* Read/write a DAC register.  DEV must be DAC1_CS or DAC2_CS.  */
uint8_t libwr2rf_dac_read(struct libwr2rf_dev *dev, unsigned ch, unsigned reg);
void libwr2rf_dac_write(struct libwr2rf_dev *dev, unsigned ch, unsigned reg,
                        uint8_t value);

/* From dac_timing.c:  */
void libwr2rf_dac_init(struct libwr2rf_dev *dev, unsigned ch);
int libwr2rf_dac_port_timing(struct libwr2rf_dev *dev, unsigned ch);
int libwr2rf_dac_validate_timing(struct libwr2rf_dev *dev, unsigned ch);
void libwr2rf_dac_set_timing_delay(struct libwr2rf_dev *dev, unsigned ch, unsigned v);

/* Adjust phase and amplitude of DAC CH.  */
int libwr2rf_dac_phase_amp_ext(struct libwr2rf_dev *dev, unsigned ch,
                               float amplitude, float phase, unsigned verbose);

/* Raw 32bit IOs through the wb16 to wb32 bridge.  */
uint32_t libwr2rf_16x32_read32(struct libwr2rf_dev *dev, unsigned off);
void libwr2rf_16x32_write32(struct libwr2rf_dev *dev, unsigned off,
                            uint32_t val);

void libwr2rf_16x32_write64(struct libwr2rf_dev *dev, unsigned off,
                            uint64_t val);

/* Regular BE 32bit IOs.  Not atomic.  */
uint32_t libwr2rf_be_read32(struct libwr2rf_dev *dev, unsigned off);
void libwr2rf_be_write32(struct libwr2rf_dev *dev, unsigned off, uint32_t val);

/* Regular BE 64bit IOs.  Not atomic.  */
uint64_t libwr2rf_be_read64(struct libwr2rf_dev *dev, unsigned off);
void libwr2rf_be_write64(struct libwr2rf_dev *dev, unsigned off, uint64_t val);

/* A WR core register.  Atomic but require to set the page. */
uint32_t libwr2rf_wrc_read32(struct libwr2rf_dev *dev, unsigned off);
void libwr2rf_wrc_write32(struct libwr2rf_dev *dev, unsigned off, uint32_t val);

void libwr2rf_vtu_dump_by_addr(struct libwr2rf_dev *dev, unsigned addr);
const char *libwr2rf_vtu_get_mode_by_index(unsigned idx);
int libwr2rf_vtu_get_mode_by_name(const char *name);

/* Set the rf reset offset delay wrt nco_reset_cdelayed */
int libwr2rf_vtu_rf_reset_offset (struct libwr2rf_dev *dev, unsigned id, unsigned wr_cycles);

#endif /* __BOARD_H_ */
