--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- WR2RF_VME core
-- https://ohwr.org/project/vme-rf-wr-bobr
--------------------------------------------------------------------------------
--
-- unit name:   wr2rf_vme
--
-- description: top level for the wr2rf_vme board
--
--------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN (home.cern)
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wrcore_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
use work.RFFrameTransceiver_pkg.all;

entity wr2rf_vme is

  generic (
    g_simulation          : integer := 0;
    g_dpram_size          : integer := 131072/4;
    g_dpram_initf         : string  := "../../../../dependencies/wrpc-sw-file/wrc.bram";
    g_dpram_initf         : string  := "";
    g_diag_id             : integer := 0;
    g_diag_ver            : integer := 0;
    g_diag_ro_size        : integer := 0;
    g_diag_rw_size        : integer := 0;
    g_fabric_iface        : t_board_fabric_iface := STREAMERS;
    g_streamers_op_mode   : t_streamers_op_mode  := TX_AND_RX;
    g_tx_streamer_params  : t_tx_streamer_params := c_tx_streamer_params_RF;
    g_rx_streamer_params  : t_rx_streamer_params := c_rx_streamer_params_RF;
    g_ftw_length          : natural := 48;
    g_offset_length       : natural := 48;
    g_ila_debug           : string  := "standard" ); -- standard, rfnco

  port (
    ---------------------------------------------------------------------------
    -- VME interface D16 A24
    -- Note: retry, berr not required
    --       addr is input only.
    ---------------------------------------------------------------------------

    vme_write_n_i    : in    std_logic;
    vme_sysreset_n_i : in    std_logic;
    vme_retry_oe_o   : out   std_logic;
    vme_retry_n_o    : out   std_logic;
    vme_lword_n_b    : inout std_logic;
    vme_iackout_n_o  : out   std_logic;
    vme_iackin_n_i   : in    std_logic;
    vme_iack_n_i     : in    std_logic;
    vme_dtack_oe_o   : out   std_logic;
    vme_dtack_n_o    : out   std_logic;
    vme_ds_n_i       : in    std_logic_vector(1 downto 0);
    vme_data_oe_n_o  : out   std_logic;
    vme_data_dir_o   : out   std_logic;
    vme_berr_o       : out   std_logic;
    vme_as_n_i       : in    std_logic;
    vme_irq_o        : out   std_logic_vector(7 downto 1);
    vme_data_b       : inout std_logic_vector(15 downto 0);
    vme_am_i         : in    std_logic_vector(5 downto 0);
    vme_addr_b       : inout std_logic_vector(23 downto 1);
    vme_addr_dir_o   : out   std_logic;
    vme_addr_oe_n_o  : out   std_logic;

    --  Geographic address
    vme_gap_i        : in    std_logic;
    vme_ga_n_i       : in    std_logic_vector(4 downto 0);

    --  Switches in absence of vme64x.
    vme_noga_n_i     : in    std_logic_vector(4 downto 0);
    switch_n         : in    std_logic_vector(2 downto 0);

    -- 62.5MHz + offset clock for DDMTD.
    clk_dmtd_62m5_p_i : in std_logic;
    clk_dmtd_62m5_n_i : in std_logic;

    -- 125 MHz Clock for Xilinx GTX transceiver.
    clk_125m_gtx_n_i : in    std_logic;
    clk_125m_gtx_p_i : in    std_logic;

    -- 62.5 MHz system clock from
    clk_sys_62m5_p_i : in std_logic;
    clk_sys_62m5_n_i : in std_logic;

    -- 10 MHz external reference clock.
    clk_ext_10m_p_i : in std_logic;
    clk_ext_10m_n_i : in std_logic;
    clk_ext_10m_o   : out std_logic;
    ext_10m_dir_o   : out std_logic;
    ext_pps_dir_o   : out std_logic;

    --  SFP 1
    sfp1_tx_n_o        : out   std_logic;
    sfp1_tx_p_o        : out   std_logic;
    sfp1_rx_n_i        : in    std_logic;
    sfp1_rx_p_i        : in    std_logic;
    sfp1_tx_fault_i    : in    std_logic;
    sfp1_los_i         : in    std_logic;
    sfp1_tx_disable_o  : out   std_logic;

    sfp1_led_active_o  : out   std_logic;
    sfp1_led_link_o    : out   std_logic;
    sfp1_detect_i      : in    std_logic;
    sfp1_rate_select_o : out   std_logic;
    sfp1_scl_b         : inout std_logic;
    sfp1_sda_b         : inout std_logic;

    --  SFP 2
    --sfp2_tx_n_o        : out   std_logic;
    --sfp2_tx_p_o        : out   std_logic;
    --sfp2_rx_n_i        : in    std_logic;
    --sfp2_rx_p_i        : in    std_logic;
    sfp2_tx_fault_i    : in    std_logic;
    sfp2_los_i         : in    std_logic;
    sfp2_tx_disable_o  : out   std_logic;

    sfp2_led_active_o  : out   std_logic;
    sfp2_led_link_o    : out   std_logic;
    sfp2_detect_i      : in    std_logic;
    sfp2_rate_select_o : out   std_logic;
    sfp2_scl_b         : inout std_logic;
    sfp2_sda_b         : inout std_logic;

    -- PPS IN & OUT
    pps_i : in  std_logic;
    pps_o : out std_logic;

    -- dac ddmtd offset clock
    wr_dac_dmtd_sclk_o   : out std_logic;
    wr_dac_dmtd_din_o    : out std_logic;
    wr_dac_dmtd_cs_n_o   : out std_logic;

    -- dac internal WR timebase
    wr_dac_ocxo_sclk_o   : out std_logic;
    wr_dac_ocxo_din_o    : out std_logic;
    wr_dac_ocxo_cs_n_o   : out std_logic;

    -- Firmware flash
    spi_flash_cs_n_o   : out std_logic;
    spi_flash_miso_i   : in  std_logic;
    spi_flash_mosi_o   : out std_logic;

    --  WR eeprom
    wr_eeprom1_scl_b       : inout std_logic;
    wr_eeprom1_sda_b       : inout std_logic;
    wr_eeprom2_scl_b       : inout std_logic;
    wr_eeprom2_sda_b       : inout std_logic;

    -- Onewire
    wr_onewire_b       : inout std_logic;

    -- OCXO
    ocxo_en_o          : out   std_logic;
    ocxo_sense_n_i     : in  std_logic;
    ocxo_sense_p_i     : in  std_logic;

    -- timing_io
    tmg_clk_i          : in    std_logic_vector(2 downto 1);
    tmg_clk_o          : out   std_logic_vector(2 downto 1);
    tmg_clk_oe_n_o     : out   std_logic_vector(2 downto 1);
    tmg_clk_term_en_o  : out   std_logic_vector(2 downto 1);
    tmg_io_i           : in    std_logic_vector(4 downto 1);
    tmg_io_o           : out   std_logic_vector(4 downto 1);
    tmg_io_oe_n_o      : out   std_logic_vector(4 downto 1);
    tmg_io_term_en_o   : out   std_logic_vector(4 downto 1);

    -- rf1 iqdac
    rf1_iqdac_data_p_o : out std_logic_vector(15 downto 0);
    rf1_iqdac_data_n_o : out std_logic_vector(15 downto 0);
    rf1_iqdac_dci_p_o  : out std_logic;
    rf1_iqdac_dci_n_o  : out std_logic;
    rf1_iqdac_reset_o  : out std_logic;

    -- rf2 iqdac
    rf2_iqdac_data_p_o : out std_logic_vector(15 downto 0);
    rf2_iqdac_data_n_o : out std_logic_vector(15 downto 0);
    rf2_iqdac_dci_p_o  : out std_logic;
    rf2_iqdac_dci_n_o  : out std_logic;
    rf2_iqdac_reset_o  : out std_logic;

    -- rf1 channel
    rf1_sync_p_o       : inout std_logic;
    rf1_sync_n_o       : inout std_logic;

    -- rf1 trigger1 channel
    rf1_t1_clk_p_i     : in  std_logic;
    rf1_t1_clk_n_i     : in  std_logic;
    rf1_t1_p_o         : inout std_logic;
    rf1_t1_n_o         : inout std_logic;
    rf1_t1_rst_p_o     : out std_logic;
    rf1_t1_rst_n_o     : out std_logic;

    -- rf1 trigger2 channel
    rf1_t2_clk_p_i     : in  std_logic;
    rf1_t2_clk_n_i     : in  std_logic;
    rf1_t2_p_o         : inout std_logic;
    rf1_t2_n_o         : inout std_logic;
    rf1_t2_rst_p_o     : out std_logic;
    rf1_t2_rst_n_o     : out std_logic;

    -- rf2 channel
    rf2_sync_p_o       : inout std_logic;
    rf2_sync_n_o       : inout std_logic;

    -- rf2 trigger1 channel
    rf2_t1_clk_p_i     : in  std_logic;
    rf2_t1_clk_n_i     : in  std_logic;
    rf2_t1_p_o         : inout std_logic;
    rf2_t1_n_o         : inout std_logic;
    rf2_t1_rst_p_o     : out std_logic;
    rf2_t1_rst_n_o     : out std_logic;

    -- rf2 trigger2 channel
    rf2_t2_clk_p_i     : in  std_logic;
    rf2_t2_clk_n_i     : in  std_logic;
    rf2_t2_p_o         : inout std_logic;
    rf2_t2_n_o         : inout std_logic;
    rf2_t2_rst_p_o     : out std_logic;
    rf2_t2_rst_n_o     : out std_logic;

    -- vme p0
    vme_p0_h1_bsb_o    : out std_logic_vector(7 downto 0);
    vme_p0_h1_c40_o    : out std_logic;
    vme_p0_h1_lbb_o   : out std_logic_vector(7 downto 0);
    vme_p0_h1_hbb_o   : out std_logic_vector(7 downto 0);
    vme_p0_h1_tc_o     : out std_logic;
    vme_p0_h2_bsb_o    : out std_logic_vector(7 downto 0);
    vme_p0_h2_c40_o    : out std_logic;
    vme_p0_h2_lbb_o   : out std_logic_vector(7 downto 0);
    vme_p0_h2_hbb_o   : out std_logic_vector(7 downto 0);
    vme_p0_h2_tc_o     : out std_logic;
    vme_p0_oen_o       : out std_logic;

    --  SPI for DDS and DACs
    dds_cs_n_o         : out std_logic;
    rf1_iqdac_cs_n_o   : out std_logic;
    rf2_iqdac_cs_n_o   : out std_logic;
    rf_sclk_o          : out std_logic;
    rf_sdi_o           : out std_logic;
    rf_sdo_i           : in  std_logic;

    -- DDS control
    dds_profile_o      : out std_logic_vector(2 downto 0);
    dds_ioupdate_o     : out std_logic;
    dds_sync_p_o       : out std_logic;
    dds_sync_n_o       : out std_logic;
    dds_sync_error_i   : in  std_logic;
    dds_reset_o        : out std_logic;

    -- SPI for PLL (ltc6950)
    pll_main_cs_n_o : out std_logic;
    pll_main_sclk_o : out std_logic;
    pll_main_sdi_o  : out std_logic;
    pll_main_sdo_i  : in  std_logic;
    pll_main_stat_i : in  std_logic_vector(2 downto 1);
    pll_main_sync_o : out std_logic;

    --  RF 1
    rf1_mux_sel_o        : out std_logic_vector(1 downto 0);
    rf1_mixer_en_o       : out std_logic;
    rf1_t1_delay_latch_o : out std_logic;
    rf1_t1_delay_oen_o   : out std_logic;
    rf1_t1_mux_sel_o     : out std_logic;
    rf1_t2_delay_latch_o : out std_logic;
    rf1_t2_delay_oen_o   : out std_logic;
    rf1_t2_mux_sel_o     : out std_logic;

    --  RF 2
    rf2_mux_sel_o        : out std_logic_vector(1 downto 0);
    rf2_mixer_en_o       : out std_logic;
    rf2_t1_delay_latch_o : out std_logic;
    rf2_t1_delay_oen_o   : out std_logic;
    rf2_t1_mux_sel_o     : out std_logic;
    rf2_t2_delay_latch_o : out std_logic;
    rf2_t2_delay_oen_o   : out std_logic;
    rf2_t2_mux_sel_o     : out std_logic;

    rf_trig_ff_delay_o   : out std_logic_vector(9 downto 0) );

  attribute keep_hierarchy : string;
  attribute shreg_extract  : string;
  attribute keep_hierarchy of wr2rf_vme : entity is "yes";
  attribute shreg_extract  of wr2rf_vme : entity is "no";

end wr2rf_vme;

architecture rtl of wr2rf_vme is

  constant c_pcs_data_width : integer := 16;

  subtype t_poweron_counter is natural range 0 to 24;
  signal poweron_counter : t_poweron_counter := t_poweron_counter'high;
  signal rst_sys_n_r     : std_logic;
  signal rst_sys_r       : std_logic;
  signal rst_sys_n       : std_logic;
  signal rst_sys         : std_logic;

  signal clk62m5          : std_logic;
  signal clk125m          : std_logic;
  signal clk200m          : std_logic;
  signal clk250m          : std_logic;
  signal clk500m          : std_logic;
  signal rst_clk62m5_n    : std_logic;
  signal rst_clk62m5      : std_logic;
  signal rst_clk125m_n    : std_logic;
  signal rst_clk125m      : std_logic;
  signal rst_clk200m_n    : std_logic;
  signal rst_clk200m      : std_logic;
  signal rst_clk250m_n    : std_logic;
  signal rst_clk250m      : std_logic;
  signal rst_clk500m_n    : std_logic;
  signal rst_clk500m      : std_logic;

  -- Wishbone bus from master
  signal wb_vme_out : t_wishbone_master_out;
  signal wb_vme_in  : t_wishbone_master_in;

  -- VME
  signal vme_data_b_out     : std_logic_vector(15 downto 0);
  signal vme_data_b_out1    : std_logic_vector(31 downto 16);
  signal vme_addr_b_out     : std_logic_vector(31 downto 1);
  signal vme_lword_n_b_out  : std_logic;
  signal vme_data_dir_int   : std_logic;
  signal vme_ga             : std_logic_vector(5 downto 0);
  signal vme_berr_n_o       : std_logic;
  signal vme_irq_n_o        : std_logic_vector(7 downto 1);

  signal vme_nogap          : std_logic;

  signal clk_dmtd_62m5      : std_logic;
  signal clk_sys_62m5       : std_logic;
  signal clk_sys_62m5_in    : std_logic;
  signal clk_ext_10m_in     : std_logic;
  signal clk_ext_10m        : std_logic;
  signal clk_gtx_125m       : std_logic;

  signal clk_sys_select     : std_logic;
  signal clk_sys_reset      : std_logic;

  signal ext_10m_dir        : std_logic;
  signal ext_pps_dir        : std_logic;
  signal clk_ext_stopped    : std_logic;
  signal clk_ext_mul_locked : std_logic;
  signal clk_ext_mul        : std_logic;
  signal clk_ext_rst        : std_logic;


  --loopen_i determines (7 Series Transceiver User Guide(UG476) Figure 2-23 and Table 2-37):
  --'0' => gtx_loopback = "000" => normal operation
  --'1' => gtx_loopback = "100" => Far-end PMA Loopback
  signal phy16_out :t_phy_16bits_from_wrc;
  signal phy16_in :t_phy_16bits_to_wrc;

  signal phy_rst          : std_logic;

  signal phy_mdio_out  : t_wishbone_master_out;
  signal phy_mdio_in   : t_wishbone_master_in;

  signal pps_p     : std_logic;
  signal pps_csync : std_logic;

  signal dac_hpll_load_p1_o : std_logic;
  signal dac_dpll_load_p1_o : std_logic;
  signal dac_hpll_data_o    : std_logic_vector(15 downto 0);
  signal dac_dpll_data_o    : std_logic_vector(15 downto 0);

  signal sfp1_scl_out : std_logic;
  signal sfp1_scl_in  : std_logic;
  signal sfp1_sda_out : std_logic;
  signal sfp1_sda_in  : std_logic;

  signal wr1_scl_out : std_logic;
  signal wr1_scl_in  : std_logic;
  signal wr1_sda_out : std_logic;
  signal wr1_sda_in  : std_logic;

  signal ocxo_enabled : std_logic;
  signal ocxo_uptime  : std_logic_vector(15 downto 0);

  signal owr_en : std_logic_vector(1 downto 0);
  signal owr_i  : std_logic_vector(1 downto 0);

  signal wb_wrc_in  : t_wishbone_master_out;
  signal wb_wrc_out : t_wishbone_master_in;
  signal wb_wrc_out2 : t_wishbone_master_in;

  signal rf1_clk_bufg   : std_logic;
  signal rf2_clk_bufg   : std_logic;

  signal rf1_frev      : std_logic;
  signal rf1_frev_main : std_logic;
  signal rf2_frev      : std_logic;
  signal rf2_frev_main : std_logic;
  signal lemo_gpio     : std_logic_vector(2 downto 1);
  signal lemo_ext_sel  : std_logic_vector(6 downto 1);
  signal rf1_t1_rst    : std_logic;
  signal rf1_t2_rst    : std_logic;
  signal rf2_t1_rst    : std_logic;
  signal rf2_t2_rst    : std_logic;
  attribute dont_touch : string;
  attribute dont_touch of rf1_t1_rst : signal is "true";
  attribute dont_touch of rf1_t2_rst : signal is "true";
  attribute dont_touch of rf2_t1_rst : signal is "true";
  attribute dont_touch of rf2_t2_rst : signal is "true";
  signal rf1_t1_start  : std_logic;
  signal rf1_t2_start  : std_logic;
  signal rf2_t1_start  : std_logic;
  signal rf2_t2_start  : std_logic;
  signal rf1_t1_stop   : std_logic;
  signal rf1_t2_stop   : std_logic;
  signal rf2_t1_stop   : std_logic;
  signal rf2_t2_stop   : std_logic;

  signal rf1_t1_vtu_start_p, rf1_t2_vtu_start_p : std_logic;
  signal rf2_t1_vtu_start_p, rf2_t2_vtu_start_p : std_logic;

  signal rf1_start_lpbk : std_logic;
  signal rf2_start_lpbk : std_logic;

  signal rf1_rst_cdelay_offset : std_logic_vector(6 downto 0);
  signal rf1_t1_sync_cdelay : std_logic_vector(6 downto 0);
  signal rf1_t1_sync_fdelay : std_logic_vector(3 downto 0);
  signal rf1_t1_sync_odelay : std_logic_vector(4 downto 0);
  signal rf2_rst_cdelay_offset : std_logic_vector(6 downto 0);
  signal rf2_t1_sync_cdelay : std_logic_vector(6 downto 0);
  signal rf2_t1_sync_fdelay : std_logic_vector(3 downto 0);
  signal rf2_t1_sync_odelay : std_logic_vector(4 downto 0);

  signal rf_trig_ff_delay   : std_logic_vector(9 downto 0);
  signal rf1_t1_delay_latch : std_logic;
  signal rf1_t2_delay_latch : std_logic;
  signal rf2_t1_delay_latch : std_logic;
  signal rf2_t2_delay_latch : std_logic;

  signal mmcm_locked      : std_logic;
  signal wrcore_reset_n   : std_logic;
  signal iodelay_reset    : std_logic;

  signal wb_rf1_vtus_in       : t_wishbone_master_in;
  signal wb_rf1_vtus_out      : t_wishbone_master_out;

  signal wb_rf2_vtus_in       : t_wishbone_master_in;
  signal wb_rf2_vtus_out      : t_wishbone_master_out;

  signal mmcm_shift_incdec : std_logic;
  signal mmcm_shift_en     : std_logic;
  signal mmcm_shift_busy   : std_logic;

  signal tmg_clk_oe_o         : std_logic_vector(2 downto 1);
  signal tmg_io_oe_o          : std_logic_vector(4 downto 1);

  signal tmgio1_osel     : std_logic_vector(13 downto 0);
  signal tmgio2_osel     : std_logic_vector(13 downto 0);
  signal tmgio3_osel     : std_logic_vector(13 downto 0);
  signal tmgio4_osel     : std_logic_vector(13 downto 0);
  signal tmgclk1_osel    : std_logic_vector(13 downto 0);
  signal tmgclk2_osel    : std_logic_vector(13 downto 0);

  signal rf1_t1_start_sel : std_logic_vector(6 downto 1);
  signal rf1_t2_start_sel : std_logic_vector(6 downto 1);
  signal rf2_t1_start_sel : std_logic_vector(6 downto 1);
  signal rf2_t2_start_sel : std_logic_vector(6 downto 1);
  signal rf1_t1_stop_sel  : std_logic_vector(6 downto 1);
  signal rf1_t2_stop_sel  : std_logic_vector(6 downto 1);
  signal rf2_t1_stop_sel  : std_logic_vector(6 downto 1);
  signal rf2_t2_stop_sel  : std_logic_vector(6 downto 1);

  signal pps           : std_logic;
  signal pps_r         : std_logic;
  signal tm_link_up    : std_logic;
  signal tm_time_valid : std_logic;
  signal tm_tai        : std_logic_vector(39 downto 0);
  signal tm_cycles     : std_logic_vector(27 downto 0);

  -- WR fabric interface
  signal wrf_src_out : t_wrf_source_out;
  signal wrf_src_in  : t_wrf_source_in;
  signal wrf_snk_out : t_wrf_sink_out;
  signal wrf_snk_in  : t_wrf_sink_in;

  signal wrs_tx_data    : std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
  signal wrs_tx_valid   : std_logic;
  signal wrs_tx_valid_r : std_logic;
  signal wrs_tx_dreq    : std_logic;
  signal wrs_tx_last    : std_logic;
  signal wrs_tx_flush   : std_logic;
  signal wrs_rx_first   : std_logic;
  signal wrs_rx_last    : std_logic;
  signal wrs_rx_data    : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
  signal wrs_rx_valid   : std_logic;
  signal wrs_rx_valid_r : std_logic;
  signal wrs_rx_dreq    : std_logic;
  signal wrs_tx_cfg     : t_tx_streamer_cfg := c_tx_streamer_cfg_default;
  signal wrs_rx_cfg     : t_rx_streamer_cfg := c_rx_streamer_cfg_default;
  signal rf1_rst_rf     : std_logic;

  signal link_ok        : std_logic;

  signal wb_aux_out     : t_wishbone_master_out;
  signal wb_aux_in      : t_wishbone_master_in;
--  signal aux_rst_n      : std_logic;

  signal xadc_wb_in     : t_wishbone_master_in;
  signal xadc_wb_out    : t_wishbone_master_out;

  constant c_streamers_diag_id  : integer := 1;  -- id reserved for streamers
  constant c_streamers_diag_ver : integer := 2;  -- version that will be probably increased
  constant c_diag_id            : integer := f_pick_diag_val(g_fabric_iface,  c_streamers_diag_id,         g_diag_id);
  constant c_diag_ver           : integer := f_pick_diag_val(g_fabric_iface,  c_streamers_diag_ver,        g_diag_id);
  constant c_diag_ro_size       : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_OUT, g_diag_ro_size);
  constant c_diag_rw_size       : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_IN,  g_diag_rw_size);

  -- WR SNMP
  signal aux_diag_in  : t_generic_word_array(c_diag_ro_size-1 downto 0);
  signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);

  signal spi_flash_cs_n_sys      : std_logic;
  signal spi_flash_mosi_sys      : std_logic;
  signal spi_flash_sck_sys       : std_logic;
  signal spi_flash_cs_n_wrc      : std_logic;
  signal spi_flash_mosi_wrc      : std_logic;
  signal spi_flash_sck_wrc       : std_logic;
  signal spi_flash_sck           : std_logic;

  -- RFFrameTransceiver
  signal wrs_rx_RFFrameHeader     : t_RFFrameHeader;
  signal wrs_rx_RFmFramePayloads  : t_RFmFramePayload;

  signal wrs_rx_RFsFramePayloads  : t_RFsFramePayload;
  signal wrs_rx_Frame_valid_pX    : std_logic;
  signal wrs_rx_Frame_typeID      : std_logic_vector(c_RFtype_ID_size-1 downto 0);
  signal wrs_tx_ready             : std_logic;
  signal wrs_tx_TransmitFrame_p1  : std_logic := '0';
  signal wrs_tx_RFFrameHeader     : t_RFFrameHeader   := c_RFFrameHeader_zero;
  signal wrs_tx_RFmFramePayloads  : t_RFmFramePayload := c_RFmFramePayload_zero;
  signal txframe_payload          : t_RFmFramePayload;
  signal loc_rx_RFmFramePayloads  : t_RFmFramePayload;
  signal loc_rx_Frame_Valid_pX    : std_logic;
  signal rx_RFmFramePayloads      : t_RFmFramePayload;
  signal rx_Frame_Valid_pX        : std_logic;
  signal rx_reset_nco_pulse       : std_logic;
  signal nco_reset_dds_mask       : std_logic;
  signal nco_reset_rfnco_ch1_mask : std_logic;
  signal nco_reset_rfnco_ch2_mask : std_logic;
  signal nco_reset_rf1_trig1_mask : std_logic;
  signal nco_reset_rf2_trig1_mask : std_logic;
  signal nco_reset_dds       : std_logic;
  signal nco_reset_rfnco_ch1 : std_logic;
  signal nco_reset_rfnco_ch2 : std_logic;
  signal nco_reset_rf1_trig1 : std_logic;
  signal nco_reset_rf2_trig1 : std_logic;

  signal nco_reset_soft           : std_logic;

  signal rf1_nco_reset_cdelayed   : std_logic;
  signal rf2_nco_reset_cdelayed   : std_logic;

  signal loc_nco_ctrl_reset      : std_logic;
  signal loc_nco_h1_ftw          : std_logic_vector(c_FTW_size-1 downto 0);
  signal loc_nco_h1_prog         : std_logic_vector(c_FTW_size-1 downto 0);
  signal loc_nco_update_valid    : std_logic;
  signal loc_or_wrs_params_sel   : std_logic;
  signal loc_rx_reset_nco_pulse  : std_logic;

  signal wrs_frame_counter       : unsigned(15 downto 0);
  signal wrs_frame_counter_r     : unsigned(15 downto 0);
  signal wrs_frame_valid         : std_logic;
  signal wrs_frame_rxwrtimestamp   : std_logic_vector(31 downto 0);
  signal wrs_frame_rxwrtimestamp_r : std_logic_vector(31 downto 0);
  signal wrs_frame_txwrtimestamp   : std_logic_vector(31 downto 0);
  signal wrs_frame_txwrtimestamp_r : std_logic_vector(31 downto 0);
  signal wrs_frame_rftimestamp   : std_logic_vector(31 downto 0);
  signal wrs_frame_rftimestamp_r : std_logic_vector(31 downto 0);
  signal wrs_rx_reset_nco_pulse  : std_logic;

  signal rfframe_ts_update          : std_logic;
  signal rfframe_nco_reset_tai_r    : std_logic_vector(39 downto 0);
  signal rfframe_nco_reset_cycles_r : std_logic_vector(27 downto 0);
  signal rfframe_tai_r              : std_logic_vector(39 downto 0);
  signal rfframe_cycles_r           : std_logic_vector(27 downto 0);
  signal rfframe_nco_reset_tai_h    : std_logic_vector(39 downto 0);
  signal rfframe_nco_reset_cycles_h : std_logic_vector(27 downto 0);
  signal rfframe_tai_h              : std_logic_vector(39 downto 0);
  signal rfframe_cycles_h           : std_logic_vector(27 downto 0);  
  signal rfframe_nco_reset_tai      : std_logic_vector(39 downto 0);
  signal rfframe_nco_reset_cycles   : std_logic_vector(27 downto 0);
  signal rfframe_tai                : std_logic_vector(39 downto 0);
  signal rfframe_cycles             : std_logic_vector(27 downto 0);

  signal wb_rfframerxtx_in       : t_wishbone_master_in;
  signal wb_rfframerxtx_out      : t_wishbone_master_out;

  signal rfframe_fifo_din : std_logic_vector(48+16-1 downto 0);
  signal rfframe_fifo_dout : std_logic_vector(48+16-1 downto 0);
  signal rfframe_fifo_full : std_logic;
  signal rfframe_fifo_empty : std_logic;
  signal rfframe_fifo_we : std_logic;
  signal rfframe_fifo_rd : std_logic;
  signal rfframe_fifo_rst_n : std_logic;
  signal rfframe_fifo_out_payload  : t_RFmFramePayload := c_RFmFramePayload_zero;

  signal bmctrl_rfframe_ctrl_update : std_logic;
  signal bmctrl_rfframe_ctrl_en : std_logic;
  signal bmctrl_rfframe_ctrl_reset : std_logic;
  signal bmctrl_rfframe_status_fifo_rdy : std_logic;

  signal wb_rf1_rfnco_in         : t_wishbone_master_in;
  signal wb_rf1_rfnco_out        : t_wishbone_master_out;
  signal wb_rf2_rfnco_in         : t_wishbone_master_in;
  signal wb_rf2_rfnco_out        : t_wishbone_master_out;

  signal rf1_iqdac_igain_arm     : std_logic_vector(15 downto 0);
  signal rf1_iqdac_qgain_arm     : std_logic_vector(15 downto 0);
  signal rf2_iqdac_igain_arm     : std_logic_vector(15 downto 0);
  signal rf2_iqdac_qgain_arm     : std_logic_vector(15 downto 0);
  signal rf1_iqdac_phase_update  : std_logic;
  signal rf2_iqdac_phase_update  : std_logic;

  signal rf1_iqdac_igain         : std_logic_vector(15 downto 0);
  signal rf1_iqdac_qgain         : std_logic_vector(15 downto 0);
  signal rf2_iqdac_igain         : std_logic_vector(15 downto 0);
  signal rf2_iqdac_qgain         : std_logic_vector(15 downto 0);
  signal rf1_iqdac_igain_r       : std_logic_vector(15 downto 0);
  signal rf1_iqdac_qgain_r       : std_logic_vector(15 downto 0);
  signal rf2_iqdac_igain_r       : std_logic_vector(15 downto 0);
  signal rf2_iqdac_qgain_r       : std_logic_vector(15 downto 0);

  signal rf1_iqdac_ctrl          : std_logic_vector(15 downto 0);
  signal rf2_iqdac_ctrl          : std_logic_vector(15 downto 0);

  signal iqdac_ram_addr         : std_logic_vector(15 downto 0);
  signal iqdac_ram_data         : std_logic_vector(15 downto 0);
  signal iqdac_ram_write        : std_logic_vector(15 downto 0);
  signal iqdac_ram_play         : std_logic_vector(15 downto 0);

  -- Xilinx DDS test block
  signal rf1_dds_ftw_valid      : std_logic;
  signal rf1_dds_ftw            : std_logic_vector(47 downto 0);
  signal rf2_dds_ftw_valid      : std_logic;
  signal rf2_dds_ftw            : std_logic_vector(47 downto 0);

  signal icap_dat, icap_dat_rev : std_logic_vector(31 downto 0);
  signal icap_en_n : std_logic := '1';

  signal reconfigure : std_logic;
  signal reconfig_cnt : natural range 0 to 15;

  signal dds_ioupdate            : std_logic;
  signal dds_ioupdate_r          : std_logic;
  signal dds_ioupdate_fdelay     : std_logic_vector(3 downto 0);
  signal dds_ioupdate_odelay     : std_logic_vector(4 downto 0);

  signal softstart_sel     : std_logic_vector(3 downto 0);
  signal softstop_sel      : std_logic_vector(3 downto 0);
  signal rf1_t1_softstart  : std_logic;
  signal rf1_t2_softstart  : std_logic;
  signal rf2_t1_softstart  : std_logic;
  signal rf2_t2_softstart  : std_logic;
  signal rf1_t1_softstop   : std_logic;
  signal rf1_t2_softstop   : std_logic;
  signal rf2_t1_softstop   : std_logic;
  signal rf2_t2_softstop   : std_logic;

   -- ILA debug
  signal ila_clk                 : std_logic;
  signal ila_sigs                : std_logic_vector(127 downto 0);
  signal rfnco1_ila_dbg          : std_logic_vector(127  downto 0);
  signal rfnco2_ila_dbg          : std_logic_vector(127  downto 0);
  signal rf1_tu_ila_dbg          : std_logic_vector(31 downto 0);
  signal rf2_tu_ila_dbg          : std_logic_vector(31 downto 0);
  signal vme_dbg                 : std_logic_vector(47 downto 0);
  signal regs_ila                : std_logic_vector(7   downto 0);

  attribute keep_hierarchy of wr2rf_vme_p0_i          : label is "yes";
  attribute keep_hierarchy of inst_vme_core           : label is "yes";
  attribute keep_hierarchy of inst_RFFrameTransceiver : label is "yes";
  attribute keep_hierarchy of inst_xwr_streamers      : label is "yes";

  attribute IOB  : string;
  attribute keep : string;
  attribute IOB  of pps_r : signal is "true";
  attribute keep of pps_r : signal is "true";

begin

    --  Poweron reset.
    process (clk_sys_62m5) is
    begin
        if rising_edge(clk_sys_62m5) then
            if poweron_counter /= 0 then
                poweron_counter <= poweron_counter - 1;
                rst_sys_n_r     <= '0';
                rst_sys_r       <= '1';
            else
                rst_sys_n_r     <= '1';
                rst_sys_r       <= '0';
            end if;
        end if;
    end process;

    rst_sys_n  <= rst_sys_n_r;
    rst_sys    <= rst_sys_r;

    ----------------------------------------------------------------------------
    -- Clock distribution/PLL and reset
    ----------------------------------------------------------------------------

    inst_IBUFDS_dmtd : IBUFGDS
        port map (
            O  => clk_dmtd_62m5,       -- Buffer output
            I  => clk_dmtd_62m5_p_i,   -- Diff_p buffer input
            IB => clk_dmtd_62m5_n_i ); -- Diff_n buffer input

    inst_IBUFDS_sys : IBUFGDS
        port map (
            O  => clk_sys_62m5_in,
            I  => clk_sys_62m5_p_i,
            IB => clk_sys_62m5_n_i );

    inst_BUFGMUX_CTRL : BUFGMUX_CTRL
        port map (
            O  => clk_sys_62m5,        -- 1-bit output: Clock output
            I0 => clk_dmtd_62m5,       -- 1-bit input: Clock input (S=0)
            I1 => clk62m5,             -- 1-bit input: Clock input (S=1)
            S  => clk_sys_select );    -- 1-bit input: Clock select

    inst_IBUFDS_clk_ext_10m : IBUFGDS
        port map (
            O  => clk_ext_10m_in,      -- Buffer output
            I  => clk_ext_10m_p_i,     -- Diff_p buffer input
            IB => clk_ext_10m_n_i );   -- Diff_n buffer input

    inst_BUFG_clk_ext_10m : BUFG
        port map (
            O  => clk_ext_10m,
            I  => clk_ext_10m_in );

    wr2rf_sysclks_i : entity work.wr2rf_sysclks
        port map (
            clk_sys_i       => clk_sys_62m5_in,
            reset_i         => clk_sys_reset,

            mmcm_locked_o       => mmcm_locked,
            mmcm_shift_incdec_i => mmcm_shift_incdec,
            mmcm_shift_en_i     => mmcm_shift_en,
            mmcm_shift_busy_o   => mmcm_shift_busy,

            clk62m5_o       => clk62m5,
            rst_clk62m5_n_o => rst_clk62m5_n,
            rst_clk62m5_o   => rst_clk62m5,

            clk125m_o       => clk125m,
            rst_clk125m_n_o => rst_clk125m_n,
            rst_clk125m_o   => rst_clk125m,

            clk250m_o       => clk250m,
            rst_clk250m_n_o => rst_clk250m_n,
            rst_clk250m_o   => rst_clk250m,

            clk500m_o       => clk500m,
            rst_clk500m_n_o => rst_clk500m_n,
            rst_clk500m_o   => rst_clk500m,

            clk200m_o       => clk200m,
            rst_clk200m_n_o => rst_clk200m_n,
            rst_clk200m_o   => rst_clk200m );

    wr2rf_gen_10mhz_i : entity work.wr2rf_gen_10mhz
       port map (
          clk125m_i      => clk125m,
          rst_clk125m_i  => rst_clk125m,
          clk500m_i      => clk500m,
          rst_clk500m_i  => rst_clk500m,
          pps_i          => pps_p,
          pps_valid_i    => tm_time_valid,
          clk10m_o       => clk_ext_10m_o );

    ------------------------------------------------------------------------------
    -- Dedicated clock for GTP
    ------------------------------------------------------------------------------

    inst_gtx_clk0_buf : IBUFDS_GTE2
        generic map(
            CLKCM_CFG    => true,
            CLKRCV_TRST  => true,
            CLKSWING_CFG => "11" )
        port map(
            O     => clk_gtx_125m,
            ODIV2 => open,
            CEB   => '0',
            I     => clk_125m_gtx_p_i,
            IB    => clk_125m_gtx_n_i );

    inst_wr2rf_extclk : entity work.wr2rf_extclk
       port map (
          clk_ext_10m_i     => clk_ext_10m_in,
          clk_ext_stopped_o => clk_ext_stopped,
          clk_ext_reset_i   => ext_10m_dir, -- 1 is output for pps and 10 MHz clock
          clk_ext_locked_o  => clk_ext_mul_locked,
          clk_ext_125m_o    => clk_ext_mul );

    phy16_in.ref_clk        <= clk_sys_62m5;
    phy16_in.sfp_tx_fault   <= sfp1_tx_fault_i;
    phy16_in.sfp_los        <= sfp1_los_i;
    sfp1_tx_disable_o <= phy16_out.sfp_tx_disable;

    inst_GTX_Link0 : entity work.wr_gtx_phy_kintex7_lp
        generic map(
            g_simulation => g_simulation)
      port map(
            clk_sys_i => clk_sys_62m5,
            rst_sys_n_i => wrcore_reset_n,
            clk_gtx_i          => clk_gtx_125m,
            clk_dmtd_i         => clk_dmtd_62m5,
            clk_ref_i          => clk_sys_62m5,
            tx_clk_o           => open,
            tx_locked_o        => open,
            tx_data_i          => phy16_out.tx_data,
            tx_k_i             => phy16_out.tx_k,
            tx_disparity_o     => phy16_in.tx_disparity,
            tx_enc_err_o       => phy16_in.tx_enc_err,
            rx_rbclk_o         => phy16_in.rx_clk,
            rx_rbclk_sampled_o => phy16_in.rx_sampled_clk,
            rx_data_o          => phy16_in.rx_data,
            rx_k_o             => phy16_in.rx_k,
            rx_enc_err_o       => phy16_in.rx_enc_err,
            rx_bitslide_o      => phy16_in.rx_bitslide,
            rdy_o              => phy16_in.rdy,
            rst_i              => phy16_out.rst,
            loopen_i           => phy16_out.loopen,
            loopen_vec_i       => phy16_out.loopen_vec,
            pad_txn_o          => sfp1_tx_n_o,
            pad_txp_o          => sfp1_tx_p_o,
            pad_rxn_i          => sfp1_rx_n_i,
            pad_rxp_i          => sfp1_rx_p_i,
            fmon_clk_o         => open,
            mdio_slave_i       => phy_mdio_out,
            mdio_slave_o       => phy_mdio_in);

    inst_WR_CORE : entity work.xwr_core
        generic map(
            g_simulation                     => g_simulation,
            g_with_external_clock_input      => true,
            --
            g_board_name                     => "WRRF",
            --g_ram_address_space_size_kb    => 256,
            g_phys_uart                      => true,
            g_virtual_uart                   => true,
            g_aux_clks                       => 0,
            g_ep_rxbuf_size                  => 1024,
            g_tx_runt_padding                => true,
            g_records_for_phy                => true,
            g_pcs_16bit                      => true,
            g_dpram_initf                    => g_dpram_initf,
            g_dpram_size                     => (131072+65536)/4,
            g_interface_mode                 => PIPELINED,
            g_address_granularity            => BYTE,
            g_aux_sdb                        => c_wrc_periph3_sdb,
            g_softpll_enable_debugger        => true,
            g_softpll_use_sampled_ref_clocks => true,
            g_vuart_fifo_size                => 1024,
            g_diag_id                        => c_diag_id,
            g_diag_ver                       => c_diag_ver,
            g_diag_ro_size                   => c_diag_ro_size,
            g_diag_rw_size                   => c_diag_rw_size )
        port map(
            clk_sys_i              => clk_sys_62m5,
            clk_dmtd_i             => clk_dmtd_62m5,
            clk_ref_i              => clk_sys_62m5,  --clk_125m_ref,
            clk_ext_i              => clk_ext_10m,
            clk_ext_mul_i          => clk_ext_mul,
            clk_ext_stopped_i      => clk_ext_stopped,
            clk_ext_mul_locked_i   => clk_ext_mul_locked,
            clk_ext_rst_o          => clk_ext_rst,
            pps_ext_i              => pps_i,
            rst_n_i                => wrcore_reset_n,
            dac_hpll_load_p1_o     => dac_hpll_load_p1_o,
            dac_hpll_data_o        => dac_hpll_data_o,
            dac_dpll_load_p1_o     => dac_dpll_load_p1_o,
            dac_dpll_data_o        => dac_dpll_data_o,
            phy16_i                => phy16_in,
            phy16_o                => phy16_out,
            phy_mdio_master_o      => phy_mdio_out,
            phy_mdio_master_i      => phy_mdio_in,
            led_act_o              => sfp1_led_active_o,
            led_link_o             => sfp1_led_link_o,
            scl_o                  => wr1_scl_out,
            scl_i                  => wr1_scl_in,
            sda_o                  => wr1_sda_out,
            sda_i                  => wr1_sda_in,
            sfp_scl_o              => sfp1_scl_out,
            sfp_scl_i              => sfp1_scl_in,
            sfp_sda_o              => sfp1_sda_out,
            sfp_sda_i              => sfp1_sda_in,
            sfp_det_i              => sfp1_detect_i,
            spi_sclk_o             => spi_flash_sck_wrc,
            spi_ncs_o              => spi_flash_cs_n_wrc,
            spi_mosi_o             => spi_flash_mosi_wrc,
            spi_miso_i             => spi_flash_miso_i,
            uart_rxd_i             => '1',
            uart_txd_o             => open,
            owr_pwren_o            => open,
            owr_en_o               => owr_en,
            owr_i                  => owr_i,

            slave_i                => wb_wrc_in,
            slave_o                => wb_wrc_out,
            aux_master_o           => wb_aux_out,
            aux_master_i           => wb_aux_in,

            wrf_src_o              => wrf_src_out,
            wrf_src_i              => wrf_src_in,
            wrf_snk_o              => wrf_snk_out,
            wrf_snk_i              => wrf_snk_in,
            timestamps_o           => open,
            timestamps_ack_i       => '1',
            fc_tx_pause_req_i      => '0',
            fc_tx_pause_delay_i    => x"0000",
            fc_tx_pause_ready_o    => open,
            tm_link_up_o           => tm_link_up,
            tm_dac_value_o         => open,
            tm_dac_wr_o            => open,
            tm_clk_aux_lock_en_i   => (others => '0'),
            tm_clk_aux_locked_o    => open,
            tm_time_valid_o        => tm_time_valid,
            tm_tai_o               => tm_tai,
            tm_cycles_o            => tm_cycles,
            pps_p_o                => pps_p,
            pps_led_o              => open,
            pps_csync_o            => pps_csync,
            rst_aux_n_o            => open,
            aux_diag_i             => aux_diag_in,
            aux_diag_o             => aux_diag_out,

            link_ok_o              => link_ok );

    inst_xwr_streamers : entity work.xwr_streamers
       generic map (
          g_streamers_op_mode    => g_streamers_op_mode,
          g_clk_ref_rate         => 62500000,
          g_tx_streamer_params   => g_tx_streamer_params,
          g_rx_streamer_params   => g_rx_streamer_params,
          g_simulation           => g_simulation )
       port map (
          clk_sys_i              => clk_sys_62m5,
          clk_ref_i              => clk_sys_62m5,

          rst_n_i                => rst_sys_n,
          src_i                  => wrf_snk_out,
          src_o                  => wrf_snk_in,
          snk_i                  => wrf_src_out,
          snk_o                  => wrf_src_in,

          -- REF clock domain
          tx_data_i              => wrs_tx_data,
          tx_valid_i             => wrs_tx_valid,
          tx_dreq_o              => wrs_tx_dreq,
          tx_last_p1_i           => wrs_tx_last,
          tx_flush_p1_i          => wrs_tx_flush,
          rx_first_p1_o          => wrs_rx_first,
          rx_last_p1_o           => wrs_rx_last,
          rx_data_o              => wrs_rx_data,
          rx_valid_o             => wrs_rx_valid,
          rx_dreq_i              => wrs_rx_dreq,

          tm_time_valid_i        => tm_time_valid,
          tm_tai_i               => tm_tai,
          tm_cycles_i            => tm_cycles,
          link_ok_i              => link_ok,
          wb_slave_i             => wb_aux_out,
          wb_slave_o             => wb_aux_in,
          snmp_array_o           => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
          snmp_array_i           => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
          tx_streamer_cfg_i      => wrs_tx_cfg,
          rx_streamer_cfg_i      => wrs_rx_cfg );

    inst_RFFrameTransceiver : entity work.RFFrameTransceiver
        port map(
            clk_i                  => clk_sys_62m5,
            rst_n_i                => rst_sys_n,

            tx_data_o              => wrs_tx_data,
            tx_valid_o             => wrs_tx_valid,
            tx_dreq_i              => wrs_tx_dreq,
            tx_last_p1_o           => wrs_tx_last,
            tx_flush_p1_o          => wrs_tx_flush,
            rx_data_i              => wrs_rx_data,
            rx_valid_i             => wrs_rx_valid,
            rx_first_p1_i          => wrs_rx_first,
            rx_dreq_o              => wrs_rx_dreq,
            rx_last_p1_i           => wrs_rx_last,

            rx_RFFrameHeader_o     => wrs_rx_RFFrameHeader,
            rx_RFmFramePayloads_o  => wrs_rx_RFmFramePayloads,
            rx_RFsFramePayloads_o  => wrs_rx_RFsFramePayloads,
            rx_Frame_valid_pX_o    => wrs_rx_Frame_valid_pX,
            rx_Frame_typeID_o      => wrs_rx_Frame_typeID,

            ready_o                => wrs_tx_ready,
            tx_TransmitFrame_p1_i  => wrs_tx_TransmitFrame_p1,
            tx_RFFrameHeader_i     => wrs_tx_RFFrameHeader,
            tx_RFmFramePayloads_i  => wrs_tx_RFmFramePayloads,
            tx_RFsFramePayloads_i  => open,

            wb_slave_i             => wb_rfframerxtx_out,
            wb_slave_o             => wb_rfframerxtx_in );

    wrs_tx_RFFrameHeader <= c_RFFrameHeader_dummy;

    --  Fifo for playing a ftw sequence.
    inst_rfframe_fifo: entity work.generic_sync_fifo
      generic map (
        g_data_width => 48 + 16,
        g_size => 16,
        g_show_ahead => True,
        g_show_ahead_legacy_mode => False,
        g_with_empty => True,
        g_with_full => True,
        g_with_almost_empty => False,
        g_with_almost_full => False,
        g_with_count => False
      )
      port map (
        rst_n_i => rfframe_fifo_rst_n,
        clk_i => clk_sys_62m5,
        d_i => rfframe_fifo_din,
        we_i => rfframe_fifo_we,
        q_o => rfframe_fifo_dout,
        rd_i => rfframe_fifo_rd,
        empty_o => rfframe_fifo_empty,
        full_o =>  rfframe_fifo_full,
        almost_empty_o => open,
        almost_full_o => open,
        count_o => open
      );

    rfframe_fifo_rst_n <= rst_sys_n and not bmctrl_rfframe_ctrl_reset;
    rfframe_fifo_din(63 downto 48) <= txframe_payload.control;
    rfframe_fifo_din(48-1 downto 0) <= txframe_payload.FTW_H1_main;
    rfframe_fifo_we <= bmctrl_rfframe_ctrl_update and not rfframe_fifo_full;
    rfframe_fifo_rd <= not rfframe_fifo_empty and bmctrl_rfframe_ctrl_en and rf1_frev_main;
    bmctrl_rfframe_status_fifo_rdy <= not rfframe_fifo_full;

    rfframe_fifo_out_payload.FTW_H1_main <= rfframe_fifo_dout(47 downto 0);
    rfframe_fifo_out_payload.control <= rfframe_fifo_dout(63 downto 48);
    wrs_tx_TransmitFrame_p1  <= rfframe_fifo_rd;
    wrs_tx_RFmFramePayloads <= rfframe_fifo_out_payload when bmctrl_rfframe_ctrl_en = '1' else txframe_payload;

    process (clk_sys_62m5) is
    begin
       if rising_edge (clk_sys_62m5) then
          if rst_sys_n = '0' then
             wrs_frame_counter_r        <= (others => '0');
             wrs_frame_rxwrtimestamp_r  <= (others => '0');
             wrs_frame_txwrtimestamp_r  <= (others => '0');
             wrs_frame_rftimestamp_r    <= (others => '0');
             rfframe_nco_reset_tai_r    <= (others => '0');
             rfframe_nco_reset_cycles_r <= (others => '0');
             rfframe_tai_r              <= (others => '0');
             rfframe_cycles_r           <= (others => '0');
             rfframe_nco_reset_tai_h    <= (others => '0');
             rfframe_nco_reset_cycles_h <= (others => '0');
             rfframe_tai_h              <= (others => '0');
             rfframe_cycles_h           <= (others => '0');             
          else
             wrs_frame_counter_r        <= wrs_frame_counter;
             wrs_frame_rxwrtimestamp_r  <= wrs_frame_rxwrtimestamp;
             wrs_frame_txwrtimestamp_r  <= wrs_frame_txwrtimestamp;
             wrs_frame_rftimestamp_r    <= wrs_frame_rftimestamp;
             rfframe_nco_reset_tai_r    <= rfframe_nco_reset_tai;
             rfframe_nco_reset_cycles_r <= rfframe_nco_reset_cycles;
             rfframe_tai_r              <= rfframe_tai;
             rfframe_cycles_r           <= rfframe_cycles;
             if rfframe_ts_update = '1' then
                rfframe_nco_reset_tai_h    <= rfframe_nco_reset_tai_r;
                rfframe_nco_reset_cycles_h <= rfframe_nco_reset_cycles_r;
                rfframe_tai_h              <= rfframe_tai_r;
                rfframe_cycles_h           <= rfframe_cycles_r;             
             end if;
          end if;
       end if;
    end process;

    process (clk_sys_62m5) is
    begin
       if rising_edge (clk_sys_62m5) then
          wrs_rx_valid_r <= wrs_rx_valid;
          wrs_tx_valid_r <= wrs_tx_valid;
       end if;
    end process;

    -- TAKE out loc values...
    wrs_frame_valid          <= '1' when wrs_rx_Frame_valid_pX                = '1' and wrs_rx_Frame_typeID = c_ID_RFmFrame else '0';
    wrs_rx_reset_nco_pulse   <= '1' when wrs_rx_RFmFramePayloads.control(0)   = '1' and wrs_frame_valid     = '1'           else '0';
    wrs_frame_counter        <= wrs_frame_counter_r + 1 when wrs_frame_valid  = '1' else wrs_frame_counter_r;
    wrs_frame_txwrtimestamp  <= tm_tai(3 downto 0) & tm_cycles when wrs_tx_valid_r    = '1' else wrs_frame_txwrtimestamp_r;
    wrs_frame_rxwrtimestamp  <= tm_tai(3 downto 0) & tm_cycles when wrs_rx_valid_r    = '1' else wrs_frame_rxwrtimestamp_r;
    wrs_frame_rftimestamp    <= tm_tai(3 downto 0) & tm_cycles when wrs_frame_valid   = '1' else wrs_frame_rftimestamp_r;

    rfframe_nco_reset_tai    <= tm_tai    when wrs_rx_reset_nco_pulse = '1' else rfframe_nco_reset_tai_r;
    rfframe_nco_reset_cycles <= tm_cycles when wrs_rx_reset_nco_pulse = '1' else rfframe_nco_reset_cycles_r;
    rfframe_tai              <= tm_tai    when wrs_frame_valid        = '1' else rfframe_tai_r;
    rfframe_cycles           <= tm_cycles when wrs_frame_valid        = '1' else rfframe_cycles_r;

    loc_rx_RFmFramePayloads.control(0)  <= rfframe_fifo_out_payload.control(0) when bmctrl_rfframe_ctrl_en = '1' else loc_nco_ctrl_reset;
    loc_rx_RFmFramePayloads.FTW_H1_main <= rfframe_fifo_out_payload.FTW_H1_main when bmctrl_rfframe_ctrl_en = '1' else loc_nco_h1_ftw;
    loc_rx_RFmFramePayloads.FTW_H1_prog <= loc_nco_h1_prog;
    loc_rx_Frame_valid_pX               <= rfframe_fifo_rd when bmctrl_rfframe_ctrl_en = '1' else loc_nco_update_valid;
    loc_rx_reset_nco_pulse              <= rfframe_fifo_dout(48) and rfframe_fifo_rd when bmctrl_rfframe_ctrl_en = '1' else loc_nco_update_valid;

    rx_RFmFramePayloads <= loc_rx_RFmFramePayloads when loc_or_wrs_params_sel = '1' else wrs_rx_RFmFramePayloads;
    rx_Frame_valid_pX   <= loc_rx_Frame_valid_pX   when loc_or_wrs_params_sel = '1' else wrs_rx_Frame_valid_pX;
    rx_reset_nco_pulse  <= '1'                     when nco_reset_soft        = '1' else
                           loc_rx_reset_nco_pulse  when loc_or_wrs_params_sel = '1' else wrs_rx_reset_nco_pulse;

    nco_reset_dds       <= rx_reset_nco_pulse and (not nco_reset_dds_mask);
    nco_reset_rfnco_ch1 <= rx_reset_nco_pulse and (not nco_reset_rfnco_ch1_mask);--unsupported for now
    nco_reset_rfnco_ch2 <= rx_reset_nco_pulse and (not nco_reset_rfnco_ch2_mask);--unsupported for now
    nco_reset_rf1_trig1 <= rx_reset_nco_pulse and (not nco_reset_rf1_trig1_mask);
    nco_reset_rf2_trig1 <= rx_reset_nco_pulse and (not nco_reset_rf2_trig1_mask);

    inst_wr2rf_dds : entity work.wr2rf_dds
       port map (
          clk62m5_i         => clk_sys_62m5,
          clk125m_i         => clk125m,
          clk500m_i         => clk500m,
          rst_clk62m5_i     => rst_sys,
          rst_clk125m_i     => rst_clk125m,
          ioupdate_fdelay_i => dds_ioupdate_fdelay,
          ioupdate_odelay_i => dds_ioupdate_odelay,
          dds_ioupdate_i    => dds_ioupdate_r,
          dds_ioupdate_o    => dds_ioupdate_o,
          dds_sync_p_o      => dds_sync_p_o,
          dds_sync_n_o      => dds_sync_n_o );

    rf1_iqdac_igain <= rf1_iqdac_igain_arm when rf1_iqdac_phase_update = '1' else rf1_iqdac_igain_r;
    rf1_iqdac_qgain <= rf1_iqdac_qgain_arm when rf1_iqdac_phase_update = '1' else rf1_iqdac_qgain_r;
    rf2_iqdac_igain <= rf2_iqdac_igain_arm when rf2_iqdac_phase_update = '1' else rf2_iqdac_igain_r;
    rf2_iqdac_qgain <= rf2_iqdac_qgain_arm when rf2_iqdac_phase_update = '1' else rf2_iqdac_qgain_r;

    process (clk_sys_62m5) is
    begin
       if rising_edge(clk_sys_62m5) then
          if (rst_sys = '1') then
             dds_ioupdate_r    <= '0';
             rf1_iqdac_igain_r <= (others => '0');
             rf1_iqdac_qgain_r <= (others => '0');
             rf2_iqdac_igain_r <= (others => '0');
             rf2_iqdac_qgain_r <= (others => '0');
          else
             dds_ioupdate_r    <= dds_ioupdate or nco_reset_dds;
             rf1_iqdac_igain_r <= rf1_iqdac_igain;
             rf1_iqdac_qgain_r <= rf1_iqdac_qgain;
             rf2_iqdac_igain_r <= rf2_iqdac_igain;
             rf2_iqdac_qgain_r <= rf2_iqdac_qgain;
          end if;
       end if;
    end process;

    inst_wr2rf_rfchan_wrap : entity work.wr2rf_rfchan_wrap
        port map (
            clk125m_i             => clk125m,
            clk250m_i             => clk250m,
            rst_clk125m_i         => rst_clk125m,
            rst_clk125m_n_i       => rst_clk125m_n,
            rst_clk250m_i         => rst_clk250m,
            rst_clk250m_n_i       => rst_clk250m_n,

            rf1_dds_ftw_valid_i   => rf1_dds_ftw_valid,
            rf1_dds_ftw_i         => rf1_dds_ftw,
            rf2_dds_ftw_valid_i   => rf2_dds_ftw_valid,
            rf2_dds_ftw_i         => rf2_dds_ftw,

            rx_RFmFramePayloads_i => rx_RFmFramePayloads,
            rx_Frame_valid_pX_i   => rx_Frame_valid_pX,

            wb_rf1_rfnco_slave_i  => wb_rf1_rfnco_out,
            wb_rf1_rfnco_slave_o  => wb_rf1_rfnco_in,
            wb_rf2_rfnco_slave_i  => wb_rf2_rfnco_out,
            wb_rf2_rfnco_slave_o  => wb_rf2_rfnco_in,

            rf1_iqdac_igain_i     => rf1_iqdac_igain,
            rf1_iqdac_qgain_i     => rf1_iqdac_qgain,
            rf1_iqdac_ctrl_i      => rf1_iqdac_ctrl,

            rf2_iqdac_igain_i     => rf2_iqdac_igain,
            rf2_iqdac_qgain_i     => rf2_iqdac_qgain,
            rf2_iqdac_ctrl_i      => rf2_iqdac_ctrl,

            rf1_frev_o            => rf1_frev,
            rf1_frev_main_o       => rf1_frev_main,
            rf2_frev_o            => rf2_frev,
            rf2_frev_main_o       => rf2_frev_main,

            rf1_iqdac_data_p_o    => rf1_iqdac_data_p_o,
            rf1_iqdac_data_n_o    => rf1_iqdac_data_n_o,
            rf1_iqdac_dci_p_o     => rf1_iqdac_dci_p_o,
            rf1_iqdac_dci_n_o     => rf1_iqdac_dci_n_o,

            rf2_iqdac_data_p_o    => rf2_iqdac_data_p_o,
            rf2_iqdac_data_n_o    => rf2_iqdac_data_n_o,
            rf2_iqdac_dci_p_o     => rf2_iqdac_dci_p_o,
            rf2_iqdac_dci_n_o     => rf2_iqdac_dci_n_o,

            rf1_ila_dbg_o         => rfnco1_ila_dbg,
            rf2_ila_dbg_o         => rfnco2_ila_dbg );

    inst_ocxo_DAC : entity work.gc_serial_dac
        generic map (
            g_num_data_bits  => 16,
            g_num_extra_bits => 8,
            g_num_cs_select  => 1,
            g_sclk_polarity  => 0)
        port map (
            clk_i         => clk_sys_62m5,
            rst_n_i       => rst_sys_n,
            value_i       => dac_dpll_data_o,
            cs_sel_i      => "1",
            load_i        => dac_dpll_load_p1_o,
            sclk_divsel_i => "010",
            dac_cs_n_o(0) => wr_dac_ocxo_cs_n_o,
            dac_sclk_o    => wr_dac_ocxo_sclk_o,
            dac_sdata_o   => wr_dac_ocxo_din_o);

    inst_dmtd_DAC : entity work.gc_serial_dac
        generic map (
            g_num_data_bits  => 16,
            g_num_extra_bits => 8,
            g_num_cs_select  => 1,
            g_sclk_polarity  => 0)
        port map (
            clk_i         => clk_sys_62m5,
            rst_n_i       => rst_sys_n,
            value_i       => dac_hpll_data_o,
            cs_sel_i      => "1",
            load_i        => dac_hpll_load_p1_o,
            sclk_divsel_i => "010",
            dac_cs_n_o(0) => wr_dac_dmtd_cs_n_o,
            dac_sclk_o    => wr_dac_dmtd_sclk_o,
            dac_sdata_o   => wr_dac_dmtd_din_o);

    sfp1_scl_b   <= '0' when sfp1_scl_out = '0' else 'Z';
    sfp1_sda_b   <= '0' when sfp1_sda_out = '0' else 'Z';
    sfp1_scl_in  <= sfp1_scl_b;
    sfp1_sda_in  <= sfp1_sda_b;

    sfp1_rate_select_o <= '1';

    -- tie of sfp2 usused
    sfp2_tx_disable_o  <= '0';
    sfp2_led_active_o  <= '0';
    sfp2_led_link_o    <= '0';
    sfp2_rate_select_o <= '1';
    sfp2_scl_b         <= '0';
    sfp2_sda_b         <= '0';

    --  One wire: use port 0 ?
    wr_onewire_b <= '0' when (owr_en(0) = '1') else 'Z';
    owr_i(0)     <= wr_onewire_b;
    owr_i(1)     <= '1';

    wr_eeprom1_scl_b   <= '0' when wr1_scl_out = '0' else 'Z';
    wr_eeprom1_sda_b   <= '0' when wr1_sda_out = '0' else 'Z';
    wr1_scl_in  <= wr_eeprom1_scl_b;
    wr1_sda_in  <= wr_eeprom1_sda_b;

    wr_eeprom2_scl_b   <= 'Z';
    wr_eeprom2_sda_b   <= 'Z';

    process(clk_sys_62m5) is
    begin
        if rising_edge(clk_sys_62m5) then
            pps_r <= pps_p;
        end if;
    end process;
    pps_o <= pps_r;

    -----------------------------------------------------------------------------
    -- VME64x Core and buffers
    -----------------------------------------------------------------------------

    --  BERR and IRQ vme signals are inverted by the drivers. See schematics.
    vme_berr_o <= not vme_berr_n_o;
    vme_irq_o <= not vme_irq_n_o;

    inst_vme_core : entity work.xvme64x_core
        generic map (
            g_CLOCK_PERIOD    => 16,
            g_VME32           => False,
            g_ENABLE_CR_CSR   => False,
            g_USER_CSR_EXT    => False,
            g_WB_GRANULARITY  => BYTE,

            g_MANUFACTURER_ID => c_CERN_ID,
            g_BOARD_ID        => c_SVEC_ID,
            g_REVISION_ID     => c_SVEC_REVISION_ID,
            g_PROGRAM_ID      => c_SVEC_PROGRAM_ID,
            g_DECODER => (0      => (adem => x"fff80000", amcap => x"ee000000_00000000", dawpr => x"83"),
                          others => (adem => x"00000000", amcap => x"00000000_00000000", dawpr => x"83")) )
        port map (
            clk_i           => clk_sys_62m5,
            rst_n_i         => rst_sys_n,
            vme_i.as_n      => vme_as_n_i,
            vme_i.rst_n     => vme_sysreset_n_i,
            vme_i.write_n   => vme_write_n_i,
            vme_i.am        => vme_am_i,
            vme_i.ds_n      => vme_ds_n_i,
            vme_i.ga        => vme_ga,
            vme_i.lword_n   => vme_lword_n_b,
            vme_i.addr (23 downto 1)      => vme_addr_b (23 downto 1),
            vme_i.addr (31 downto 24)     => x"00",
            vme_i.data (15 downto 0)      => vme_data_b (15 downto 0),
            vme_i.data (31 downto 16) => x"0000",
            vme_i.iack_n    => vme_iack_n_i,
            vme_i.iackin_n  => vme_iackin_n_i,
            vme_o.berr_n    => vme_berr_n_o,
            vme_o.dtack_n   => vme_dtack_n_o,
            vme_o.retry_n   => vme_retry_n_o,
            vme_o.retry_oe  => vme_retry_oe_o,
            vme_o.lword_n   => vme_lword_n_b_out,
            vme_o.data (15 downto 0)      => vme_data_b_out,
            vme_o.data (31 downto 16)     => vme_data_b_out1,
            vme_o.addr      => vme_addr_b_out,
            vme_o.irq_n     => vme_irq_n_o,
            vme_o.iackout_n => vme_iackout_n_o,
            vme_o.dtack_oe  => vme_dtack_oe_o,
            vme_o.data_dir  => vme_data_dir_int,
            vme_o.data_oe_n => vme_data_oe_n_o,
            vme_o.addr_dir  => vme_addr_dir_o,
            vme_o.addr_oe_n => vme_addr_oe_n_o,
            wb_i   => wb_vme_in,
            wb_o   => wb_vme_out);

    vme_nogap <= not (vme_noga_n_i(0) xor vme_noga_n_i(1) xor vme_noga_n_i(2)
                      xor vme_noga_n_i(3) xor vme_noga_n_i(4));
    --  Use vme_ga_n_i if not unconnected (there are pull-up).
    --  Despite the name, the vme64x core want negated logic.
    vme_ga <= vme_gap_i & vme_ga_n_i when vme_ga_n_i /= (4 downto 0 => '1')
        else vme_nogap & vme_noga_n_i;

    -- VME tri-state buffers
    vme_data_b (15 downto 0)  <= vme_data_b_out    when vme_data_dir_int = '1'
                                 else (others => 'Z');

    vme_data_dir_o <= vme_data_dir_int;

    vme_dbg(0)            <= vme_as_n_i;
    vme_dbg(1)            <= vme_write_n_i;
    vme_dbg(7 downto 2)   <= vme_am_i;
    vme_dbg(23 downto 8)  <= vme_data_b (15 downto 0);
    vme_dbg(24)           <= '0';
    vme_dbg(47 downto 25) <= vme_addr_b (23 downto 1);

    inst_rf1_trigger : entity work.wr2rf_rftrigger
        port map (
            clk_sys_i         => clk_sys_62m5,
            rst_sys_n_i       => rst_sys_n,
            rst_sys_i         => rst_sys,
            clk125m_i         => clk125m,
            rst_clk125m_i     => rst_clk125m,
            clk500m_i         => clk500m,
            clk_refclk_200m_i => clk200m,
            iodelay_reset_i   => iodelay_reset,
            wb_i              => wb_rf1_vtus_out,
            wb_o              => wb_rf1_vtus_in,
            tm_tai_i          => tm_tai,
            tm_cycles_i       => tm_cycles,            

            rf_t1_sync_i            => nco_reset_rf1_trig1,
            rf_t1_sync_cdelay_i     => rf1_t1_sync_cdelay,
            rf_t1_sync_fdelay_i     => rf1_t1_sync_fdelay,
            rf_t1_sync_odelay_i     => rf1_t1_sync_odelay,
            rf_rst_cdelay_offset_i  => rf1_rst_cdelay_offset,
            rf_nco_reset_cdelayed_o => rf1_nco_reset_cdelayed,
            rf_rst_o                => rf1_rst_rf,
            rf_t1_sync_p_o          => rf1_sync_p_o,
            rf_t1_sync_n_o          => rf1_sync_n_o,

            rf_t1_clk_p_i    => rf1_t1_clk_p_i,
            rf_t1_clk_n_i    => rf1_t1_clk_n_i,
            rf_t1_p_o        => rf1_t1_p_o,
            rf_t1_n_o        => rf1_t1_n_o,
            rf_t1_rst_i      => rf1_t1_rst,
            rf_t1_rst_p_o    => rf1_t1_rst_p_o,
            rf_t1_rst_n_o    => rf1_t1_rst_n_o,
            rf_t1_start_i    => rf1_t1_start,
            rf_t1_stop_i     => rf1_t1_stop,

            rf_t2_clk_p_i    => rf1_t2_clk_p_i,
            rf_t2_clk_n_i    => rf1_t2_clk_n_i,
            rf_t2_p_o        => rf1_t2_p_o,
            rf_t2_n_o        => rf1_t2_n_o,
            rf_t2_rst_i      => rf1_t2_rst,
            rf_t2_rst_p_o    => rf1_t2_rst_p_o,
            rf_t2_rst_n_o    => rf1_t2_rst_n_o,
            rf_t2_start_i    => rf1_t2_start,
            rf_t2_stop_i     => rf1_t2_stop,

            rf_t1_softstart_o => rf1_t1_softstart,
            rf_t2_softstart_o => rf1_t2_softstart,
            rf_t1_softstop_o  => rf1_t1_softstop,
            rf_t2_softstop_o  => rf1_t2_softstop,

            rf_t1_vtu_start_p_o => rf1_t1_vtu_start_p,
            rf_t2_vtu_start_p_o => rf1_t2_vtu_start_p,

            rf_clk_bufg_o    => rf1_clk_bufg,

            rf_ila_dbg_o     => rf1_tu_ila_dbg );

    inst_rf2_trigger : entity work.wr2rf_rftrigger
        port map (
            clk_sys_i         => clk_sys_62m5,
            rst_sys_n_i       => rst_sys_n,
            rst_sys_i         => rst_sys,
            clk125m_i         => clk125m,
            rst_clk125m_i     => rst_clk125m,
            clk500m_i         => clk500m,
            clk_refclk_200m_i => clk200m,
            iodelay_reset_i   => iodelay_reset,
            wb_i              => wb_rf2_vtus_out,
            wb_o              => wb_rf2_vtus_in,
            tm_tai_i          => tm_tai,
            tm_cycles_i       => tm_cycles,                        

            rf_t1_sync_i            => nco_reset_rf2_trig1,
            rf_t1_sync_cdelay_i     => rf2_t1_sync_cdelay,
            rf_t1_sync_fdelay_i     => rf2_t1_sync_fdelay,
            rf_t1_sync_odelay_i     => rf2_t1_sync_odelay,
            rf_rst_cdelay_offset_i  => rf2_rst_cdelay_offset,
            rf_nco_reset_cdelayed_o => rf2_nco_reset_cdelayed,
            rf_rst_o                => open,

            rf_t1_sync_p_o      => rf2_sync_p_o,
            rf_t1_sync_n_o      => rf2_sync_n_o,

            rf_t1_clk_p_i    => rf2_t1_clk_p_i,
            rf_t1_clk_n_i    => rf2_t1_clk_n_i,
            rf_t1_p_o        => rf2_t1_p_o,
            rf_t1_n_o        => rf2_t1_n_o,
            rf_t1_rst_i      => rf2_t1_rst,
            rf_t1_rst_p_o    => rf2_t1_rst_p_o,
            rf_t1_rst_n_o    => rf2_t1_rst_n_o,
            rf_t1_start_i    => rf2_t1_start,
            rf_t1_stop_i     => rf2_t1_stop,

            rf_t2_clk_p_i    => rf2_t2_clk_p_i,
            rf_t2_clk_n_i    => rf2_t2_clk_n_i,
            rf_t2_p_o        => rf2_t2_p_o,
            rf_t2_n_o        => rf2_t2_n_o,
            rf_t2_rst_i      => rf2_t2_rst,
            rf_t2_rst_p_o    => rf2_t2_rst_p_o,
            rf_t2_rst_n_o    => rf2_t2_rst_n_o,
            rf_t2_start_i    => rf2_t2_start,
            rf_t2_stop_i     => rf2_t2_stop,

            rf_t1_softstart_o => rf2_t1_softstart,
            rf_t2_softstart_o => rf2_t2_softstart,
            rf_t1_softstop_o  => rf2_t1_softstop,
            rf_t2_softstop_o  => rf2_t2_softstop,

            rf_t1_vtu_start_p_o => rf2_t1_vtu_start_p,
            rf_t2_vtu_start_p_o => rf2_t2_vtu_start_p,

            rf_clk_bufg_o    => rf2_clk_bufg,

            rf_ila_dbg_o     => rf2_tu_ila_dbg );


    wr2rf_vme_p0_i : entity work.wr2rf_vme_p0
        port map (
            rf1_clk_bufg_i   => rf1_clk_bufg,
            rf2_clk_bufg_i   => rf2_clk_bufg,
            vme_p0_h1_bsb_o  => vme_p0_h1_bsb_o,
            vme_p0_h1_c40_o  => vme_p0_h1_c40_o,
            vme_p0_h1_lbb_o  => vme_p0_h1_lbb_o,
            vme_p0_h1_hbb_o  => vme_p0_h1_hbb_o,
            vme_p0_h1_tc_o   => vme_p0_h1_tc_o,
            vme_p0_h2_bsb_o  => vme_p0_h2_bsb_o,
            vme_p0_h2_c40_o  => vme_p0_h2_c40_o,
            vme_p0_h2_lbb_o  => vme_p0_h2_lbb_o,
            vme_p0_h2_hbb_o  => vme_p0_h2_hbb_o,
            vme_p0_h2_tc_o   => vme_p0_h2_tc_o,
            vme_p0_oen_o     => vme_p0_oen_o );

    --  When the WRcore is on reset, always set the ack to avoid a deadlock.
    wb_wrc_out2 <= (ack => wb_wrc_out.ack or not wrcore_reset_n,
                    stall => wb_wrc_out.stall,
                    err => wb_wrc_out.err,
                    rty => wb_wrc_out.rty,
                    dat => wb_wrc_out.dat);

    inst_wr2rf_regs_core: entity work.wr2rf_regs_core
       port map (
          clk_sys_i            => clk_sys_62m5,
          rst_sys_n_i          => rst_sys_n,

          clk_ref_i            => clk_sys_62m5,
          rst_ref_n_i          => rst_sys_n,

          clk125_i             => clk125m,
          rst_clk125_n_i       => rst_clk125m_n,

          wb_vme_i             => wb_vme_out,
          wb_vme_o             => wb_vme_in,

          wb_wrc_i             => wb_wrc_out2,
          wb_wrc_o             => wb_wrc_in,

          wb_rfframerxtx_i     => wb_rfframerxtx_in,
          wb_rfframerxtx_o     => wb_rfframerxtx_out,

          wb_rf1_vtus_i        => wb_rf1_vtus_in,
          wb_rf1_vtus_o        => wb_rf1_vtus_out,
          wb_rf2_vtus_i        => wb_rf2_vtus_in,
          wb_rf2_vtus_o        => wb_rf2_vtus_out,

          wb_rf1_rfnco_i       => wb_rf1_rfnco_in,
          wb_rf1_rfnco_o       => wb_rf1_rfnco_out,
          wb_rf2_rfnco_i       => wb_rf2_rfnco_in,
          wb_rf2_rfnco_o       => wb_rf2_rfnco_out,

          rf1_iqdac_phase_update_o    => rf1_iqdac_phase_update,
          rf2_iqdac_phase_update_o    => rf2_iqdac_phase_update,
          rf1_iqdac_igain_arm_o    => rf1_iqdac_igain_arm,
          rf1_iqdac_qgain_arm_o    => rf1_iqdac_qgain_arm,
          rf2_iqdac_igain_arm_o    => rf2_iqdac_igain_arm,
          rf2_iqdac_qgain_arm_o    => rf2_iqdac_qgain_arm,
          rf1_iqdac_igain_i    => rf1_iqdac_igain_r,
          rf1_iqdac_qgain_i    => rf1_iqdac_qgain_r,
          rf2_iqdac_igain_i    => rf2_iqdac_igain_r,
          rf2_iqdac_qgain_i    => rf2_iqdac_qgain_r,
          rf1_iqdac_ctrl_o     => rf1_iqdac_ctrl,
          rf2_iqdac_ctrl_o     => rf2_iqdac_ctrl,
          iqdac_ram_write_o    => iqdac_ram_write,
          iqdac_ram_addr_o     => iqdac_ram_addr,
          iqdac_ram_data_o     => iqdac_ram_data,
          iqdac_ram_play_o     => iqdac_ram_play,

          rf1_dds_ftw_valid_o  => rf1_dds_ftw_valid,
          rf1_dds_ftw_o        => rf1_dds_ftw,
          rf2_dds_ftw_valid_o  => rf2_dds_ftw_valid,
          rf2_dds_ftw_o        => rf2_dds_ftw,

          mmcm_locked_i        => mmcm_locked,
          clk_sel_o            => clk_sys_select,
          clk_sys_reset_o      => clk_sys_reset,
          wrcore_reset_n_o     => wrcore_reset_n,
          iodelay_reset_o      => iodelay_reset,

          mmcm_shift_incdec_o  => mmcm_shift_incdec,
          mmcm_shift_en_o      => mmcm_shift_en,
          mmcm_shift_busy_i    => mmcm_shift_busy,

          reconfigure_o        => reconfigure,

          tmg_clk_term_en_o      => tmg_clk_term_en_o,
          tmg_io_term_en_o       => tmg_io_term_en_o,
          tmg_clk_oe_o           => tmg_clk_oe_o,
          tmg_io_oe_o            => tmg_io_oe_o,

          rf1_t1_start_sel_o => rf1_t1_start_sel,
          rf1_t2_start_sel_o => rf1_t2_start_sel,
          rf2_t1_start_sel_o => rf2_t1_start_sel,
          rf2_t2_start_sel_o => rf2_t2_start_sel,
          rf1_t1_stop_sel_o  => rf1_t1_stop_sel,
          rf1_t2_stop_sel_o  => rf1_t2_stop_sel,
          rf2_t1_stop_sel_o  => rf2_t1_stop_sel,
          rf2_t2_stop_sel_o  => rf2_t2_stop_sel,

          tmgio1_osel_o     => tmgio1_osel,
          tmgio2_osel_o     => tmgio2_osel,
          tmgio3_osel_o     => tmgio3_osel,
          tmgio4_osel_o     => tmgio4_osel,
          tmgclk1_osel_o    => tmgclk1_osel,
          tmgclk2_osel_o    => tmgclk2_osel,

          lemo_gpio_o       => lemo_gpio,

          softstart_sel_o   => softstart_sel,
          softstop_sel_o    => softstop_sel,
          lemo_ext_sel_o    => lemo_ext_sel,

          ext_10m_dir_o        => ext_10m_dir,
          ext_pps_dir_o        => ext_pps_dir,

          dds_cs_n_o           => dds_cs_n_o,
          rf1_iqdac_cs_n_o     => rf1_iqdac_cs_n_o,
          rf2_iqdac_cs_n_o     => rf2_iqdac_cs_n_o,
          rf_sclk_o            => rf_sclk_o,
          rf_sdi_o             => rf_sdi_o,
          rf_sdo_i             => rf_sdo_i,

          pll_main_cs_n_o      => pll_main_cs_n_o,
          pll_main_sclk_o      => pll_main_sclk_o,
          pll_main_sdi_o       => pll_main_sdi_o,
          pll_main_sdo_i       => pll_main_sdo_i,

          pll_main_error_i     => pll_main_stat_i(1),
          pll_main_locked_i    => pll_main_stat_i(2),
          pll_main_sync_o      => pll_main_sync_o,

          dds_reset_o           => dds_reset_o,
          dds_ioupdate_o        => dds_ioupdate,
          dds_profile_o         => dds_profile_o,
          dds_ioupdate_fdelay_o => dds_ioupdate_fdelay,
          dds_ioupdate_odelay_o => dds_ioupdate_odelay,
          dds_sync_error_i      => dds_sync_error_i,

          ocxo_enabled_o       => ocxo_enabled,
          ocxo_uptime_i        => ocxo_uptime,

          wr2rfsd_nco_azimuthal_o  => open,
          wr2rfsd_nco_cabledelay_o => open,
          wr2rfsd_nco_hb_o         => open,
          loc_nco_ctrl_reset_o     => loc_nco_ctrl_reset,
          loc_nco_h1_ftw_o         => loc_nco_h1_ftw,
          loc_nco_h1_prog_o        => loc_nco_h1_prog,
          loc_nco_update_valid_o   => loc_nco_update_valid,
          loc_or_wrs_params_sel_o  => loc_or_wrs_params_sel,

          wrs_frame_last_ftw_i           => wrs_rx_RFmFramePayloads.FTW_H1_main,
          wrs_frame_last_ctrl_i          => wrs_rx_RFmFramePayloads.control,
          wrs_frame_last_rxwrtimestamp_i => wrs_frame_rxwrtimestamp_r,
          wrs_frame_last_txwrtimestamp_i => wrs_frame_txwrtimestamp_r,
          wrs_frame_last_rftimestamp_i   => wrs_frame_rftimestamp_r,
          wrs_frame_counter_i            => std_logic_vector(wrs_frame_counter_r),
          rfframe_ts_update_o            => rfframe_ts_update,
          rfframe_nco_reset_tai_i        => rfframe_nco_reset_tai_h,
          rfframe_nco_reset_cycles_i     => rfframe_nco_reset_cycles_h,
          rfframe_tai_i                  => rfframe_tai_h,
          rfframe_cycles_i               => rfframe_cycles_h,

          txframe_payload_o    => txframe_payload,

          nco_reset_dds_mask_o       => nco_reset_dds_mask,
          nco_reset_rfnco_ch1_mask_o => nco_reset_rfnco_ch1_mask,
          nco_reset_rfnco_ch2_mask_o => nco_reset_rfnco_ch2_mask,
          nco_reset_rf1_trig1_mask_o => nco_reset_rf1_trig1_mask,
          nco_reset_rf2_trig1_mask_o => nco_reset_rf2_trig1_mask,
          nco_reset_soft_o           => nco_reset_soft,

          rf1_mux_sel_o        => rf1_mux_sel_o,
          rf1_mixer_en_o       => rf1_mixer_en_o,
          rf1_iqdac_reset_o    => rf1_iqdac_reset_o,
          rf1_t1_delay_oen_o   => rf1_t1_delay_oen_o,
          rf1_t1_mux_sel_o     => rf1_t1_mux_sel_o,
          rf1_t1_rst_o         => rf1_t1_rst,
          rf1_t1_delay_latch_o => rf1_t1_delay_latch,
          rf1_rst_cdelay_offset_o  => rf1_rst_cdelay_offset,
          rf1_t1_sync_cdelay_o => rf1_t1_sync_cdelay,
          rf1_t1_sync_fdelay_o => rf1_t1_sync_fdelay,
          rf1_t1_sync_odelay_o => rf1_t1_sync_odelay,
          rf1_t2_delay_oen_o   => rf1_t2_delay_oen_o,
          rf1_t2_mux_sel_o     => rf1_t2_mux_sel_o,
          rf1_t2_rst_o         => rf1_t2_rst,
          rf1_t2_delay_latch_o => rf1_t2_delay_latch,
          rf1_start_lpbk_o     => rf1_start_lpbk,
          rf1_t1_vtu_start_p_i => rf1_t1_vtu_start_p,
          rf1_t2_vtu_start_p_i => rf1_t2_vtu_start_p,

          rf2_mux_sel_o        => rf2_mux_sel_o,
          rf2_mixer_en_o       => rf2_mixer_en_o,
          rf2_iqdac_reset_o    => rf2_iqdac_reset_o,
          rf2_t1_delay_oen_o   => rf2_t1_delay_oen_o,
          rf2_t1_mux_sel_o     => rf2_t1_mux_sel_o,
          rf2_t1_rst_o         => rf2_t1_rst,
          rf2_t1_delay_latch_o => rf2_t1_delay_latch,
          rf2_rst_cdelay_offset_o  => rf2_rst_cdelay_offset,
          rf2_t1_sync_cdelay_o => rf2_t1_sync_cdelay,
          rf2_t1_sync_fdelay_o => rf2_t1_sync_fdelay,
          rf2_t1_sync_odelay_o => rf2_t1_sync_odelay,
          rf2_t2_delay_oen_o   => rf2_t2_delay_oen_o,
          rf2_t2_mux_sel_o     => rf2_t2_mux_sel_o,
          rf2_t2_rst_o         => rf2_t2_rst,
          rf2_t2_delay_latch_o => rf2_t2_delay_latch,
          rf2_start_lpbk_o     => rf2_start_lpbk,
          rf2_t1_vtu_start_p_i => rf2_t1_vtu_start_p,
          rf2_t2_vtu_start_p_i => rf2_t2_vtu_start_p,

          rf_trig_ff_delay_o   => rf_trig_ff_delay,

          flash_cs_n_o         => spi_flash_cs_n_sys,
          flash_miso_i         => spi_flash_miso_i,
          flash_mosi_o         => spi_flash_mosi_sys,
          flash_sck_o          => spi_flash_sck_sys,

          bmctrl_rfframe_ctrl_update_o => bmctrl_rfframe_ctrl_update,
          bmctrl_rfframe_status_fifo_rdy_i => bmctrl_rfframe_status_fifo_rdy,
          bmctrl_rfframe_ctrl_reset_o      => bmctrl_rfframe_ctrl_reset,
          bmctrl_rfframe_ctrl_en_o         => bmctrl_rfframe_ctrl_en,

          xadc_wb_i            => xadc_wb_in,
          xadc_wb_o            => xadc_wb_out,

          tm_tai_i             => tm_tai,
          tm_cycles_i          => tm_cycles,
          tm_linkup_i          => tm_link_up,
          tm_time_valid_i      => tm_time_valid,

          pps_i                => pps,
          ila_sigs_o           => regs_ila );

    -- outputs
    rf_trig_ff_delay_o   <= rf_trig_ff_delay;
    rf1_t1_delay_latch_o <= rf1_t1_delay_latch;
    rf1_t2_delay_latch_o <= rf1_t2_delay_latch;
    rf2_t1_delay_latch_o <= rf2_t1_delay_latch;
    rf2_t2_delay_latch_o <= rf2_t2_delay_latch;

    ocxo_en_o <= ocxo_enabled;
    inst_wr2rf_ocxo : entity work.wr2rf_ocxo
       port map (
          clk_sys_i      => clk_sys_62m5,
          ocxo_enabled_i => ocxo_enabled,
          ocxo_uptime_o  => ocxo_uptime );

    -- ext_ref_signals
    ext_10m_dir_o   <= ext_10m_dir;
    ext_pps_dir_o   <= ext_pps_dir;

    -- timing_io
    tmg_clk_oe_n_o  <= not tmg_clk_oe_o;
    tmg_io_oe_n_o   <= not tmg_io_oe_o;


    inst_wr2rf_lemo : entity work.wr2rf_lemo
       port map (
          clk_sys_i        => clk_sys_62m5,
          rst_sys_n_i      => rst_sys_n,
          clk125m_i        => clk125m,

          tmg_clk_i         => tmg_clk_i,
          tmg_io_i          => tmg_io_i,
          tmg_clk_o         => tmg_clk_o,
          tmg_io_o          => tmg_io_o,

          rf1_t1_start_sel_i => rf1_t1_start_sel,
          rf1_t2_start_sel_i => rf1_t2_start_sel,
          rf2_t1_start_sel_i => rf2_t1_start_sel,
          rf2_t2_start_sel_i => rf2_t2_start_sel,
          rf1_t1_stop_sel_i  => rf1_t1_stop_sel,
          rf1_t2_stop_sel_i  => rf1_t2_stop_sel,
          rf2_t1_stop_sel_i  => rf2_t1_stop_sel,
          rf2_t2_stop_sel_i  => rf2_t2_stop_sel,

          rf1_t1_start_o   => rf1_t1_start,
          rf1_t2_start_o   => rf1_t2_start,
          rf2_t1_start_o   => rf2_t1_start,
          rf2_t2_start_o   => rf2_t2_start,
          rf1_t1_stop_o    => rf1_t1_stop,
          rf1_t2_stop_o    => rf1_t2_stop,
          rf2_t1_stop_o    => rf2_t1_stop,
          rf2_t2_stop_o    => rf2_t2_stop,

          wrs_rx_valid_i   => wrs_rx_valid,
          wrs_tx_valid_i   => wrs_tx_valid,
          nco_reset_i      => rx_reset_nco_pulse,
          rf1_nco_reset_cdelayed_i => rf1_nco_reset_cdelayed,
          rf2_nco_reset_cdelayed_i => rf2_nco_reset_cdelayed,
          rf1_frev_i       => rf1_frev,
          rf1_frev_main_i  => rf1_frev_main,
          rf2_frev_i       => rf2_frev,
          rf2_frev_main_i  => rf2_frev_main,
          lemo_gpio_i      => lemo_gpio,
          rf_rst_i         => rf1_rst_rf,

          softstart_sel_i     => softstart_sel,
          softstop_sel_i      => softstop_sel,
          rf1_t1_softstart_i  => rf1_t1_softstart,
          rf1_t2_softstart_i  => rf1_t2_softstart,
          rf2_t1_softstart_i  => rf2_t1_softstart,
          rf2_t2_softstart_i  => rf2_t2_softstart,
          rf1_t1_softstop_i   => rf1_t1_softstop,
          rf1_t2_softstop_i   => rf1_t2_softstop,
          rf2_t1_softstop_i   => rf2_t1_softstop,
          rf2_t2_softstop_i   => rf2_t2_softstop,
          lemo_ext_sel_i      => lemo_ext_sel,

          tmgio1_osel_i     => tmgio1_osel,
          tmgio2_osel_i     => tmgio2_osel,
          tmgio3_osel_i     => tmgio3_osel,
          tmgio4_osel_i     => tmgio4_osel,
          tmgclk1_osel_i    => tmgclk1_osel,
          tmgclk2_osel_i    => tmgclk2_osel );

    -- debug
    g_std_dbg : if g_ila_debug = "standard" generate
    begin
       ila_sigs(0)  <= clk_sys_select;
       ila_sigs(1)  <= clk_sys_reset;
       ila_sigs(2)  <= mmcm_shift_incdec;
       ila_sigs(3)  <= mmcm_shift_en;
       ila_sigs(4)  <= mmcm_shift_busy;
       ila_sigs(5)  <= mmcm_locked;
       ila_sigs(6)  <= wrcore_reset_n;
       ila_sigs(7)  <= vme_sysreset_n_i;

       ila_sigs(8)  <= wb_vme_out.stb;
       ila_sigs(9)  <= wb_vme_out.we;
       ila_sigs(10) <= wb_vme_out.cyc;
       ila_sigs(11) <= wb_vme_in.ack;
       ila_sigs(12) <= wb_vme_in.stall;

       ila_sigs(13) <= wb_wrc_in.stb;
       ila_sigs(14) <= wb_wrc_in.we;
       ila_sigs(15) <= wb_wrc_out.ack;

       ila_sigs(63 downto 16)   <= vme_dbg;
       ila_sigs(78 downto 64)   <= rf1_tu_ila_dbg(14 downto 0);
       ila_sigs(79) <= rf1_nco_reset_cdelayed;
       ila_sigs(95 downto 80)   <= rf2_tu_ila_dbg(15 downto 0);
       ila_sigs(96)             <= rf1_t1_vtu_start_p;
       ila_sigs(97)             <= rf1_t2_vtu_start_p;
       ila_sigs(98)             <= rf2_t1_vtu_start_p;
       ila_sigs(99)             <= rf2_t2_vtu_start_p;
       --ila_sigs(69 downto 64)   <= rf1_t1_start_sel;
       --ila_sigs(70)             <= rf1_t1_start;
       --ila_sigs(71)             <= rf1_t2_start;
       --ila_sigs(77 downto 72)   <= rf1_t1_stop_sel;
       --ila_sigs(78)             <= rf1_t1_stop;
       --ila_sigs(79)             <= rf1_t2_stop;
       --ila_sigs(80)             <= iodelay_reset;
       --ila_sigs(81)             <= rf1_t1_rst;
       --ila_sigs(82)             <= rf1_t2_rst;
       --ila_sigs(83)             <= rf2_t1_rst;
       --ila_sigs(84)             <= rf2_t2_rst;
       --ila_sigs(85)             <= reconfigure;
       --ila_sigs(86)             <= rf1_t1_delay_latch;
       --ila_sigs(87)             <= rf1_t2_delay_latch;
       --ila_sigs(88)             <= rf2_t1_delay_latch;
       --ila_sigs(89)             <= rf2_t2_delay_latch;
       --ila_sigs(99 downto 90)   <= rf_trig_ff_delay;
       ila_sigs(100)            <= clk_ext_rst;
       ila_sigs(101)            <= clk_ext_stopped;
       ila_sigs(102)            <= clk_ext_mul_locked;
       ila_sigs(103)            <= clk_ext_10m_in;
       ila_sigs(104)            <= pps_i;
       ila_sigs(105)            <= ext_pps_dir;
       ila_sigs(109 downto 106) <= tmg_io_i;
       ila_sigs(111 downto 110) <= tmg_clk_i;
       ila_sigs(112)            <= wb_rf1_rfnco_out.stb;
       ila_sigs(113)            <= wb_rf1_rfnco_out.we;
       ila_sigs(114)            <= wb_rf1_rfnco_in.ack;
       ila_sigs(115)            <= wrs_rx_Frame_valid_pX;
       ila_sigs(116)            <= rx_Frame_valid_pX;
       ila_sigs(117)            <= wrs_rx_valid;
       ila_sigs(118)            <= wrs_rx_dreq;
       ila_sigs(119)            <= wrs_frame_valid;
       ila_sigs(120)            <= loc_or_wrs_params_sel;
       ila_sigs(121)            <= wrs_tx_valid;
       ila_sigs(122)            <= wrs_tx_dreq;
       ila_sigs(123)            <= tm_link_up;
       ila_sigs(124)            <= tm_time_valid;
       ila_sigs(125)            <= rx_reset_nco_pulse;
       ila_sigs(126)            <= rf1_frev;
       ila_sigs(127)            <= rf1_frev_main;

       ila_clk <= clk_sys_62m5;
    end generate;

    g_rfnco_dbg : if g_ila_debug = "rfnco" generate
       ila_sigs <= rfnco1_ila_dbg;
       ila_clk  <= clk125m;
    end generate;

    ila_i : entity work.ila
       generic map (
          ila_en      => true )
       port map (
          clk0        => ila_clk,
          ila0        => ila_sigs );

    spi_flash_cs_n_o <= spi_flash_cs_n_sys and spi_flash_cs_n_wrc;
    spi_flash_mosi_o <= spi_flash_mosi_sys or  spi_flash_mosi_wrc;
    spi_flash_sck    <= spi_flash_sck_sys  or  spi_flash_sck_wrc;

    inst_STARTUPE2 : STARTUPE2
      generic map (
        PROG_USR => "FALSE",  -- Activate program event security feature. Requires encrypted bitstreams.
        SIM_CCLK_FREQ => 0.0  -- Set the Configuration Clock Frequency(ns) for simulation.
        )
      port map (
        CFGCLK => open,   -- 1-bit output: Configuration main clock output
        CFGMCLK => open,  -- 1-bit output: Configuration internal oscillator clock output
        EOS => open,      -- 1-bit output: Active high output signal indicating the End Of Startup.
        PREQ => open,     -- 1-bit output: PROGRAM request to fabric output
        CLK => '0',       -- 1-bit input: User start-up clock input
        GSR => '0',       -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
        GTS => '0',       -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
        KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
        PACK => '0',      -- 1-bit input: PROGRAM acknowledge input
        USRCCLKO => spi_flash_sck,   -- 1-bit input: User CCLK input
        USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
        USRDONEO => '0',  -- 1-bit input: User DONE pin output control
        USRDONETS => '1'  -- 1-bit input: User DONE 3-state enable output
    );

  --  ICAPE2 sequence for reconfiguration.
  --  See UG470 table 7.1
  process (clk_sys_62m5) is
  begin
    if rising_edge(clk_sys_62m5) then
      if rst_sys_n = '0' then
        reconfig_cnt <= 0;
        icap_en_n <= '1';
        icap_dat <= (others => '1');
      else
        reconfig_cnt <= reconfig_cnt + 1;
        icap_en_n <= '0';

        case reconfig_cnt is
          when 0 =>
            if reconfigure = '0' then
              --  Do not start reconfiguration.
              reconfig_cnt <= 0;
            end if;
            icap_en_n <= '1';
            icap_dat <= (others => '1');
          when 1 =>
            icap_dat <= x"aa99_5566"; -- sync word
          when 2 =>
            icap_dat <= x"2000_0000"; -- type 1 no op
          when 3 =>
            icap_dat <= x"3002_0001"; -- Write 1 word to WBSTAR
          when 4 =>
            icap_dat <= x"0000_0000"; -- boot address
          when 5 =>
            icap_dat <= x"2000_0000"; -- type 1 no op
          when 6 =>
            icap_dat <= x"3000_8001"; -- write 1 word to CMD
          when 7 =>
            icap_dat <= x"0000_000f"; -- IPROG
          when 8 =>
            icap_dat <= x"2000_0000"; -- type 1 no op
          when others =>
            icap_dat <= x"2000_0000"; -- type 1 no op
            icap_en_n <= '1';
            reconfig_cnt <= 15;
        end case;
      end if;
    end if;
  end process;

  --  Reverse bit in bytes
  process (icap_dat) is
  begin
    for i in 0 to 3 loop
      for j in 0 to 7 loop
        icap_dat_rev (i * 8 + 7 - j) <= icap_dat(i * 8 + j);
      end loop;
    end loop;
  end process;

  inst_ICAPE2 : ICAPE2
    generic map (
      DEVICE_ID => X"3651093",  -- Specifies the pre-programmed Device ID value to be used for simulation
      ICAP_WIDTH => "X32",-- Specifies the input and output data width.
      SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
    )
    port map (
      O => open,
      CLK => clk_sys_62m5,
      CSIB => icap_en_n,
      I => icap_dat_rev,
      RDWRB => '0'
    );

  b_xadc: block is
    signal den : std_logic;
  begin
    den <= xadc_wb_out.stb and xadc_wb_out.cyc;

    -- xadc_wb_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => (others => '0'));

    xadc_wb_in.err <= '0';
    xadc_wb_in.rty <= '0';
    xadc_wb_in.stall <= '0';

  inst_xadc : XADC
    generic map(
      INIT_40 => b"1_0_11_0000_00000000", -- config reg 0: CAVG, AVG=256,
      INIT_41 => b"0010_0000_0000_1111", -- config reg 1: continuous
      INIT_42 => X"0400", -- config reg 2: adcclk max is 26Mhz, DCLK / 4 ~= 15Mhz
      INIT_48 => X"4701", -- Sequencer channel: cal(0), temp(8), vccint(9), vccaux(10), vccbram(14)
      INIT_49 => X"0004", -- Sequencer channel: ch2(2)
      INIT_4A => X"4701", -- Sequencer Average: same
      INIT_4B => X"d804", -- Sequencer Average
      INIT_4C => X"0000", -- Sequencer Bipolar: unipolar 
      INIT_4D => X"0000", -- Sequencer Bipolar: 
      INIT_4E => X"0000", -- Sequencer Acq time selection
      INIT_4F => X"0000", -- Sequencer Acq time selection
      INIT_50 => X"B5ED", -- Temp alarm trigger
      INIT_51 => X"57E4", -- Vccint upper alarm limit
      INIT_52 => X"A147", -- Vccaux upper alarm limit
      INIT_53 => X"CA33",  -- Temp alarm OT upper
      INIT_54 => X"A93A", -- Temp alarm reset
      INIT_55 => X"52C6", -- Vccint lower alarm limit
      INIT_56 => X"9555", -- Vccaux lower alarm limit
      INIT_57 => X"AE4E",  -- Temp alarm OT reset
      INIT_58 => X"5999",  -- Vccbram upper alarm limit
      INIT_5C => X"5111",  -- Vccbram lower alarm limit
      SIM_DEVICE => "7SERIES",
      SIM_MONITOR_FILE => "unused.txt"
    )
    port map (
      CONVST              => '0',
      CONVSTCLK           => '0',
      DCLK                => clk_sys_62m5,
      RESET               => rst_sys,
      DADDR               => xadc_wb_out.adr(7 downto 1),
      DEN                 => den,
      DI                  => xadc_wb_out.dat(15 downto 0),
      DWE                 => xadc_wb_out.we,
      DRDY                => xadc_wb_in.ack,
      VAUXN(1 downto 0)   => (others => '0'),
      VAUXN(2)            => ocxo_sense_n_i,
      VAUXN(15 downto 3)  => (others => '0'),
      VAUXP(1 downto 0)   => (others => '0'),
      VAUXP(2)            => ocxo_sense_p_i,
      VAUXP(15 downto 3)  => (others => '0'),
      ALM                 => open,
      BUSY                => open,
      CHANNEL             => open,
      DO(15 downto 0)     => xadc_wb_in.dat(15 downto 0),
      EOC                 => open,
      EOS                 => open,
      JTAGBUSY            => open,
      JTAGLOCKED          => open,
      JTAGMODIFIED        => open,
      OT                  => open,
    
      MUXADDR             => open,
      VN                  => '0',
      VP                  => '0'
    );
  end block;

end rtl;
