-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
-- Generated on Wed May 10 11:16:39 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

entity wr2rf_rftrigger_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- WB bus t1
    t1_i                 : in    t_wishbone_master_in;
    t1_o                 : out   t_wishbone_master_out;

    -- WB bus t2
    t2_i                 : in    t_wishbone_master_in;
    t2_o                 : out   t_wishbone_master_out;

    -- Control register
    -- Enable the unit
    rf_diag_control_enable_o : out   std_logic;
    -- Select the window to measure the frequency.  A change to this value is taken into account at the end of the current window. 000: 5us; 010: 500us; 100: 50ms; 101: 5s; 110: 20s 001, 011, 111: unused.
    rf_diag_control_window_o : out   std_logic_vector(2 downto 0);

    -- This register is incremented at the end of the window, when the new frequency is made available.
    rf_diag_generation_i : in    std_logic_vector(15 downto 0);

    -- Number of period of the input signal during the previous window period.
    rf_diag_freq_i       : in    std_logic_vector(31 downto 0);

    -- This register is incremented on each rising edge of the signal. Not valid if the input frequency is greater than the clock.
    rf_diag_counter_i    : in    std_logic_vector(31 downto 0)
  );
end wr2rf_rftrigger_regs;

architecture syn of wr2rf_rftrigger_regs is
  signal adr_int                        : std_logic_vector(8 downto 1);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal t1_re                          : std_logic;
  signal t1_we                          : std_logic;
  signal t1_wt                          : std_logic;
  signal t1_rt                          : std_logic;
  signal t1_tr                          : std_logic;
  signal t1_wack                        : std_logic;
  signal t1_rack                        : std_logic;
  signal t2_re                          : std_logic;
  signal t2_we                          : std_logic;
  signal t2_wt                          : std_logic;
  signal t2_rt                          : std_logic;
  signal t2_tr                          : std_logic;
  signal t2_wack                        : std_logic;
  signal t2_rack                        : std_logic;
  signal rf_diag_control_enable_reg     : std_logic;
  signal rf_diag_control_window_reg     : std_logic_vector(2 downto 0);
  signal rf_diag_control_wreq           : std_logic;
  signal rf_diag_control_wack           : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(15 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(8 downto 1);
  signal wr_dat_d0                      : std_logic_vector(15 downto 0);
  signal wr_sel_d0                      : std_logic_vector(1 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(8 downto 1);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat(15 downto 0) <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat(15 downto 0);
        wr_sel_d0 <= wb_i.sel(1 downto 0);
      end if;
    end if;
  end process;

  -- Interface t1
  t1_tr <= t1_wt or t1_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        t1_rt <= '0';
        t1_wt <= '0';
      else
        t1_rt <= (t1_rt or t1_re) and not t1_rack;
        t1_wt <= (t1_wt or t1_we) and not t1_wack;
      end if;
    end if;
  end process;
  t1_o.cyc <= t1_tr;
  t1_o.stb <= t1_tr;
  t1_wack <= t1_i.ack and t1_wt;
  t1_rack <= t1_i.ack and t1_rt;
  t1_o.adr <= ((24 downto 0 => '0') & adr_int(6 downto 1)) & (0 downto 0 => '0');
  t1_o.sel(1 downto 0) <= wr_sel_d0;
  t1_o.we <= t1_wt;
  t1_o.dat(15 downto 0) <= wr_dat_d0;

  -- Interface t2
  t2_tr <= t2_wt or t2_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        t2_rt <= '0';
        t2_wt <= '0';
      else
        t2_rt <= (t2_rt or t2_re) and not t2_rack;
        t2_wt <= (t2_wt or t2_we) and not t2_wack;
      end if;
    end if;
  end process;
  t2_o.cyc <= t2_tr;
  t2_o.stb <= t2_tr;
  t2_wack <= t2_i.ack and t2_wt;
  t2_rack <= t2_i.ack and t2_rt;
  t2_o.adr <= ((24 downto 0 => '0') & adr_int(6 downto 1)) & (0 downto 0 => '0');
  t2_o.sel(1 downto 0) <= wr_sel_d0;
  t2_o.we <= t2_wt;
  t2_o.dat(15 downto 0) <= wr_dat_d0;

  -- Register rf_diag_control
  rf_diag_control_enable_o <= rf_diag_control_enable_reg;
  rf_diag_control_window_o <= rf_diag_control_window_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf_diag_control_enable_reg <= '0';
        rf_diag_control_window_reg <= "000";
        rf_diag_control_wack <= '0';
      else
        if rf_diag_control_wreq = '1' then
          rf_diag_control_enable_reg <= wr_dat_d0(4);
          rf_diag_control_window_reg <= wr_dat_d0(2 downto 0);
        end if;
        rf_diag_control_wack <= rf_diag_control_wreq;
      end if;
    end if;
  end process;

  -- Register rf_diag_generation

  -- Register rf_diag_freq

  -- Register rf_diag_counter

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, t1_wack, t2_wack, rf_diag_control_wack) begin
    t1_we <= '0';
    t2_we <= '0';
    rf_diag_control_wreq <= '0';
    case wr_adr_d0(8 downto 7) is
    when "00" =>
      -- Submap t1
      t1_we <= wr_req_d0;
      wr_ack_int <= t1_wack;
    when "01" =>
      -- Submap t2
      t2_we <= wr_req_d0;
      wr_ack_int <= t2_wack;
    when "10" =>
      case wr_adr_d0(6 downto 2) is
      when "00000" =>
        case wr_adr_d0(1 downto 1) is
        when "0" =>
          -- Reg rf_diag_control
          rf_diag_control_wreq <= wr_req_d0;
          wr_ack_int <= rf_diag_control_wack;
        when "1" =>
          -- Reg rf_diag_generation
          wr_ack_int <= wr_req_d0;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "00001" =>
        case wr_adr_d0(1 downto 1) is
        when "0" =>
          -- Reg rf_diag_freq
          wr_ack_int <= wr_req_d0;
        when "1" =>
          -- Reg rf_diag_freq
          wr_ack_int <= wr_req_d0;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "00010" =>
        case wr_adr_d0(1 downto 1) is
        when "0" =>
          -- Reg rf_diag_counter
          wr_ack_int <= wr_req_d0;
        when "1" =>
          -- Reg rf_diag_counter
          wr_ack_int <= wr_req_d0;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, t1_i.dat, t1_rack, t2_i.dat, t2_rack,
           rf_diag_control_window_reg, rf_diag_control_enable_reg,
           rf_diag_generation_i, rf_diag_freq_i, rf_diag_counter_i) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    t1_re <= '0';
    t2_re <= '0';
    case adr_int(8 downto 7) is
    when "00" =>
      -- Submap t1
      t1_re <= rd_req_int;
      rd_dat_d0 <= t1_i.dat(15 downto 0);
      rd_ack_d0 <= t1_rack;
    when "01" =>
      -- Submap t2
      t2_re <= rd_req_int;
      rd_dat_d0 <= t2_i.dat(15 downto 0);
      rd_ack_d0 <= t2_rack;
    when "10" =>
      case adr_int(6 downto 2) is
      when "00000" =>
        case adr_int(1 downto 1) is
        when "0" =>
          -- Reg rf_diag_control
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0(2 downto 0) <= rf_diag_control_window_reg;
          rd_dat_d0(3) <= '0';
          rd_dat_d0(4) <= rf_diag_control_enable_reg;
          rd_dat_d0(15 downto 5) <= (others => '0');
        when "1" =>
          -- Reg rf_diag_generation
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= rf_diag_generation_i;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "00001" =>
        case adr_int(1 downto 1) is
        when "0" =>
          -- Reg rf_diag_freq
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= rf_diag_freq_i(31 downto 16);
        when "1" =>
          -- Reg rf_diag_freq
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= rf_diag_freq_i(15 downto 0);
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "00010" =>
        case adr_int(1 downto 1) is
        when "0" =>
          -- Reg rf_diag_counter
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= rf_diag_counter_i(31 downto 16);
        when "1" =>
          -- Reg rf_diag_counter
          rd_ack_d0 <= rd_req_int;
          rd_dat_d0 <= rf_diag_counter_i(15 downto 0);
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
