--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- WR2RF_VME core
-- https://ohwr.org/project/vme-rf-wr-bobr
--------------------------------------------------------------------------------
--
-- unit name:   svec_wr2rf_vme
--
-- description: top level for the svec_wr2rf_vme mockup
--
--------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN (home.cern)
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
use work.streamers_pkg.all;
use work.RFFrameTransceiver_pkg.all;

entity svec_wr2rf_vme is
   generic (
      g_simulation  : integer := 0;
      g_dpram_size  : integer := 131072/4;
      g_dpram_initf : string  := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram" );
   port (
      ---------------------------------------------------------------------------
      -- Clocks/resets
      ---------------------------------------------------------------------------

      -- Reset from system fpga
      rst_n_i : in std_logic;

      -- Local oscillators
      clk_20m_vcxo_i : in std_logic;                -- 20MHz VCXO clock

      clk_125m_pllref_p_i : in std_logic;           -- 125 MHz PLL reference
      clk_125m_pllref_n_i : in std_logic;

      clk_125m_gtp_n_i : in std_logic;              -- 125 MHz GTP reference
      clk_125m_gtp_p_i : in std_logic;


      ---------------------------------------------------------------------------
      -- VME interface D16 A24
      -- Note: retry, berr not required
      --       addr is input only.
      ---------------------------------------------------------------------------

      vme_write_n_i    : in    std_logic;
      vme_sysreset_n_i : in    std_logic;
      vme_retry_oe_o   : out   std_logic;
      vme_retry_n_o    : out   std_logic;
      vme_lword_n_b    : inout std_logic;
      vme_iackout_n_o  : out   std_logic;
      vme_iackin_n_i   : in    std_logic;
      vme_iack_n_i     : in    std_logic;
      vme_dtack_oe_o   : out   std_logic;
      vme_dtack_n_o    : out   std_logic;
      vme_ds_n_i       : in    std_logic_vector(1 downto 0);
      vme_data_oe_n_o  : out   std_logic;
      vme_data_dir_o   : out   std_logic;
      vme_berr_o       : out   std_logic;
      vme_as_n_i       : in    std_logic;
      vme_irq_o        : out   std_logic_vector(7 downto 1);
      vme_data_b       : inout std_logic_vector(15 downto 0);
      vme_am_i         : in    std_logic_vector(5 downto 0);
      vme_addr_b       : inout std_logic_vector(23 downto 1);

      --  Geographic address
      vme_gap_i        : in    std_logic;
      vme_ga_n_i       : in    std_logic_vector(4 downto 0);

      vme_addr_oe_n_o  : out   std_logic;
      vme_addr_dir_o   : out   std_logic;

      --  Switches in absence of vme64x.
      vme_noga_n_i     : in    std_logic_vector(4 downto 0);

      -- SPI interfaces to DACs
      pll20dac_din_o    : out std_logic;
      pll20dac_sclk_o   : out std_logic;
      pll20dac_sync_n_o : out std_logic;
      pll25dac_din_o    : out std_logic;
      pll25dac_sclk_o   : out std_logic;
      pll25dac_sync_n_o : out std_logic;

      -- SFP I/O for transceiver
      sfp_txp_o         : out   std_logic;
      sfp_txn_o         : out   std_logic;
      sfp_rxp_i         : in    std_logic;
      sfp_rxn_i         : in    std_logic;
      sfp_mod_def0_i    : in    std_logic;          -- sfp detect
      sfp_mod_def1_b    : inout std_logic;          -- scl
      sfp_mod_def2_b    : inout std_logic;          -- sda
      sfp_rate_select_o : out   std_logic;
      sfp_tx_fault_i    : in    std_logic;
      sfp_tx_disable_o  : out   std_logic;
      sfp_los_i         : in    std_logic;

      -- Carrier I2C EEPROM
      carrier_scl_b : inout std_logic;
      carrier_sda_b : inout std_logic;

      -- Onewire interface
      onewire_b : inout std_logic;

      -- UART
      uart_rxd_i : in  std_logic;
      uart_txd_o : out std_logic;

      -- SPI (flash is connected to SFPGA and routed to AFPGA
      -- once the boot process is complete)
      spi_sclk_o : out std_logic;
      spi_ncs_o  : out std_logic;
      spi_mosi_o : out std_logic;
      spi_miso_i : in  std_logic;

      -- Carrier front panel LEDs
      fp_led_line_oen_o : out std_logic_vector(1 downto 0);
      fp_led_line_o     : out std_logic_vector(1 downto 0);
      fp_led_column_o   : out std_logic_vector(3 downto 0);

      -- svec fp io, all outputs here
      fp_gpio1_o      : out std_logic;
      fp_gpio2_o      : out std_logic;
      fp_gpio3_o      : out std_logic;
      fp_gpio4_o      : out std_logic;
      fp_term_en_o    : out std_logic_vector(4 downto 1);
      fp_gpio1_a2b_o  : out std_logic;
      fp_gpio2_a2b_o  : out std_logic;
      fp_gpio34_a2b_o : out std_logic;

      -- wr2rfsd bounce pads...
      frev_p_b        : inout std_logic;
      frev_n_b        : inout std_logic;
      bclk_p_b        : inout std_logic;
      bclk_n_b        : inout std_logic;

      --rf trigger unit via dio boards
      fmc1_dio_clk_p_i   : in  std_logic;
      fmc1_dio_clk_n_i   : in  std_logic;
      fmc1_dio_n_i       : in  std_logic_vector(5 downto 1);
      fmc1_dio_p_i       : in  std_logic_vector(5 downto 1);
      fmc1_dio_n_o       : out std_logic_vector(5 downto 1);
      fmc1_dio_p_o       : out std_logic_vector(5 downto 1);
      fmc1_dio_oe_n_o    : out std_logic_vector(5 downto 1);
      fmc1_dio_term_en_o : out std_logic_vector(5 downto 1);
      fmc1_dio_led_top_o : out std_logic;
      fmc1_dio_led_bot_o : out std_logic;

      fmc2_dio_clk_p_i   : in  std_logic;
      fmc2_dio_clk_n_i   : in  std_logic;
      fmc2_dio_n_i       : in  std_logic_vector(5 downto 1);
      fmc2_dio_p_i       : in  std_logic_vector(5 downto 1);
      fmc2_dio_n_o       : out std_logic_vector(5 downto 1);
      fmc2_dio_p_o       : out std_logic_vector(5 downto 1);
      fmc2_dio_oe_n_o    : out std_logic_vector(5 downto 1);
      fmc2_dio_term_en_o : out std_logic_vector(5 downto 1);
      fmc2_dio_led_top_o : out std_logic;
      fmc2_dio_led_bot_o : out std_logic );

end svec_wr2rf_vme;

architecture rtl of svec_wr2rf_vme is
   constant c_pcs_data_width : integer := 16;

   subtype t_poweron_counter is natural range 0 to 15;

   -- clock and reset
   signal areset_n       : std_logic;
   signal clk_sys_62m5   : std_logic;
   signal rst_sys_62m5_n : std_logic;
   signal rst_sys_62m5   : std_logic;
   signal rst_ref_125m_n : std_logic;
   signal clk_ref_125m   : std_logic;
   signal clk_ext_ref    : std_logic;

   -- I2C EEPROM
   signal eeprom_sda_in  : std_logic;
   signal eeprom_sda_out : std_logic;
   signal eeprom_scl_in  : std_logic;
   signal eeprom_scl_out : std_logic;

   -- SFP
   signal sfp_sda_in     : std_logic;
   signal sfp_sda_out    : std_logic;
   signal sfp_scl_in     : std_logic;
   signal sfp_scl_out    : std_logic;

   -- OneWire
   signal onewire_data   : std_logic;
   signal onewire_oe     : std_logic;

   -- LEDs and GPIO
   signal pps_out     : std_logic;
   signal pps_led     : std_logic;
   signal pps_ext_in  : std_logic;
   signal svec_led    : std_logic_vector(15 downto 0);
   signal wr2rf_led   : std_logic_vector(15 downto 0);
   signal fp_leds     : std_logic_vector(15 downto 0);
   signal wr_led_link : std_logic;
   signal wr_led_act  : std_logic;

   -- Wishbone buses
   signal wb_vme_out       : t_wishbone_master_out;
   signal wb_vme_in        : t_wishbone_master_in;
   signal wb_wrc_in        : t_wishbone_master_out;
   signal wb_wrc_out       : t_wishbone_master_in;
   signal wb_rf1_vtus_in   : t_wishbone_master_in;
   signal wb_rf1_vtus_out  : t_wishbone_master_out;
   signal wb_rf2_vtus_in   : t_wishbone_master_in;
   signal wb_rf2_vtus_out  : t_wishbone_master_out;
   signal wb_rf1_rfnco_in  : t_wishbone_master_in;
   signal wb_rf1_rfnco_out : t_wishbone_master_out;
   signal wb_rf2_rfnco_in  : t_wishbone_master_in;
   signal wb_rf2_rfnco_out : t_wishbone_master_out;

   -- VME
   signal vme_data_b_out    : std_logic_vector(15 downto 0);
   signal vme_data_b_out1   : std_logic_vector(31 downto 16);
   signal vme_addr_b_out    : std_logic_vector(31 downto 1);
   signal vme_lword_n_b_out : std_logic;
   signal vme_data_dir_int  : std_logic;
   signal vme_addr_dir_int  : std_logic;
   signal vme_addr_oe_n     : std_logic;
   signal vme_ga            : std_logic_vector(5 downto 0);
   signal vme_berr_n_o      : std_logic;
   signal vme_irq_n_o       : std_logic_vector(7 downto 1);
   signal vme_nogap         : std_logic;

   -------------------------------------------------------------------
   -- Signals to mimick WR2RF IO connectivity from wr2rf register core
   -------------------------------------------------------------------
   signal mmcm_locked       : std_logic;
   signal clk_sel           : std_logic;
   signal clk_sys_select    : std_logic;
   signal clk_sys_reset     : std_logic;
   signal wrcore_reset_n    : std_logic;
   signal iodelay_reset     : std_logic;
   signal mmcm_shift_incdec : std_logic;
   signal mmcm_shift_en     : std_logic;
   signal mmcm_shift_busy   : std_logic;

   -- timing_io
   signal tmg_clk_o          : std_logic_vector(2 downto 1);
   signal tmg_clk_oe_n_o     : std_logic_vector(2 downto 1);
   signal tmg_clk_term_en_o  : std_logic_vector(2 downto 1);
   signal tmg_io_o           : std_logic_vector(4 downto 1);
   signal tmg_io_oe_n_o      : std_logic_vector(4 downto 1);
   signal tmg_io_term_en_o   : std_logic_vector(4 downto 1);
   signal tmg_clk_oe_o       : std_logic_vector(2 downto 1);
   signal tmg_io_oe_o        : std_logic_vector(4 downto 1);

   signal ext_ref_dir_o      : std_logic;

   -- RF SPI
   signal dds_cs_n_o         : std_logic;
   signal rf1_iqdac_cs_n_o   : std_logic;
   signal rf2_iqdac_cs_n_o   : std_logic;
   signal rf_sclk_o          : std_logic;
   signal rf_sdi_o           : std_logic;
   signal rf_sdo_i           : std_logic;

   signal dds_profile_o      : std_logic_vector(2 downto 0);
   signal dds_ioupdate_o     : std_logic;
   signal dds_sync_error_i   : std_logic;
   signal dds_reset_o        : std_logic;

   signal pll_main_cs_n_o : std_logic;
   signal pll_main_sclk_o : std_logic;
   signal pll_main_sdi_o  : std_logic;
   signal pll_main_sdo_i  : std_logic;
   signal pll_main_stat_i : std_logic_vector(2 downto 1);
   signal pll_main_sync_o : std_logic;

   --  RF 1
   signal rf1_mux_sel_o        : std_logic_vector(1 downto 0);
   signal rf1_mixer_en_o       : std_logic;
   signal rf1_t1_delay_latch_o : std_logic;
   signal rf1_t1_delay_oen_o   : std_logic;
   signal rf1_t1_mux_sel_o     : std_logic;
   signal rf1_t2_delay_latch_o : std_logic;
   signal rf1_t2_delay_oen_o   : std_logic;
   signal rf1_t2_mux_sel_o     : std_logic;

   --  RF 2
   signal rf2_mux_sel_o        : std_logic_vector(1 downto 0);
   signal rf2_mixer_en_o       : std_logic;
   signal rf2_t1_delay_latch_o : std_logic;
   signal rf2_t1_delay_oen_o   : std_logic;
   signal rf2_t1_mux_sel_o     : std_logic;
   signal rf2_t2_delay_latch_o : std_logic;
   signal rf2_t2_delay_oen_o   : std_logic;
   signal rf2_t2_mux_sel_o     : std_logic;

   signal rf_delay_o           : std_logic_vector(9 downto 0);

   -- Firmware flash
   signal spi_flash_cs_n_o   : std_logic;
   signal spi_flash_miso_i   : std_logic;
   signal spi_flash_mosi_o   : std_logic;

   -- NCO logic
   signal loc_nco_azimuthal       : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_cabledelay      : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_hb              : std_logic_vector(9 downto 0);
   signal loc_nco_ctrl_reset      : std_logic;
   signal loc_nco_h1_ftw          : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_h1_prog         : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_update_valid    : std_logic;
   signal loc_or_wrs_params_sel   : std_logic;
   signal loc_nco_azimuthal_r     : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_cabledelay_r    : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_hb_r            : std_logic_vector(9 downto 0);
   signal loc_nco_ctrl_reset_r    : std_logic;
   signal loc_nco_h1_ftw_r        : std_logic_vector(c_FTW_size-1 downto 0);
   signal loc_nco_h1_prog_r       : std_logic_vector(c_FTW_size-1 downto 0);

   signal wrs_frame_valid         : std_logic;
   signal wrs_frame_counter       : unsigned(15 downto 0);
   signal wrs_nco_ctrl_reset      : std_logic;
   signal wrs_nco_h1_ftw          : std_logic_vector(c_FTW_size-1 downto 0);
   signal wrs_nco_h1_prog         : std_logic_vector(c_FTW_size-1 downto 0);
   signal wrs_frame_counter_r     : unsigned(15 downto 0);
   signal wrs_nco_ctrl_reset_r    : std_logic;
   signal wrs_nco_h1_ftw_r        : std_logic_vector(c_FTW_size-1 downto 0);
   signal wrs_nco_h1_prog_r       : std_logic_vector(c_FTW_size-1 downto 0);

   signal nco_azimuthal           : std_logic_vector(c_FTW_size-1 downto 0);
   signal nco_cabledelay          : std_logic_vector(c_FTW_size-1 downto 0);
   signal nco_hb                  : std_logic_vector(9 downto 0);
   signal nco_h1_ftw              : std_logic_vector(c_FTW_size-1 downto 0);
   signal nco_h1_prog             : std_logic_vector(c_FTW_size-1 downto 0);
   signal nco_reset               : std_logic;

   -- rf trigger mockup
   signal svec_mup_gpio_sel       : std_logic_vector(3 downto 0);
   signal svec_mup_led_sel        : std_logic_vector(3 downto 0);
   signal svec_mup_bclk_rfclk_sel : std_logic;
   signal svec_mup_ila_sel        : std_logic;
   signal svec_mup_rftrig_t1stop  : std_logic;
   signal svec_mup_rftrig_t1start : std_logic;
   signal svec_mup_rftrig_t2stop  : std_logic;
   signal svec_mup_rftrig_t2start : std_logic;
   signal svec_mup_fmc1_term      : std_logic_vector(5 downto 1);
   signal svec_mup_fmc2_term      : std_logic_vector(5 downto 1);
   signal svec_mup_fmc1_oe_n      : std_logic_vector(5 downto 1);
   signal svec_mup_fmc2_oe_n      : std_logic_vector(5 downto 1);
   signal svec_mup_fmc1_led       : std_logic_vector(1 downto 0);
   signal svec_mup_fmc2_led       : std_logic_vector(1 downto 0);

   signal reset_clk125       : std_logic;
   signal wr2rfsd_gpio       : std_logic_vector(3 downto 0);
   signal wr2rfsd_leds       : std_logic_vector(7 downto 0);
   signal wr2rfsd_ila        : std_logic_vector(127 downto 0);

   -- Misc
   signal ila_clk               : std_logic;
   signal ila_sigs              : std_logic_vector(127 downto 0);
   signal dbg_sigs              : std_logic_vector(127 downto 0);

   --  Streamer
   signal wrs_tx_data  : std_logic_vector(c_RF_streamer_data_width-1 downto 0);
   signal wrs_tx_valid : std_logic;
   signal wrs_tx_dreq  : std_logic;
   signal wrs_tx_last  : std_logic;
   signal wrs_tx_flush : std_logic;
   signal wrs_rx_data  : std_logic_vector(c_RF_streamer_data_width-1 downto 0);
   signal wrs_rx_valid : std_logic;
   signal wrs_rx_first : std_logic;
   signal wrs_rx_dreq  : std_logic;
   signal wrs_rx_last  : std_logic;

   signal pps           : std_logic;
   signal tm_link_up    : std_logic;
   signal tm_time_valid : std_logic;
   signal tm_tai        : std_logic_vector(39 downto 0);
   signal tm_cycles     : std_logic_vector(27 downto 0);

   -- RFFrameTransceiver
   signal rx_RFFrameHeader     : t_RFFrameHeader;
   signal rx_RFmFramePayloads  : t_RFmFramePayload;
   signal rx_RFsFramePayloads  : t_RFsFramePayload;
   signal rx_Frame_valid_pX    : std_logic;
   signal rx_Frame_typeID      : std_logic_vector(c_RFtype_ID_size-1 downto 0);
   signal tx_ready             : std_logic;
   signal tx_TransmitFrame_p1  : std_logic         := '0';
   signal tx_RFFrameHeader     : t_RFFrameHeader   := c_RFFrameHeader_zero;
   signal tx_RFmFramePayloads  : t_RFmFramePayload := c_RFmFramePayload_zero;
   signal tx_RFsFramePayloads  : t_RFsFramePayload := c_RFsFramePayload_zero;

   signal wb_rfframerxtx_in    : t_wishbone_master_in;
   signal wb_rfframerxtx_out   : t_wishbone_master_out;

   signal wb_dds_fpg_in        : t_wishbone_master_in;
   signal wb_dds_fpg_out       : t_wishbone_master_out;
   signal reset_on_pwr         : std_logic_vector(15 downto 0) := X"0000";
   signal was_areset_n_low     : std_logic := '0';

   attribute keep_hierarchy : string;
--   attribute keep_hierarchy of inst_vme_core           : label is "true";
--   attribute keep_hierarchy of inst_wr2rf_regs_core    : label is "true";
--   attribute keep_hierarchy of inst_rfframetransceiver : label is "true";
--   attribute keep_hierarchy of xwrc_board_svec         : label is "true";
   attribute keep_hierarchy of all                     : label is "true";

begin

   -- forced pwr on reset
   process(clk_20m_vcxo_i) is
   begin
      if (rising_edge(clk_20m_vcxo_i)) then
         reset_on_pwr <= '1' & reset_on_pwr(15 downto 1);
         if areset_n = '0' then
            was_areset_n_low <= '1';
         end if;
      end if;
   end process;
   
   -----------------------------------------------------------------------------
   -- System reset
   -----------------------------------------------------------------------------
   areset_n <= vme_sysreset_n_i and rst_n_i and reset_on_pwr(0);

   -----------------------------------------------------------------------------
   -- VME64x Core and buffers
   -----------------------------------------------------------------------------

   --  BERR and IRQ vme signals are inverted by the drivers. See schematics.
   vme_berr_o <= not vme_berr_n_o;
   vme_irq_o <= not vme_irq_n_o;

   inst_vme_core : entity work.xvme64x_core
      generic map (
         g_CLOCK_PERIOD    => 16,
         g_VME32           => False,
         g_ENABLE_CR_CSR   => false,
         g_USER_CSR_EXT    => false,
         g_WB_GRANULARITY  => BYTE,

         g_MANUFACTURER_ID => c_CERN_ID,
         g_BOARD_ID        => c_SVEC_ID,
         g_REVISION_ID     => c_SVEC_REVISION_ID,
         g_PROGRAM_ID      => c_SVEC_PROGRAM_ID,
         g_DECODER => (0      => (adem => x"fff00000", amcap => x"ee000000_00000000", dawpr => x"83"),
                       others => (adem => x"00000000", amcap => x"00000000_00000000", dawpr => x"83")) )
      port map (
         clk_i           => clk_sys_62m5,
         rst_n_i         => rst_sys_62m5_n,
         vme_i.as_n      => vme_as_n_i,
         vme_i.rst_n     => vme_sysreset_n_i,
         vme_i.write_n   => vme_write_n_i,
         vme_i.am        => vme_am_i,
         vme_i.ds_n      => vme_ds_n_i,
         vme_i.ga        => vme_ga,
         vme_i.lword_n   => vme_lword_n_b,
         vme_i.addr (23 downto 1)      => vme_addr_b (23 downto 1),
         vme_i.addr (31 downto 24)     => x"00",
         vme_i.data (15 downto 0)      => vme_data_b (15 downto 0),
         vme_i.data (31 downto 16) => x"0000",
         vme_i.iack_n    => vme_iack_n_i,
         vme_i.iackin_n  => vme_iackin_n_i,
         vme_o.berr_n    => vme_berr_n_o,
         vme_o.dtack_n   => vme_dtack_n_o,
         vme_o.retry_n   => vme_retry_n_o,
         vme_o.retry_oe  => vme_retry_oe_o,
         vme_o.lword_n   => vme_lword_n_b_out,
         vme_o.data (15 downto 0)      => vme_data_b_out,
         vme_o.data (31 downto 16)     => vme_data_b_out1,
         vme_o.addr      => vme_addr_b_out,
         vme_o.irq_n     => vme_irq_n_o,
         vme_o.iackout_n => vme_iackout_n_o,
         vme_o.dtack_oe  => vme_dtack_oe_o,
         vme_o.data_dir  => vme_data_dir_int,
         vme_o.data_oe_n => vme_data_oe_n_o,
         vme_o.addr_dir  => vme_addr_dir_int,
         vme_o.addr_oe_n => vme_addr_oe_n,
         wb_i   => wb_vme_in,
         wb_o   => wb_vme_out);

   vme_nogap <= not (vme_noga_n_i(0) xor vme_noga_n_i(1) xor vme_noga_n_i(2)
                     xor vme_noga_n_i(3) xor vme_noga_n_i(4));
   --  Use vme_ga_n_i if not unconnected (there are pull-up).
   --  Despite the name, the vme64x core want negated logic.
   vme_ga <= vme_gap_i & vme_ga_n_i when vme_ga_n_i /= (4 downto 0 => '1')
             else vme_nogap & vme_noga_n_i;

   -- VME tri-state buffers
   vme_data_b(15 downto 0)  <= vme_data_b_out               when vme_data_dir_int = '1' else (others => 'Z');
   vme_addr_b(23 downto 1)  <= (others => 'Z');--vme_addr_b_out(23 downto 1)  when vme_addr_dir_int = '1' else (others => 'Z');
   vme_lword_n_b            <= 'Z';

   vme_data_dir_o  <= vme_data_dir_int;
   vme_addr_dir_o  <= '0';
   vme_addr_oe_n_o <= vme_addr_oe_n;


   inst_wr2rf_regs_core: entity work.wr2rf_regs_core
      generic map (
         g_svec_mockup => true )
      port map (
         clk_sys_i   => clk_sys_62m5,
         rst_sys_n_i => rst_sys_62m5_n,
         clk_ref_i   => clk_ref_125m,
         rst_ref_n_i => rst_ref_125m_n,
         clk125_i    => clk_ref_125m,
         rst_clk125_n_i => rst_ref_125m_n,

         wb_vme_i => wb_vme_out,
         wb_vme_o => wb_vme_in,

         wb_wrc_i => wb_wrc_out,
         wb_wrc_o => wb_wrc_in,

         wb_rfframerxtx_i => wb_rfframerxtx_in,
         wb_rfframerxtx_o => wb_rfframerxtx_out,

         wb_dds_fpg_i     => wb_dds_fpg_in,
         wb_dds_fpg_o     => wb_dds_fpg_out,

         wb_rf1_vtus_i => wb_rf1_vtus_in,
         wb_rf1_vtus_o => wb_rf1_vtus_out,
         wb_rf2_vtus_i => wb_rf2_vtus_in,
         wb_rf2_vtus_o => wb_rf2_vtus_out,

         wb_rf1_rfnco_i => wb_rf1_rfnco_in,
         wb_rf1_rfnco_o => wb_rf1_rfnco_out,
         wb_rf2_rfnco_i => wb_rf2_rfnco_in,
         wb_rf2_rfnco_o => wb_rf2_rfnco_out,
         

         mmcm_locked_i    => mmcm_locked,
         clk_sel_o        => clk_sys_select,
         wrcore_reset_n_o => wrcore_reset_n,
         clk_sys_reset_o  => clk_sys_reset,
         iodelay_reset_o  => iodelay_reset,         

         mmcm_shift_incdec_o => mmcm_shift_incdec,
         mmcm_shift_en_o     => mmcm_shift_en,
         mmcm_shift_busy_i   => mmcm_shift_busy,

         tmg_clk_term_en_o => tmg_clk_term_en_o,
         tmg_io_term_en_o  => tmg_io_term_en_o,
         tmg_clk_oe_o      => tmg_clk_oe_o,
         tmg_io_oe_o       => tmg_io_oe_o,
         ext_ref_dir_o     => ext_ref_dir_o,

         dds_cs_n_o        => dds_cs_n_o,
         rf1_iqdac_cs_n_o  => rf1_iqdac_cs_n_o,
         rf2_iqdac_cs_n_o  => rf2_iqdac_cs_n_o,
         rf_sclk_o         => rf_sclk_o,
         rf_sdi_o          => rf_sdi_o,
         rf_sdo_i          => rf_sdo_i,
         
         pll_main_cs_n_o => pll_main_cs_n_o,
         pll_main_sclk_o => pll_main_sclk_o,
         pll_main_sdi_o  => pll_main_sdi_o,
         pll_main_sdo_i  => pll_main_sdo_i,

         pll_main_error_i  => pll_main_stat_i(1),
         pll_main_locked_i => pll_main_stat_i(2),
         pll_main_sync_o   => pll_main_sync_o,

         dds_reset_o      => dds_reset_o,
         dds_ioupdate_o   => dds_ioupdate_o,
         dds_profile_o    => dds_profile_o,
         dds_sync_error_i => dds_sync_error_i,

         ocxo_enabled_o   => open,
         ocxo_uptime_i => x"0000",
         
         wr2rfsd_nco_azimuthal_o  => loc_nco_azimuthal,
         wr2rfsd_nco_cabledelay_o => loc_nco_cabledelay,
         wr2rfsd_nco_hb_o         => loc_nco_hb,
         loc_nco_ctrl_reset_o     => loc_nco_ctrl_reset,
         loc_nco_h1_ftw_o         => loc_nco_h1_ftw,
         loc_nco_h1_prog_o        => loc_nco_h1_prog,
         loc_nco_update_valid_o   => loc_nco_update_valid,
         loc_or_wrs_params_sel_o  => loc_or_wrs_params_sel,

         svec_mup_gpio_sel_o       => svec_mup_gpio_sel,
         svec_mup_led_sel_o        => svec_mup_led_sel,
         svec_mup_bclk_rfclk_sel_o => svec_mup_bclk_rfclk_sel,
         svec_mup_ila_sel_o        => svec_mup_ila_sel,

         svec_mup_rftrig_t1stop_o  => svec_mup_rftrig_t1stop,
         svec_mup_rftrig_t1start_o => svec_mup_rftrig_t1start,
         svec_mup_rftrig_t2stop_o  => svec_mup_rftrig_t2stop,
         svec_mup_rftrig_t2start_o => svec_mup_rftrig_t2start,

         svec_mup_fmc1_term_o     => svec_mup_fmc1_term,
         svec_mup_fmc1_oe_n_o     => svec_mup_fmc1_oe_n,
         svec_mup_fmc1_led_o      => svec_mup_fmc1_led,
         svec_mup_fmc2_term_o     => svec_mup_fmc2_term,
         svec_mup_fmc2_oe_n_o     => svec_mup_fmc2_oe_n,
         svec_mup_fmc2_led_o      => svec_mup_fmc2_led,

         rf1_mux_sel_o        => rf1_mux_sel_o,
         rf1_mixer_en_o       => rf1_mixer_en_o,
         rf1_t1_delay_latch_o => rf1_t1_delay_latch_o,
         rf1_t1_delay_oen_o   => rf1_t1_delay_oen_o,
         rf1_t1_mux_sel_o     => rf1_t1_mux_sel_o,
         rf1_t2_delay_latch_o => rf1_t2_delay_latch_o,
         rf1_t2_delay_oen_o   => rf1_t2_delay_oen_o,
         rf1_t2_mux_sel_o     => rf1_t2_mux_sel_o,

         rf2_mux_sel_o        => rf2_mux_sel_o,
         rf2_mixer_en_o       => rf2_mixer_en_o,
         rf2_t1_delay_latch_o => rf2_t1_delay_latch_o,
         rf2_t1_delay_oen_o   => rf2_t1_delay_oen_o,
         rf2_t1_mux_sel_o     => rf2_t1_mux_sel_o,
         rf2_t2_delay_latch_o => rf2_t2_delay_latch_o,
         rf2_t2_delay_oen_o   => rf2_t2_delay_oen_o,
         rf2_t2_mux_sel_o     => rf2_t2_mux_sel_o,

         rf_delay_o   => rf_delay_o,

         flash_cs_n_o => spi_flash_cs_n_o,
         flash_miso_i => spi_flash_miso_i,
         flash_mosi_o => spi_flash_mosi_o,

         tm_tai_i        => tm_tai,
         tm_cycles_i     => tm_cycles,
         tm_linkup_i     => tm_link_up,
         tm_time_valid_i => tm_time_valid,

         pps_i           => pps);

   -- timing_io
   tmg_clk_oe_n_o  <= not tmg_clk_oe_o;
   tmg_io_oe_n_o   <= not tmg_io_oe_o;

   tmg_clk_o     <= "00";
   tmg_io_o      <= "0000";

   --  Note: use clk_ref.
   pps <= '1' when tm_time_valid = '1' and tm_cycles(27 downto 8) = x"00000" else '0';

   -----------------------------------------------------------------------------
   -- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
   -----------------------------------------------------------------------------

   cmp_xwrc_board_svec : entity work.xwrc_board_svec
      generic map (
         g_simulation                => g_simulation,
         g_with_external_clock_input => TRUE,
         g_dpram_initf               => g_dpram_initf,
         g_fabric_iface              => STREAMERS,
         g_streamers_op_mode         => TX_AND_RX,
         g_tx_streamer_params        => c_tx_streamer_params_RF,
         g_rx_streamer_params        => c_rx_streamer_params_RF)
      port map (
         clk_20m_vcxo_i      => clk_20m_vcxo_i,
         clk_125m_pllref_p_i => clk_125m_pllref_p_i,
         clk_125m_pllref_n_i => clk_125m_pllref_n_i,
         clk_125m_gtp_n_i    => clk_125m_gtp_n_i,
         clk_125m_gtp_p_i    => clk_125m_gtp_p_i,
         clk_10m_ext_i       => clk_ext_ref,
         areset_n_i          => areset_n,
         clk_sys_62m5_o      => clk_sys_62m5,
         clk_ref_125m_o      => clk_ref_125m,
         rst_sys_62m5_n_o    => rst_sys_62m5_n,
         rst_ref_125m_n_o    => rst_ref_125m_n,
         pll20dac_din_o      => pll20dac_din_o,
         pll20dac_sclk_o     => pll20dac_sclk_o,
         pll20dac_sync_n_o   => pll20dac_sync_n_o,
         pll25dac_din_o      => pll25dac_din_o,
         pll25dac_sclk_o     => pll25dac_sclk_o,
         pll25dac_sync_n_o   => pll25dac_sync_n_o,
         sfp_txp_o           => sfp_txp_o,
         sfp_txn_o           => sfp_txn_o,
         sfp_rxp_i           => sfp_rxp_i,
         sfp_rxn_i           => sfp_rxn_i,
         sfp_det_i           => sfp_mod_def0_i,
         sfp_sda_i           => sfp_sda_in,
         sfp_sda_o           => sfp_sda_out,
         sfp_scl_i           => sfp_scl_in,
         sfp_scl_o           => sfp_scl_out,
         sfp_rate_select_o   => sfp_rate_select_o,
         sfp_tx_fault_i      => sfp_tx_fault_i,
         sfp_tx_disable_o    => sfp_tx_disable_o,
         sfp_los_i           => sfp_los_i,
         eeprom_sda_i        => eeprom_sda_in,
         eeprom_sda_o        => eeprom_sda_out,
         eeprom_scl_i        => eeprom_scl_in,
         eeprom_scl_o        => eeprom_scl_out,
         onewire_i           => onewire_data,
         onewire_oen_o       => onewire_oe,
         uart_rxd_i          => uart_rxd_i,
         uart_txd_o          => uart_txd_o,
         spi_sclk_o          => spi_sclk_o,
         spi_ncs_o           => spi_ncs_o,
         spi_mosi_o          => spi_mosi_o,
         spi_miso_i          => spi_miso_i,

         wb_slave_o          => wb_wrc_out, --cnx_slave_out(c_WB_SLAVE_WRC),
         wb_slave_i          => wb_wrc_in, --cnx_slave_in(c_WB_SLAVE_WRC),

         --  Streamer
         wrs_tx_data_i       => wrs_tx_data,
         wrs_tx_valid_i      => wrs_tx_valid,
         wrs_tx_dreq_o       => wrs_tx_dreq,
         wrs_tx_last_i       => wrs_tx_last,
         wrs_tx_flush_i      => wrs_tx_flush,
         wrs_rx_first_o      => wrs_rx_first,
         wrs_rx_last_o       => wrs_rx_last,
         wrs_rx_data_o       => wrs_rx_data,
         wrs_rx_valid_o      => wrs_rx_valid,
         wrs_rx_dreq_i       => wrs_rx_dreq,
         wrs_tx_cfg_i        => c_tx_streamer_cfg_default,
         wrs_rx_cfg_i        => c_rx_streamer_cfg_default,

         tm_link_up_o        => tm_link_up,
         tm_time_valid_o     => tm_time_valid,
         tm_tai_o            => tm_tai,
         tm_cycles_o         => tm_cycles,

         pps_ext_i           => pps_ext_in,
         pps_p_o             => pps_out,
         pps_led_o           => pps_led,
         led_link_o          => wr_led_link,
         led_act_o           => wr_led_act );

   -- tri-state Carrier EEPROM
   carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
   eeprom_sda_in <= carrier_sda_b;
   carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
   eeprom_scl_in <= carrier_scl_b;

   -- Tristates for SFP EEPROM
   sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
   sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
   sfp_scl_in     <= sfp_mod_def1_b;
   sfp_sda_in     <= sfp_mod_def2_b;

   -- tri-state onewire access
   onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
   onewire_data <= onewire_b;


   -----------------------------------------------------------------------------
   -- Carrier front panel LEDs and LEMOs
   -----------------------------------------------------------------------------

   cmp_led_controller : entity work.gc_bicolor_led_ctrl
      generic map(
         g_nb_column    => 4,
         g_nb_line      => 2,
         g_clk_freq     => 62500000,                 -- in Hz
         g_refresh_rate => 250                       -- in Hz
         )
      port map(
         rst_n_i => rst_sys_62m5_n,
         clk_i   => clk_sys_62m5,

         led_intensity_i => "1100100",               -- in %

         led_state_i => fp_leds,

         column_o   => fp_led_column_o,
         line_o     => fp_led_line_o,
         line_oen_o => fp_led_line_oen_o);

   -- LED 1
   svec_led(1 downto 0) <= c_led_green when wr_led_link = '1' else c_led_off;

   -- LED 5
   svec_led(9 downto 8) <= c_led_red_green when wr_led_act = '1' else c_led_off;

   -- LED 8
   svec_led(15 downto 14) <= c_led_green when pps_led = '1' else c_led_off;

   -- unused LEDs
   svec_led(7 downto 2)   <= (others => '0');
   svec_led(13 downto 10) <= (others => '0');


   -- wr2rfsd LED drivers...
   wr2rf_led(1  downto  0) <= c_led_green when wr2rfsd_leds(3) = '1' else c_led_off;
   wr2rf_led(3  downto  2) <= c_led_green when wr2rfsd_leds(2) = '1' else c_led_off;
   wr2rf_led(5  downto  4) <= c_led_green when wr2rfsd_leds(1) = '1' else c_led_off;
   wr2rf_led(7  downto  6) <= c_led_green when wr2rfsd_leds(0) = '1' else c_led_off;
   wr2rf_led(9  downto  8) <= c_led_red_green when wr2rfsd_leds(7) = '1' else c_led_off;
   wr2rf_led(11 downto 10) <= c_led_green when wr2rfsd_leds(6) = '1' else c_led_off;
   wr2rf_led(13 downto 12) <= c_led_green when wr2rfsd_leds(5) = '1' else c_led_off;
   wr2rf_led(15 downto 14) <= c_led_green when wr2rfsd_leds(4) = '1' else c_led_off;

   fp_leds <= svec_led when svec_mup_led_sel(0) /= '0' else wr2rf_led;

   -----------------------------------------------------------------
   -- wiring for svec_wr2rf_vme mockup
   -----------------------------------------------------------------

   mmcm_locked  <= rst_sys_62m5_n;

   dbg_sigs(0)  <= clk_sel;
   dbg_sigs(1)  <= clk_sys_reset;
   dbg_sigs(2)  <= mmcm_shift_incdec;
   dbg_sigs(3)  <= mmcm_shift_en;
   dbg_sigs(4)  <= mmcm_shift_busy;
   dbg_sigs(5)  <= wrcore_reset_n;
   dbg_sigs(6)  <= iodelay_reset;
   dbg_sigs(7)  <= '0';
   
   dbg_sigs(8)  <= wb_vme_out.stb;
   dbg_sigs(9)  <= wb_vme_out.we;
   dbg_sigs(10) <= wb_vme_out.cyc;
   dbg_sigs(11) <= wb_vme_in.ack;
   dbg_sigs(12) <= wb_vme_in.stall;
   dbg_sigs(15 downto 13) <= wb_vme_out.adr(3 downto 1);

   dbg_sigs(16) <= clk_20m_vcxo_i;
   dbg_sigs(17) <= areset_n;
   dbg_sigs(18) <= wb_wrc_in.stb;
   dbg_sigs(19) <= wb_wrc_out.ack;
   
   --dbg_sigs(16) <= wrcore_reset_n;
   --dbg_sigs(17) <= iodelay_reset;
   --dbg_sigs(18) <= svec_mup_gpio_sel(0);
   --dbg_sigs(19) <= loc_or_wrs_params_sel;
   dbg_sigs(20) <= loc_nco_update_valid;
   dbg_sigs(21) <= nco_reset;
   dbg_sigs(22) <= loc_nco_ctrl_reset_r;
   dbg_sigs(23) <= loc_nco_ctrl_reset;
   
--   dbg_sigs(16) <= dds_cs_n_o;
--   dbg_sigs(17) <= rf1_iqdac_cs_n_o;
--   dbg_sigs(18) <= rf2_iqdac_cs_n_o;
--   dbg_sigs(19) <= rf_sclk_o;
--   dbg_sigs(20) <= rf_sdi_o;
--   dbg_sigs(21) <= rf_sdo_i;
--   dbg_sigs(23 downto 22) <= (others => '0');

   dbg_sigs(24)  <= pll_main_cs_n_o;
   dbg_sigs(25)  <= pll_main_sclk_o;
   dbg_sigs(26)  <= pll_main_sdi_o;
   dbg_sigs(27)  <= pll_main_sdo_i;
   dbg_sigs(28)  <= pll_main_sync_o;
   dbg_sigs(29)  <= loc_or_wrs_params_sel;
   dbg_sigs(30)  <= loc_nco_update_valid;
   dbg_sigs(31)  <= nco_reset;

   --dbg_sigs(32) <= rf1_mux_sel_o(0);
   --dbg_sigs(33) <= rf1_mixer_en_o;
   --dbg_sigs(34) <= rf1_t1_delay_latch_o;
   --dbg_sigs(35) <= rf1_t1_delay_oen_o;
   --dbg_sigs(36) <= rf1_t1_mux_sel_o;
   --dbg_sigs(37) <= rf1_t2_delay_latch_o;
   --dbg_sigs(38) <= rf1_t2_delay_oen_o;
   --dbg_sigs(39) <= rf1_t2_mux_sel_o;

   --dbg_sigs(40) <= rf2_mux_sel_o(0);
   --dbg_sigs(41) <= rf2_mixer_en_o;
   --dbg_sigs(42) <= rf2_t1_delay_latch_o;
   --dbg_sigs(43) <= rf2_t1_delay_oen_o;
   --dbg_sigs(44) <= rf2_t1_mux_sel_o;
   --dbg_sigs(45) <= rf2_t2_delay_latch_o;
   --dbg_sigs(46) <= rf2_t2_delay_oen_o;
   --dbg_sigs(47) <= rf2_t2_mux_sel_o;
   dbg_sigs(47 downto 32) <= wb_vme_out.adr(15 downto 0);
   
   dbg_sigs(48) <= rf1_mux_sel_o(1);
   dbg_sigs(49) <= rf2_mux_sel_o(1);
   dbg_sigs(50) <= spi_flash_cs_n_o;
   dbg_sigs(51) <= spi_flash_miso_i;
   dbg_sigs(52) <= spi_flash_mosi_o;
   dbg_sigs(55  downto 53) <= (others => '0');

   dbg_sigs(57 downto 56)  <= tmg_clk_term_en_o;
   dbg_sigs(59 downto 58)  <= tmg_clk_oe_o;
   dbg_sigs(63 downto 60)  <= tmg_io_term_en_o;
   dbg_sigs(67 downto 64)  <= tmg_io_oe_o;
   dbg_sigs(68)            <= ext_ref_dir_o;
   dbg_sigs(69)            <= '0';
   dbg_sigs(79 downto 70)   <= rf_delay_o;
   dbg_sigs(87 downto 80)   <= wr2rfsd_leds;

   -- some vme signals
   dbg_sigs(99  downto 92)  <= vme_addr_b(23 downto 16);
   dbg_sigs(105 downto 100) <= vme_am_i;
   dbg_sigs(106)            <= vme_data_dir_int;
   dbg_sigs(107)            <= vme_addr_dir_int;
   dbg_sigs(108)            <= vme_write_n_i;
   dbg_sigs(109)            <= vme_sysreset_n_i;
   dbg_sigs(110)            <= vme_as_n_i;
   dbg_sigs(111)            <= vme_addr_oe_n;
   dbg_sigs(127 downto 112) <= vme_data_b;

--   ila_sigs <= dbg_sigs     when svec_mup_ila_sel /= '0' else wr2rfsd_ila;

--   bclk_pll_buf : bufgmux
--      generic map (
--         clk_sel_type => "ASYNC" )
--      port map (
--         o  => ila_clk,
--         i0 => clk_sys_62m5,
--         i1 => clk_ref_125m,
--         s  => svec_mup_ila_sel );

   --ila_sigs <= wr2rfsd_ila;
   --ila_clk  <= clk_ref_125m;
   ila_sigs  <= dbg_sigs;
   ila_clk   <= clk_sys_62m5;

   ila_i : entity work.ila
      generic map (
         ila_en      => true )
      port map (
         clk0        => ila_clk,
         ila0        => ila_sigs );

   dds_sync_error_i <= '0';

   -- loopbacks
   spi_flash_miso_i <= spi_flash_mosi_o;
   pll_main_sdo_i   <= pll_main_sdi_o;
   rf_sdo_i         <= rf_sdi_o;
   mmcm_shift_busy  <= mmcm_shift_en;

   -- WR2RF datapath
    inst_RFFrameTransceiver : entity work.RFFrameTransceiver
        port map(
            clk_i                  => clk_sys_62m5,
            rst_n_i                => rst_sys_62m5_n,

            tx_data_o              => wrs_tx_data,
            tx_valid_o             => wrs_tx_valid,
            tx_dreq_i              => wrs_tx_dreq,
            tx_last_p1_o           => wrs_tx_last,
            tx_flush_p1_o          => wrs_tx_flush,
            rx_data_i              => wrs_rx_data,
            rx_valid_i             => wrs_rx_valid,
            rx_first_p1_i          => wrs_rx_first,
            rx_dreq_o              => wrs_rx_dreq,
            rx_last_p1_i           => wrs_rx_last,

            rx_RFFrameHeader_o     => rx_RFFrameHeader,
            rx_RFmFramePayloads_o  => rx_RFmFramePayloads,
            rx_RFsFramePayloads_o  => rx_RFsFramePayloads,
            rx_Frame_valid_pX_o    => rx_Frame_valid_pX,
            rx_Frame_typeID_o      => rx_Frame_typeID,

            ready_o                => tx_ready,
            tx_TransmitFrame_p1_i  => tx_TransmitFrame_p1,
            tx_RFFrameHeader_i     => tx_RFFrameHeader,
            tx_RFmFramePayloads_i  => tx_RFmFramePayloads,
            tx_RFsFramePayloads_i  => tx_RFsFramePayloads,

            wb_slave_i             => wb_rfframerxtx_out,
            wb_slave_o             => wb_rfframerxtx_in );

   wrs_frame_valid    <= '1' when rx_Frame_valid_pX = '1' and rx_Frame_typeID = c_ID_RFmFrame else '0';
   wrs_frame_counter  <= wrs_frame_counter_r + 1         when wrs_frame_valid = '1' else wrs_frame_counter_r;
   wrs_nco_ctrl_reset <= rx_RFmFramePayloads.control(0)  when wrs_frame_valid = '1' else wrs_nco_ctrl_reset_r;
   wrs_nco_h1_ftw     <= rx_RFmFramePayloads.FTW_H1_main when wrs_frame_valid = '1' else wrs_nco_h1_ftw_r;
   wrs_nco_h1_prog    <= rx_RFmFramePayloads.FTW_H1_prog when wrs_frame_valid = '1' else wrs_nco_h1_prog_r;

   process (clk_ref_125m)
   begin
      if rising_edge (clk_ref_125m) then
         if rst_ref_125m_n = '0' then
            wrs_frame_counter_r  <= (others => '0');
            wrs_nco_ctrl_reset_r <= '1';
            wrs_nco_h1_ftw_r     <= (others => '0');
            wrs_nco_h1_prog_r    <= (others => '0');
            loc_nco_azimuthal_r  <= (others => '0');
            loc_nco_cabledelay_r <= (others => '0');
            loc_nco_hb_r         <= "11" & X"9c";
            loc_nco_h1_ftw_r     <= X"001687012c84";
            loc_nco_h1_prog_r    <= (others => '0');
            loc_nco_ctrl_reset_r <= '1';
         else
            wrs_frame_counter_r    <= wrs_frame_counter;
            wrs_nco_ctrl_reset_r   <= wrs_nco_ctrl_reset;
            wrs_nco_h1_ftw_r       <= wrs_nco_h1_ftw;
            wrs_nco_h1_prog_r      <= wrs_nco_h1_prog;
            if (loc_nco_update_valid = '1') then
               loc_nco_azimuthal_r  <= loc_nco_azimuthal;
               loc_nco_cabledelay_r <= loc_nco_cabledelay;
               loc_nco_hb_r         <= loc_nco_hb;
               loc_nco_h1_ftw_r     <= loc_nco_h1_ftw;
               loc_nco_h1_prog_r    <= loc_nco_h1_prog;
               loc_nco_ctrl_reset_r <= loc_nco_ctrl_reset;
            end if;
         end if;
      end if;
   end process;

   process (clk_ref_125m)
   begin
      if rising_edge(clk_ref_125m) then
         if (rst_sys_62m5_n = '0') then
            reset_clk125 <= '1';
         else
            reset_clk125 <= '0';
         end if;
      end if;
   end process;

   -- use wr2rf-sd core to check delivery of FTW over WRS or via local register map
   -- configuration parameters - source is local regmap
   nco_hb         <= loc_nco_hb_r;
   nco_cabledelay <= loc_nco_cabledelay_r;
   nco_azimuthal  <= loc_nco_azimuthal_r;
   -- dynamic parameters - source can be wrs or local regmap
   nco_reset      <= loc_nco_ctrl_reset_r when loc_or_wrs_params_sel = '1' else wrs_nco_ctrl_reset;
   nco_h1_ftw     <= loc_nco_h1_ftw_r     when loc_or_wrs_params_sel = '1' else wrs_nco_h1_ftw;
   nco_h1_prog    <= loc_nco_h1_prog_r    when loc_or_wrs_params_sel = '1' else wrs_nco_h1_prog;

   wr2rfsd_i : entity work.wr2rfsd_svec
      port map (
         clk125_i           => clk_ref_125m,
         reset_clk125_i     => reset_clk125,

         nco_hb_i           => nco_hb,
         nco_cabledel_i     => nco_cabledelay,
         nco_azimuthal_i    => nco_azimuthal,
         nco_lvl2_en_i      => '0',

         nco_reset_i        => nco_reset,
         nco_h1_ftw_i       => nco_h1_ftw,
         nco_h1_phase_adj_i => nco_h1_prog,

         bclk_rfclk_sel_i   => svec_mup_bclk_rfclk_sel,
         gpio_io            => wr2rfsd_gpio,
         frev_p_b           => frev_p_b,
         frev_n_b           => frev_n_b,
         bclk_p_b           => bclk_p_b,
         bclk_n_b           => bclk_n_b,
         leds_o             => wr2rfsd_leds,
         dbg_o              => wr2rfsd_ila );

   -- front panel
   fp_gpio1_o      <= pll_main_sclk_o when svec_mup_gpio_sel(0) /= '0' else wr2rfsd_gpio(0);
   fp_gpio2_o      <= pll_main_sdi_o  when svec_mup_gpio_sel(0) /= '0' else wr2rfsd_gpio(1);
   fp_gpio3_o      <= pll_main_cs_n_o when svec_mup_gpio_sel(0) /= '0' else pps;
   fp_gpio4_o      <= vme_as_n_i      when svec_mup_gpio_sel(0) /= '0' else wr2rfsd_gpio(3);
   fp_term_en_o    <= (others => '0');
   fp_gpio1_a2b_o  <= '1';
   fp_gpio2_a2b_o  <= '1';
   fp_gpio34_a2b_o <= '1';

   rftrig_b : block is

      signal rf1_t1_clk_p_i : std_logic;
      signal rf1_t1_clk_n_i : std_logic;
      signal rf1_t1_start_i : std_logic;
      signal rf1_t1_stop_i  : std_logic;
      signal rf1_t1_sync_i  : std_logic;
      signal rf1_t1         : std_logic;

      signal rf1_t2_clk_p_i : std_logic;
      signal rf1_t2_clk_n_i : std_logic;
      signal rf1_t2_start_i : std_logic;
      signal rf1_t2_stop_i  : std_logic;
      signal rf1_t2_sync_i  : std_logic;
      signal rf1_t2         : std_logic;

      signal rf1_t1_sync_r  : std_logic;
      signal rf1_t2_r       : std_logic;
      signal rf1_t2_sync_r  : std_logic;

      signal rf1_clk_bufg   : std_logic;
      signal rf1_clk_bufg_r : std_logic;

      signal fmc1_dio_i     : std_logic_vector(5 downto 1);
      signal fmc2_dio_i     : std_logic_vector(5 downto 1);

      -- Trigger out (on fmc_dio_o(0) is driven directly
      signal fmc1_dio_o     : std_logic_vector(5 downto 1);
      signal fmc2_dio_o     : std_logic_vector(5 downto 1);

   begin
      -- rf trigger unit mockup
      fmc1_dio_oe_n_o    <= svec_mup_fmc1_oe_n;
      fmc1_dio_term_en_o <= svec_mup_fmc1_term;
      fmc2_dio_oe_n_o    <= svec_mup_fmc2_oe_n;
      fmc2_dio_term_en_o <= svec_mup_fmc2_term;

      -- differential io buffers
      fmc_dio_i_g : for i in 1 to 5 generate
      begin
         ibufds_fmc1_i : ibufds
            port map (
               I   => fmc1_dio_p_i(i),
               IB  => fmc1_dio_n_i(i),
               O   => fmc1_dio_i(i) );
         ibufds_fmc2_i : ibufds
            port map (
               I   => fmc2_dio_p_i(i),
               IB  => fmc2_dio_n_i(i),
               O   => fmc2_dio_i(i) );
      end generate;

      fmc_dio_o_g : for i in 1 to 5 generate
      begin
         obufds_fmc1_i : obufds
            port map (
               O   => fmc1_dio_p_o(i),
               OB  => fmc1_dio_n_o(i),
               I   => fmc1_dio_o(i) );
         obufds_fmc2_i : obufds
            port map (
               O   => fmc2_dio_p_o(i),
               OB  => fmc2_dio_n_o(i),
               I   => fmc2_dio_o(i) );
      end generate;

      process (rf1_clk_bufg) is
      begin
         if rising_edge(rf1_clk_bufg) then
            rf1_t1_sync_r <= rf1_t1_sync_i;
            --rf1_t1_r      <= rf1_t1;
            rf1_t2_sync_r <= rf1_t2_sync_i;
            rf1_t2_r      <= rf1_t2;
            rf1_clk_bufg_r <= not rf1_clk_bufg_r;
         end if;
      end process;

      rst_sys_62m5       <= not rst_sys_62m5_n;

      rf1_t1_clk_p_i     <= fmc1_dio_clk_p_i;
      rf1_t1_clk_n_i     <= fmc1_dio_clk_n_i;
      fmc1_dio_o(3)      <= rf1_t1;
      rf1_t1_start_i     <= svec_mup_rftrig_t1start;
      rf1_t1_stop_i      <= svec_mup_rftrig_t1stop;
      rf1_t1_sync_i      <= fmc1_dio_i(4);

      fmc1_dio_o(2)      <= fmc1_dio_i(1);
      fmc1_dio_led_bot_o <= svec_mup_fmc1_led(0);
      fmc1_dio_led_top_o <= fmc1_dio_i(1);--svec_mup_fmc1_led(1);

      rf1_t2_clk_p_i     <= fmc2_dio_clk_p_i;
      rf1_t2_clk_n_i     <= fmc2_dio_clk_n_i;
      fmc2_dio_o(2)      <= rf1_t2;
      rf1_t2_start_i     <= svec_mup_rftrig_t2start;
      rf1_t2_stop_i      <= svec_mup_rftrig_t2stop;
      rf1_t2_sync_i      <= fmc2_dio_i(1);

      fmc2_dio_o(4)      <= fmc2_dio_i(3);
      fmc2_dio_led_bot_o <= svec_mup_fmc2_led(0);
      fmc2_dio_led_top_o <= fmc2_dio_i(3);--svec_mup_fmc2_led(1);

      dbg_sigs(88)             <= rf1_t1_sync_r;
      dbg_sigs(89)             <= svec_mup_rftrig_t1start;
      dbg_sigs(90)             <= svec_mup_rftrig_t1stop;
      dbg_sigs(91)             <= rf1_clk_bufg_r;
      
      -- we only have one rf channel with trigger units on svec mockup
      svec_wr2rf_rftrigger_i : entity work.svec_wr2rf_rftrigger
         port map (
            clk_sys_i         => clk_sys_62m5,
            rst_sys_i         => rst_sys_62m5,

            clk_refclk_200m_i => '0',

            wb_i              => wb_rf1_vtus_out, --
            wb_o              => wb_rf1_vtus_in, --

            rf_t1_sync_i      => rf1_t1_sync_i,
            --rf_sync_p_o       => rf1_sync_p_o,
            --rf_sync_n_o       => rf1_sync_n_o,

            rf_t1_clk_p_i     => rf1_t1_clk_p_i,--
            rf_t1_clk_n_i     => rf1_t1_clk_n_i,--
            --rf_t1_p_o         => rf1_t1_p_o,--
            --rf_t1_n_o         => rf1_t1_n_o,--
            rf_t1_o           => rf1_t1,
            rf_t1_rst_p_o     => open,--rf_t1_rst_p_o,
            rf_t1_rst_n_o     => open, --rf_t1_rst_n_o,
            rf_t1_start_i     => rf1_t1_start_i, --
            rf_t1_stop_i      => rf1_t1_stop_i, --

            rf_t2_sync_i      => rf1_t2_sync_i,
            rf_t2_clk_p_i     => rf1_t2_clk_p_i, --
            rf_t2_clk_n_i     => rf1_t2_clk_n_i, --
            --rf_t2_p_o         => rf1_t2_p_o, --
            --rf_t2_n_o         => rf1_t2_n_o, --
            rf_t2_o           => rf1_t2,
            rf_t2_rst_p_o     => open, --rf_t2_rst_p_o,
            rf_t2_rst_n_o     => open, --rf_t2_rst_n_o,
            rf_t2_start_i     => rf1_t2_start_i,--
            rf_t2_stop_i      => rf1_t2_stop_i,--

            rf_clk_bufg_o     => rf1_clk_bufg );

   end block;

end rtl;
