--------------------------------------------------------------------------------
-- CERN BE-CO-HT
--
-- https://www.ohwr.org/projects/wr2rf-vme
--------------------------------------------------------------------------------
--
-- unit name:   wr2rf_rftrigger
--
-- description: Provides clock architecture wrapper for VTU
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.wishbone_pkg.all;

entity wr2rf_rftrigger is

    port (
        --  System clock (125Mhz or 62.5Mhz)
        clk_sys_i     : in  std_logic;
        clk125m_i     : in  std_logic;
        clk500m_i     : in  std_logic;

        --  Systen reset clock (> 50ns)
        rst_sys_n_i   : in  std_logic;
        rst_sys_i     : in  std_logic;
        rst_clk125m_i : in  std_logic;

        --  Reference clock for io delays
        clk_refclk_200m_i : in std_logic;
        iodelay_reset_i   : in std_logic;

        --  Wishbone interface, uses clk_sys.
        wb_i       : in    t_wishbone_slave_in;
        wb_o       : out   t_wishbone_slave_out;

        -- TAI
        tm_tai_i      : in  std_logic_vector(39 downto 0);
        tm_cycles_i   : in  std_logic_vector(27 downto 0);

        --  Pulse from the Reset/sync logic.
        rf_t1_sync_i         : in    std_logic;
        rf_t1_sync_p_o       : inout std_logic;
        rf_t1_sync_n_o       : inout std_logic;

        -- RF reset due nco_reset + programmable t1_sync delay
        -- Programmable delay signals for the sync pulse into trigger unit 1
        rf_t1_sync_cdelay_i     : in  std_logic_vector(6 downto 0);
        rf_t1_sync_fdelay_i     : in  std_logic_vector(3 downto 0);
        rf_t1_sync_odelay_i     : in  std_logic_vector(4 downto 0);
        rf_rst_cdelay_offset_i  : in  std_logic_vector(6 downto 0);
        rf_nco_reset_cdelayed_o : out std_logic;
        rf_rst_o                : out std_logic;

        rf_t1_clk_p_i     : in  std_logic;
        rf_t1_clk_n_i     : in  std_logic;
        rf_t1_p_o         : inout std_logic;
        rf_t1_n_o         : inout std_logic;
        rf_t1_rst_i       : in  std_logic;
        rf_t1_rst_p_o     : out std_logic;
        rf_t1_rst_n_o     : out std_logic;
        rf_t1_start_i     : in  std_logic; --  Asynchronous tmg inputs.
        rf_t1_stop_i      : in  std_logic; --  Asynchronous tmg inputs.

        rf_t2_clk_p_i     : in  std_logic;
        rf_t2_clk_n_i     : in  std_logic;
        rf_t2_p_o         : inout std_logic;
        rf_t2_n_o         : inout std_logic;
        rf_t2_rst_i       : in  std_logic;
        rf_t2_rst_p_o     : out std_logic;
        rf_t2_rst_n_o     : out std_logic;
        rf_t2_start_i     : in  std_logic; --  Asynchronous tmg inputs.
        rf_t2_stop_i      : in  std_logic; --  Asynchronous tmg inputs.

        rf_t1_softstart_o : out std_logic;
        rf_t2_softstart_o : out std_logic;
        rf_t1_softstop_o  : out std_logic;
        rf_t2_softstop_o  : out std_logic;

        rf_t1_vtu_start_p_o : out std_logic;
        rf_t2_vtu_start_p_o : out std_logic;

        rf_clk_bufg_o     : out std_logic;

        rf_ila_dbg_o      : out std_logic_vector(31 downto 0) );

    attribute keep_hierarchy                    : STRING;
    attribute keep_hierarchy of wr2rf_rftrigger : entity is "yes";
    attribute shreg_extract                     : STRING;
    attribute shreg_extract of wr2rf_rftrigger  : entity is "no";

end entity;

architecture rtl of wr2rf_rftrigger is
  signal rf_clk_in   : std_logic;
  signal clk_rf      : std_logic;

  signal rf_clk_io  : std_logic;
  signal clk_vtu    : std_logic;
  signal clk_vtu_x2 : std_logic;
  signal rf_idelay_rdy : std_logic;

  signal rf_t1_out : std_logic;
  signal rf_t1_fb : std_logic;

  signal rf_t2_out : std_logic;

  signal rst_sys_n_r : std_logic;
  signal rst_sys_r   : std_logic;

  signal t1_wb_in : t_wishbone_slave_in;
  signal t1_wb_out : t_wishbone_slave_out;

  signal t2_wb_in : t_wishbone_slave_in;
  signal t2_wb_out : t_wishbone_slave_out;

  signal diag_rf_window : std_logic_vector (2 downto 0);
  signal diag_rf_enable : std_logic;
  signal diag_rf_freq : std_logic_vector (31 downto 0);
  signal diag_rf_generation : std_logic_vector (15 downto 0);
  signal diag_rf_counter : std_logic_vector (31 downto 0);


  -- RF input clock glitches after an NCO reset gate-out this period of
  -- unstable RF
  signal rf_activated   : std_logic;
  signal rf_activated_r : std_logic;
  signal rst_rf         : std_logic;
  signal rst_rf_r       : std_logic;
  signal rst_rf_cnt     : unsigned(6 downto 0);
  signal rst_rf_cnt_r   : unsigned(6 downto 0);
  signal sync_serdes_tristate : std_logic;
  signal async_cdc_rst_rf_n_r : std_logic;
  signal cdc_rst_rf_n_r       : std_logic;
  signal cdc_rst_rf_n_h       : std_logic;
  signal t1_rst_rf_n_r        : std_logic;
  signal t2_rst_rf_n_r        : std_logic;

  -- programmable sync
  signal rf_t1_sync_fdelay_r : std_logic_vector(3  downto 0);
  signal t1_sync_cdelay      : std_logic_vector(127 downto 0);
  signal t1_sync_cdelay_r    : std_logic_vector(127 downto 0);
  signal t1_sync_cdelayed    : std_logic;
  signal t1_sync_cdelayed_r  : std_logic;
  signal t1_sync_cdelayed_h  : std_logic;
  signal t1_sync_cdelayed_hh : std_logic;
  signal t1_sync_cdelayed_hhh : std_logic;
  signal t1_sync_pattern    : std_logic_vector(23 downto 0);
  signal t1_sync_pattern_r  : std_logic_vector(23 downto 0);

  signal t1_sync_fdelay     : std_logic_vector(7  downto 0);
  signal t1_sync_fdelay_r   : std_logic_vector(7  downto 0);
  signal t1_sync_fdelayed   : std_logic;
  signal t1_sync_odelayed   : std_logic;
  signal rf_sync_fb         : std_logic;

  signal rf_t1_sync_x8_fb : std_logic_vector(7 downto 0);
  signal bufr_clr         : std_logic;
  signal clk_rf_special   : std_logic;
  signal t1_rst_rf_n_h : std_logic;
  signal t2_rst_rf_n_h : std_logic;
  signal t1_rst_vtu_pulse : std_logic;
  signal t2_rst_vtu_pulse : std_logic;
  signal t1_rst_vtu_pulse_r : std_logic;
  signal t2_rst_vtu_pulse_r : std_logic;


  attribute async_reg  : string;
  attribute async_reg  of async_cdc_rst_rf_n_r : signal is "true";
  attribute async_reg  of cdc_rst_rf_n_r       : signal is "true";
  attribute async_reg  of cdc_rst_rf_n_h       : signal is "true";

  attribute max_fanout                   : integer;
  attribute max_fanout of t1_rst_rf_n_r  : signal is 8;
  attribute max_fanout of t2_rst_rf_n_r  : signal is 8;
  attribute keep                         : string;
  attribute keep       of t1_rst_rf_n_r  : signal is "true";
  attribute keep       of t2_rst_rf_n_r  : signal is "true";

begin
  --  Clock.
  inst_rf_clk_IBUFDS: IBUFDS
    generic map (
      DIFF_TERM    => FALSE, --Differential Termination
      IBUF_LOW_PWR => TRUE,  --Lowpower (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD   => "DEFAULT")
    port map(
      O  => rf_clk_in,
      I  => rf_t1_clk_p_i,
      IB => rf_t1_clk_n_i);

  --  Distribute to the I/Os for serdes.
  inst_rf_clk_io_BUFIO: BUFIO
    port map (
      O => rf_clk_io,
      I => rf_clk_in );

  -- Sync nco_reset into the RF clk domain
  process (clk_rf_special, rst_rf_r) is
  begin
     if rst_rf_r = '1' then
        async_cdc_rst_rf_n_r <= '0';
        cdc_rst_rf_n_r       <= '0';
        cdc_rst_rf_n_h       <= '0';
     elsif rising_edge (clk_rf_special) then
        async_cdc_rst_rf_n_r <= '1';
        cdc_rst_rf_n_r       <= async_cdc_rst_rf_n_r;
        cdc_rst_rf_n_h       <= cdc_rst_rf_n_r;
     end if;
  end process;

  bufr_clr <= '1' when cdc_rst_rf_n_h = '0' and cdc_rst_rf_n_r = '1' else '0';

  process (clk_vtu) is
  begin
     if rising_edge (clk_vtu) then
        t1_rst_rf_n_r       <= cdc_rst_rf_n_h;
        t1_rst_rf_n_h       <= t1_rst_rf_n_r;
        t2_rst_rf_n_r       <= cdc_rst_rf_n_h;
        t2_rst_rf_n_h       <= t2_rst_rf_n_r;
        t1_rst_vtu_pulse_r  <= t1_rst_vtu_pulse;
        t2_rst_vtu_pulse_r  <= t2_rst_vtu_pulse;
     end if;
  end process;

  t1_rst_vtu_pulse <= '1' when t1_rst_rf_n_h = '0' and t1_rst_rf_n_r = '1' else '0';
  t2_rst_vtu_pulse <= '1' when t2_rst_rf_n_h = '0' and t2_rst_rf_n_r = '1' else '0';

  --  Distribute to the region for logic (vtu).  Note: divided by 8.
  inst_rf_clkdiv8_BUFR: BUFR
    generic map (
      BUFR_DIVIDE => "8",
      SIM_DEVICE  => "7SERIES")
    port map (
      O   => clk_vtu,
      CE  => '1',--cdc_rst_rf_n_h,
      CLR => bufr_clr,
      I   => rf_clk_in );

  inst_rf_clkdiv4_BUFR: BUFR
    generic map (
      BUFR_DIVIDE => "4",
      SIM_DEVICE  => "7SERIES")
    port map (
      O   => clk_vtu_x2,
      CE  => '1',--cdc_rst_rf_n_r,
      CLR => bufr_clr,
      I   => rf_clk_in );

  inst_rf_clk_BUFR: BUFR
    generic map (
      BUFR_DIVIDE => "1",
      SIM_DEVICE  => "7SERIES")
    port map (
      O   => clk_rf,
      CE  => '1',--cdc_rst_rf_n_r,
      CLR => bufr_clr,
      I   => rf_clk_in );

  inst_rf_clk_special_BUFR: BUFR
    generic map (
      BUFR_DIVIDE => "1",
      SIM_DEVICE  => "7SERIES")
    port map (
      O   => clk_rf_special,
      CE  => '1',--cdc_rst_rf_n_r,
      CLR => '0',
      I   => rf_clk_in );

  -- The RF sync signal into the trigger unit has a programmable delay
  -- It consists of a coarse delay circuit which is just a delayed nco_reset
  -- for sys clock cycles (16 ns). Then we use an oserdes block to delay the output
  -- with finer precision (1 ns). There are some odelay and idelay cells
  -- but the dynamic range is insufficient to cover our needs.
  rf_activated <= '1' when rf_t1_sync_i = '1' else rf_activated_r;
  rst_rf       <= '1' when rf_t1_sync_i = '1'                                        else
                  '0' when rst_rf_cnt_r = (unsigned(rf_t1_sync_cdelay_i) - unsigned(rf_rst_cdelay_offset_i)) else rst_rf_r;
  rst_rf_cnt  <= rst_rf_cnt_r + 1  when rst_rf = '1' and rf_activated = '1' else (others => '0');

  -- Delay rf_t1_syncs such that we have stable RF at the trigger unit input after an nco_reset
  t1_sync_cdelay(0)            <= rf_t1_sync_i;
  t1_sync_cdelay(127 downto 1) <= t1_sync_cdelay_r(126 downto 0);
  t1_sync_cdelayed             <= t1_sync_cdelay_r(to_integer(unsigned(rf_t1_sync_cdelay_i)));
  t1_sync_pattern              <= std_logic_vector(unsigned'(X"0000FF") sll to_integer(unsigned(rf_t1_sync_fdelay_r)));

  t1_sync_fdelay <= t1_sync_pattern_r(7  downto  0) when t1_sync_cdelayed_r  = '1' and t1_sync_cdelayed_h   = '0' else
                    t1_sync_pattern_r(15 downto  8) when t1_sync_cdelayed_h  = '1' and t1_sync_cdelayed_hh  = '0' else
                    t1_sync_pattern_r(23 downto 16) when t1_sync_cdelayed_hh = '1' and t1_sync_cdelayed_hhh = '0' else (others => '0');

  process (clk_sys_i) is
  begin
     if rising_edge(clk_sys_i) then
        t1_sync_cdelay_r    <= t1_sync_cdelay;
        rf_activated_r      <= rf_activated;
        rst_rf_r            <= rst_rf;
        rst_rf_cnt_r        <= rst_rf_cnt;
     end if;
  end process;

  rf_rst_o <= rst_rf_r;

  process (clk125m_i) is
  begin
     if rising_edge(clk125m_i) then
        t1_sync_cdelayed_r   <= t1_sync_cdelayed;
        t1_sync_cdelayed_h   <= t1_sync_cdelayed_r;
        t1_sync_cdelayed_hh  <= t1_sync_cdelayed_h;
        t1_sync_cdelayed_hhh <= t1_sync_cdelayed_hh;
        t1_sync_pattern_r    <= t1_sync_pattern;
        rf_t1_sync_fdelay_r  <= rf_t1_sync_fdelay_i;
        t1_sync_fdelay_r     <= t1_sync_fdelay;
     end if;
  end process;

  rf_nco_reset_cdelayed_o <= t1_sync_cdelayed_r;

  inst_sync_OSERDESE2 : oserdese2
     generic map (
        DATA_RATE_OQ   => "DDR",    -- DDR, SDR
        DATA_RATE_TQ   => "SDR",    -- DDR, BUF, SDR
        DATA_WIDTH     => 8,        -- Parallel data width (2-8,10,14)
        INIT_OQ        => '0',      -- Initial value of OQ output (1'b0,1'b1)
        INIT_TQ        => '0',      -- Initial value of TQ output (1'b0,1'b1)
        SERDES_MODE    => "MASTER", -- MASTER, SLAVE
        SRVAL_OQ       => '0',      -- OQ output value when SR is used (1'b0,1'b1)
        SRVAL_TQ       => '0',      -- TQ output value when SR is used (1'b0,1'b1)
        TBYTE_CTL      => "FALSE",  -- Enable tristate byte operation (FALSE, TRUE)
        TBYTE_SRC      => "FALSE",  -- Tristate byte source (FALSE, TRUE)
        TRISTATE_WIDTH => 1 )       -- 3-state converter width (1,4)
     port map (
        OFB       => open,                 -- 1-bit output: Feedback path for data
        OQ        => t1_sync_fdelayed,     -- 1-bit output: Data path output
        SHIFTOUT1 => open,                 -- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
        SHIFTOUT2 => open,
        TBYTEOUT  => open,                 -- 1-bit output: Byte group tristate
        TFB       => open,                 -- 1-bit output: 3-state control
        TQ        => sync_serdes_tristate, -- 1-bit output: 3-state control
        CLK       => clk500m_i,            -- 1-bit input: High speed clock
        CLKDIV    => clk125m_i,            -- 1-bit input: Divided clock
        D1        => t1_sync_fdelay_r(0), -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
        D2        => t1_sync_fdelay_r(1),
        D3        => t1_sync_fdelay_r(2),
        D4        => t1_sync_fdelay_r(3),
        D5        => t1_sync_fdelay_r(4),
        D6        => t1_sync_fdelay_r(5),
        D7        => t1_sync_fdelay_r(6),
        D8        => t1_sync_fdelay_r(7),
        OCE       => '1',                  -- 1-bit input: Output data clock enable
        RST       => rst_clk125m_i,        -- 1-bit input: Reset
        SHIFTIN1  => '0',                  -- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
        SHIFTIN2  => '0',
        T1        => '0',                  -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
        T2        => '0',
        T3        => '0',
        T4        => '0',
        TBYTEIN   => '0',                  -- 1-bit input: Byte group tristate
        TCE       => '0' );                -- 1-bit input: 3-state clock enable
                                           --
    inst_sync_ODELAYE2 : ODELAYE2
        generic map (
            CINVCTRL_SEL          => "FALSE",    -- Enable dynamic clock inversion (FALSE, TRUE)
            DELAY_SRC             => "ODATAIN",  -- Delay input (ODATAIN, CLKIN)
            HIGH_PERFORMANCE_MODE => "TRUE",     -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
            ODELAY_TYPE           => "VAR_LOAD", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
            ODELAY_VALUE          => 0,          -- Output delay tap setting (0-31)
            PIPE_SEL              => "FALSE",    -- Select pipelined mode, FALSE, TRUE
            REFCLK_FREQUENCY      => 200.0,      -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
            SIGNAL_PATTERN        => "DATA" )    -- DATA, CLOCK input signal
        port map (
            CNTVALUEOUT => open,               -- output: Counter value output
            DATAOUT     => t1_sync_odelayed,   -- output: Delayed data/clock output
            C           => clk125m_i,          -- input: Clock input
            CE          => '0',                -- input: Active high enable increment/decrement input
            CINVCTRL    => '0',                -- input: Dynamic clock inversion input
            CLKIN       => '0',                -- input: Clock delay input
            CNTVALUEIN  => rf_t1_sync_odelay_i,-- input: Counter value input
            INC         => '0',                -- input: Increment / Decrement tap delay input
            LD          => '1',                -- input: Loads ODELAY_VALUE tap delay in VARIABLE mode
            LDPIPEEN    => '0',                -- input: Enables the pipeline register to load data
            ODATAIN     => t1_sync_fdelayed,   -- input: Output delay data input
            REGRST      => rst_sys_i );        -- input: Active-high reset tap-delay input

  rf_sync_OBUFDS : IOBUFDS
    generic map (
      IOSTANDARD => "LVDS",
      SLEW       => "FAST" )
    port map (
      IO  => rf_t1_sync_p_o,
      IOB => rf_t1_sync_n_o,
      T   => sync_serdes_tristate,
      O   => rf_sync_fb,
      I   => t1_sync_odelayed );

  process (clk_sys_i)
  begin
     if rising_edge(clk_sys_i) then
        rst_sys_r   <= rst_sys_i;
        rst_sys_n_r <= rst_sys_n_i;
     end if;
  end process;

  rf_t1_i : entity work.vtu_blk
     generic map (
        trigger_unit_t1  => true )
    port map (
      clk_sys_i        => clk_sys_i,
      rst_sys_i        => rst_sys_r,
      rst_rf_n_i       => t1_rst_rf_n_r,
      rst_serdes_i     => t1_rst_vtu_pulse_r,
      wb_i             => t1_wb_in,
      wb_o             => t1_wb_out,
      tm_tai_i         => tm_tai_i,
      tm_cycles_i      => tm_cycles_i,                                

      clk_rf_io_i      => rf_clk_io,
      clk_rf_i         => clk_rf,
      clk_vtu_i        => clk_vtu,
      clk_vtu_x2_i     => clk_vtu_x2,
      sync_i           => rf_sync_fb,
      sync_x8_fb_i     => X"00",
      sync_x8_fb_o     => rf_t1_sync_x8_fb,
      trig_o           => rf_t1_out,
      trig_rst_i       => rf_t1_rst_i,
      trig_rst_p_o     => rf_t1_rst_p_o,
      trig_rst_n_o     => rf_t1_rst_n_o,
      start_i          => rf_t1_start_i,
      stop_i           => rf_t1_stop_i,

      softstop_o       => rf_t1_softstop_o,
      softstart_o      => rf_t1_softstart_o,
      vtu_start_p_o    => rf_t1_vtu_start_p_o,

      ila_dbg_o        => rf_ila_dbg_o(15 downto 0) );

  --  Unit 1 output
  rf_trig_OBUFDS : OBUFDS
    generic map (
      IOSTANDARD => "LVDS",
      SLEW => "FAST")
    port map (
      O  => rf_t1_p_o,  -- Diff_p output
      OB => rf_t1_n_o,  -- Diff_n output
      I  => rf_t1_out );

  --  Feedback (directly from the pad) of unit 1 output.
  --rf_trig_IBUFDS : IBUFDS
  --  generic map (
  --    DIFF_TERM    => FALSE, --Differential Termination
  --    IBUF_LOW_PWR => TRUE,  --Lowpower (TRUE) vs. performance (FALSE) setting for referenced I/O standards
  --    IOSTANDARD   => "LVDS")
  --  port map (
  --    I  => rf_t1_p_o,  -- Diff_p output
  --    IB => rf_t1_n_o,  -- Diff_n output
  --    O  => open );
  rf_t1_fb <= '0';

  rf_t2_i : entity work.vtu_blk
     generic map (
        trigger_unit_t1  => false )
      port map (
        clk_sys_i        => clk_sys_i,
        rst_sys_i        => rst_sys_r,
        rst_rf_n_i       => t2_rst_rf_n_r,
        rst_serdes_i     => t2_rst_vtu_pulse_r,
        wb_i             => t2_wb_in,
        wb_o             => t2_wb_out,
        tm_tai_i         => tm_tai_i,
        tm_cycles_i      => tm_cycles_i,                                

        clk_rf_io_i      => rf_clk_io,
        clk_rf_i         => clk_rf,
        clk_vtu_i        => clk_vtu,
        clk_vtu_x2_i     => clk_vtu_x2,
        sync_i           => rf_t1_fb,
        sync_x8_fb_i     => rf_t1_sync_x8_fb,
        sync_x8_fb_o     => open,
        trig_o           => rf_t2_out,
        trig_rst_i       => rf_t2_rst_i,
        trig_rst_p_o     => rf_t2_rst_p_o,
        trig_rst_n_o     => rf_t2_rst_n_o,
        start_i          => rf_t2_start_i,
        stop_i           => rf_t2_stop_i,
        softstop_o       => rf_t2_softstop_o,
        softstart_o      => rf_t2_softstart_o,
        vtu_start_p_o    => rf_t2_vtu_start_p_o,

        ila_dbg_o        => rf_ila_dbg_o(31 downto 16) );

  --  Unit 2 output
  rf_trig2_OBUFDS : OBUFDS
    generic map (
      IOSTANDARD => "LVDS",
      SLEW => "SLOW")
    port map (
      O  => rf_t2_p_o,  -- Diff_p output
      OB => rf_t2_n_o,  -- Diff_n output
      I => rf_t2_out);

  --  Distribute clock to a bufg (for P0 signals)
  rf_bufg_1 : BUFG
    port map (
      I => rf_clk_in,
      O => rf_clk_bufg_o);

  --  Delay control (1 per clock region)
  rf_IDELAYCTRL : IDELAYCTRL
    port map (
      RDY    => rf_idelay_rdy,     -- 1-bit output: Ready output
      REFCLK => clk_refclk_200m_i, -- 1-bit input: Reference clock input
      RST    => iodelay_reset_i ); -- 1-bit input: Active high reset input

  --  Diag for rf_clk.
  inst_rf_diag: entity work.vtu_diag
  port map (
    clk_i => clk_sys_i,
    rst_n_i => rst_sys_n_r,
    sig_i => rf_clk_in,
    dat_i => b"0100_0000",  -- One pulse.
    enable_i => diag_rf_enable,
    windows_i => diag_rf_window,
    freq_o => diag_rf_freq,
    generation_o => diag_rf_generation,
    counter_o => diag_rf_counter
  );

  inst_regs: entity work.wr2rf_rftrigger_regs
    port map (
      rst_n_i => rst_sys_n_r,
      clk_i => clk_sys_i,
      wb_i => wb_i,
      wb_o => wb_o,
      t1_i => t1_wb_out,
      t1_o => t1_wb_in,
      t2_i => t2_wb_out,
      t2_o => t2_wb_in,
      rf_diag_control_enable_o => diag_rf_enable,
      rf_diag_control_window_o => diag_rf_window,
      rf_diag_freq_i => diag_rf_freq,
      rf_diag_generation_i => diag_rf_generation,
      rf_diag_counter_i => diag_rf_counter
    );

end architecture;
