source Options/build.tcl
update_compile_order -fileset sources_1

#synth_design -top "nonIQModInterp2FIR_wrapper" -part ${part_name}

launch_runs synth_1 -jobs 24
wait_on_run synth_1
open_run synth_1 -name synth_1

write_verilog nonIQModInterp2FIR.v

set_property target_language VHDL [current_project]
make_wrapper -files [get_files Work/nonIQModInterp2FIR.srcs/sources_1/bd/nonIQModInterp2FIR/nonIQModInterp2FIR.bd] -top

exit
