--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- WR2RF_VME
-- https://ohwr.org/project/vme-rf-wr-bobr
--------------------------------------------------------------------------------
--
-- unit name:   wr2rf_rfchan_wrap
--
-- description: a wrapper for instantiating the two RFNCO and IQMod blocks.
--
--------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN (home.cern)
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.RFFrameTransceiver_pkg.all;
use work.wishbone_pkg.all;

entity wr2rf_rfchan_wrap is

    generic (
        g_dac_dpins           : integer := 16 );

    port (
        clk125m_i             : in  std_logic;
        clk250m_i             : in  std_logic;

        rst_clk125m_i         : in  std_logic;
        rst_clk125m_n_i       : in  std_logic;
        rst_clk250m_i         : in  std_logic;
        rst_clk250m_n_i       : in  std_logic;

        rf1_dds_ftw_valid_i   : in  std_logic;
        rf1_dds_ftw_i         : in  std_logic_vector(47 downto 0);
        rf2_dds_ftw_valid_i   : in  std_logic;
        rf2_dds_ftw_i         : in  std_logic_vector(47 downto 0);

        rx_RFmFramePayloads_i : in  t_RFmFramePayload;
        rx_Frame_valid_pX_i   : in  std_logic;

        rf1_iqdac_igain_i     : in  std_logic_vector(15 downto 0);
        rf1_iqdac_qgain_i     : in  std_logic_vector(15 downto 0);
        rf1_iqdac_ctrl_i      : in  std_logic_vector(15 downto 0);

        rf2_iqdac_igain_i     : in  std_logic_vector(15 downto 0);
        rf2_iqdac_qgain_i     : in  std_logic_vector(15 downto 0);
        rf2_iqdac_ctrl_i      : in  std_logic_vector(15 downto 0);

        wb_rf1_rfnco_slave_i  : in  t_wishbone_slave_in;
        wb_rf1_rfnco_slave_o  : out t_wishbone_slave_out;
        wb_rf2_rfnco_slave_i  : in  t_wishbone_slave_in;
        wb_rf2_rfnco_slave_o  : out t_wishbone_slave_out;

        rf1_frev_o            : out std_logic;
        rf1_frev_main_o       : out std_logic;
        rf2_frev_o            : out std_logic;
        rf2_frev_main_o       : out std_logic;

        rf1_iqdac_data_p_o    : out std_logic_vector(g_dac_dpins-1 downto 0);
        rf1_iqdac_data_n_o    : out std_logic_vector(g_dac_dpins-1 downto 0);
        rf1_iqdac_dci_p_o     : out std_logic;
        rf1_iqdac_dci_n_o     : out std_logic;

        rf2_iqdac_data_p_o    : out std_logic_vector(g_dac_dpins-1 downto 0);
        rf2_iqdac_data_n_o    : out std_logic_vector(g_dac_dpins-1 downto 0);
        rf2_iqdac_dci_p_o     : out std_logic;
        rf2_iqdac_dci_n_o     : out std_logic;

        rf1_ila_dbg_o         : out std_logic_vector(127 downto 0);
        rf2_ila_dbg_o         : out std_logic_vector(127 downto 0) );

end entity;

architecture rtl of wr2rf_rfchan_wrap is

--    signal zero        : std_logic := '0';

begin

   rfchan_1 : entity  work.wr2rf_rfchan
      generic map (
         g_dac_dpins           =>  g_dac_dpins )
      port map (
         clk125m_i             => clk125m_i,
         clk250m_i             => clk250m_i,

         rst_clk125m_i         => rst_clk125m_i,
         rst_clk125m_n_i       => rst_clk125m_n_i,
         rst_clk250m_i         => rst_clk250m_i,
         rst_clk250m_n_i       => rst_clk250m_n_i,

         dds_ftw_valid_i       => rf1_dds_ftw_valid_i,
         dds_ftw_i             => rf1_dds_ftw_i,

         rx_RFmFramePayloads_i => rx_RFmFramePayloads_i,
         rx_Frame_valid_pX_i   => rx_Frame_valid_pX_i,
         iqdac_igain_i         => rf1_iqdac_igain_i,
         iqdac_qgain_i         => rf1_iqdac_qgain_i,
         iqdac_ctrl_i          => rf1_iqdac_ctrl_i,

         wb_rfnco_slave_i      => wb_rf1_rfnco_slave_i,
         wb_rfnco_slave_o      => wb_rf1_rfnco_slave_o,

         rfnco_frev_o          => rf1_frev_o,
         rfnco_frev_main_o     => rf1_frev_main_o,
         iqdac_data_p_o        => rf1_iqdac_data_p_o,
         iqdac_data_n_o        => rf1_iqdac_data_n_o,
         iqdac_dci_p_o         => rf1_iqdac_dci_p_o,
         iqdac_dci_n_o         => rf1_iqdac_dci_n_o,

         ila_dbg_o             => rf1_ila_dbg_o );

   rfchan_2 : entity  work.wr2rf_rfchan
      generic map (
         g_dac_dpins           =>  g_dac_dpins )
      port map (
         clk125m_i             => clk125m_i,
         clk250m_i             => clk250m_i,

         rst_clk125m_i         => rst_clk125m_i,
         rst_clk125m_n_i       => rst_clk125m_n_i,
         rst_clk250m_i         => rst_clk250m_i,
         rst_clk250m_n_i       => rst_clk250m_n_i,

         dds_ftw_valid_i       => rf2_dds_ftw_valid_i,
         dds_ftw_i             => rf2_dds_ftw_i,

         rx_RFmFramePayloads_i => rx_RFmFramePayloads_i,
         rx_Frame_valid_pX_i   => rx_Frame_valid_pX_i,
         iqdac_igain_i         => rf2_iqdac_igain_i,
         iqdac_qgain_i         => rf2_iqdac_qgain_i,
         iqdac_ctrl_i          => rf2_iqdac_ctrl_i,

         wb_rfnco_slave_i      => wb_rf2_rfnco_slave_i,
         wb_rfnco_slave_o      => wb_rf2_rfnco_slave_o,

         rfnco_frev_o          => rf2_frev_o,
         rfnco_frev_main_o     => rf2_frev_main_o,
         iqdac_data_p_o        => rf2_iqdac_data_p_o,
         iqdac_data_n_o        => rf2_iqdac_data_n_o,
         iqdac_dci_p_o         => rf2_iqdac_dci_p_o,
         iqdac_dci_n_o         => rf2_iqdac_dci_n_o,

         ila_dbg_o             => rf2_ila_dbg_o );

end architecture;
