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Commit 5418cc30 authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: refactoring.

parent 4fc725b8
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dependencies/vtu/rtl/vtuCore.vhd
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......@@ -1078,7 +1078,6 @@ architecture vtuCore of vtuCore is
signal wValueOne_seq : std_logic;
signal BCoarseZero : std_logic;
signal SwitchOutput : std_logic;
signal COne : std_logic_vector(63 downto 0 );
signal Run_i : std_logic;
signal PlayMemoryMode : std_logic;
signal wrongHT_s : std_logic;
......@@ -1144,104 +1143,6 @@ architecture vtuCore of vtuCore is
signal ReadDataZero : std_logic;
begin
-- Data shifter using B parameters: from Sync pulse to the first pulse.
B_DataShifterB: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '1')
port map (CoarseZero => BCoarseZero,
DataOut => DataOut_B,
OutputEnabled => OE_B,
Clk => Clk,
Delay => bValue,
DataIn => DataIn,
Enabled => Shifter1Ena,
SyncPulse => SyncPulse_i);
-- Data shifter using HT parameters: after the first pulse.
B_DataShifterHT: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0')
port map (CoarseZero => HTCoarseZero,
DataOut => DataOut_HT,
OutputEnabled => OE_HT,
Clk => Clk,
Delay => htValue_effective,
DataIn => DataIn_HT,
Enabled => Shifter2Ena,
SyncPulse => open);
B_vtuSeq: entity work.vtuSeq
port map (Clk => Clk,
Rst => Rst,
Start => Start_seq,
Stop => Stop_seq,
SyncPulse => SyncPulse_i,
OutputEnable1 => OE_B,
OutputEnable2 => OE_HT,
Shifter1Ena => Shifter1Ena,
Shifter2Ena => Shifter2Ena,
SwitchtoHT => SwitchtoHT,
wValueOne => wValueOne_seq,
WindowDone => WindowDone_seq,
CounterRst => counterReset,
Run => Run_seq);
-- Select start input.
Start_i <= Start when UseSyncAsStart = '0' else SyncPulse_i;
-- Start sequencer on start signal if sequencer mode selected.
Start_seq <= Start_i when (SyncLessOperationMode or PlayMemoryMode) = '0' else '0';
-- Stop sequencer on stop signal or if values aren't correct.
Stop_seq <= Stop or wrongValue;
B_DataShifterHT_SyncLess: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0')
port map (CoarseZero => open,
DataOut => DataOutHTSyncLess,
OutputEnabled => OE_SyncLess,
Clk => Clk,
Delay => htValue_effective,
DataIn => DataInHTSyncLess,
Enabled => SyncLessEna,
SyncPulse => open);
B_PlayMemRunningFF: entity work.RSFF
port map (Clk => Clk,
Set => StartPlayMem,
Clr => StopPlayMem,
Rst => Rst,
Q => RunPlayMem_i);
B_FirstSyncFF: entity work.RSFF
port map (Clk => Clk,
Set => RunPlayAndSyncPulse,
Clr => StopPlayMem,
Rst => Rst,
Q => FirstSyncArrived);
B_PlayingMemFF: entity work.RSFF
port map (Clk => Clk,
Set => SetPlayingMem,
Clr => StopPlayMem,
Rst => Rst,
Q => PlayingMem_i);
B_PlayMemLogic: entity work.PlayMemLogic
port map (Clk => Clk,
RunPlayMem => RunPlayMem,
FirstOutput => FirstOutput,
PlayingMem => PlayingMem,
LastElem => Mem_LastElem(14 downto 0),
RdData => Mem_RdData(7 downto 0),
RdDataPrev => Mem_RdData_prev(7 downto 0),
RdDataZero => Mem_RdDataZero(7 downto 0),
FirstBit => FirstBit(2 downto 0),
LastBit => Mem_LastBit(2 downto 0),
Mem_Addr => Mem_Addr_i(14 downto 0),
DataOut => DataOutPlayMem(7 downto 0));
B_ModeSelDecoder: entity work.ModeSelDecoder
port map (Mode => Mode(2 downto 0),
SinglePulseMode => SinglePulseMode,
......@@ -1271,302 +1172,410 @@ begin
wrongW <= wrongW_s;
-- True if running.
Run_i <= Run_seq or RunSyncLess or PlayingMem;
Run <= Run_i;
SwitchOutput <= SwitchtoHT or (not Run_seq);
process (DataOut_B, DataOut_HT, SwitchOutput)
blk_seq: block
begin
case SwitchOutput is
when '0' =>
-- B datashifter.
DataOut_seq_i <= DataOut_B;
when others =>
-- HT datashifter
DataOut_seq_i <= DataOut_HT;
end case;
end process;
RstOrStopSeq <= Rst or Stop_seq;
DataOut_seq <= DataOut_seq_i when RstOrStopSeq = '0' else (others => '0');
process (DataOut_B, DataOut_HT, SwitchtoHT)
begin
case SwitchtoHT is
when '0' =>
-- B datashifter to HT datashifter
DataIn_HT <= DataOut_B;
when others =>
-- HT datashifter loopback.
DataIn_HT <= DataOut_HT;
end case;
end process;
-- Data shifter using B parameters: from Sync pulse to the first pulse.
B_DataShifterB: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '1')
port map (CoarseZero => BCoarseZero,
DataOut => DataOut_B,
OutputEnabled => OE_B,
Clk => Clk,
Delay => bValue,
DataIn => DataIn,
Enabled => Shifter1Ena,
SyncPulse => SyncPulse_i);
-- Data shifter using HT parameters: after the first pulse.
B_DataShifterHT: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0')
port map (CoarseZero => HTCoarseZero,
DataOut => DataOut_HT,
OutputEnabled => OE_HT,
Clk => Clk,
Delay => htValue_effective,
DataIn => DataIn_HT,
Enabled => Shifter2Ena,
SyncPulse => open);
B_vtuSeq: entity work.vtuSeq
port map (Clk => Clk,
Rst => Rst,
Start => Start_seq,
Stop => Stop_seq,
SyncPulse => SyncPulse_i,
OutputEnable1 => OE_B,
OutputEnable2 => OE_HT,
Shifter1Ena => Shifter1Ena,
Shifter2Ena => Shifter2Ena,
SwitchtoHT => SwitchtoHT,
wValueOne => wValueOne_seq,
WindowDone => WindowDone_seq,
CounterRst => counterReset,
Run => Run_seq);
-- Select start input.
Start_i <= Start when UseSyncAsStart = '0' else SyncPulse_i;
-- Start sequencer on start signal if sequencer mode selected.
Start_seq <= Start_i when (SyncLessOperationMode or PlayMemoryMode) = '0' else '0';
-- Stop sequencer on stop signal or if values aren't correct.
Stop_seq <= Stop or wrongValue;
-- True if running.
Run_i <= Run_seq or RunSyncLess or PlayingMem;
Run <= Run_i;
SwitchOutput <= SwitchtoHT or (not Run_seq);
process (DataOut_B, DataOut_HT, SwitchOutput)
begin
case SwitchOutput is
when '0' =>
-- B datashifter.
DataOut_seq_i <= DataOut_B;
when others =>
-- HT datashifter
DataOut_seq_i <= DataOut_HT;
end case;
end process;
DataOut <= DataOutHTSyncLess when Mode = C_Code_ctuAsVtu_control2_mode_syncLessOperation else
DataOutLowFreq when Mode = C_Code_ctuAsVtu_control2_mode_lowFreqGeneration else
DataOutPlayMem when Mode = C_Code_ctuAsVtu_control2_mode_playMemory else
DataOut_seq;
RstOrStopSeq <= Rst or Stop_seq;
-- Pulse detected.
SyncPulse <= SyncPulse_i;
DataOut_seq <= DataOut_seq_i when RstOrStopSeq = '0' else (others => '0');
process (htValue, SwitchHTeffective)
begin
case SwitchHTeffective is
when '0' =>
htValue_effective <= htValue;
when others =>
-- Do not care about overflow in the addition. It can only happen when htValue is ffff_ffff_ffff_ffff,
-- and thus the switch happen after the end of the universe.
htValue_effective <= std_logic_vector(unsigned(htValue) + 1);
end case;
end process;
process (DataOut_B, DataOut_HT, SwitchtoHT)
begin
case SwitchtoHT is
when '0' =>
-- B datashifter to HT datashifter
DataIn_HT <= DataOut_B;
when others =>
-- HT datashifter loopback.
DataIn_HT <= DataOut_HT;
end case;
end process;
HTSwitchEna <= (OE_HT or OE_SyncLess) and htSwitching;
counterEnable <= (OE_B or OE_HT) and Run_seq;
process (Clk, Run_i)
begin
if Run_i = '0' then
SwitchHTeffective <= '0';
elsif Clk'event and Clk = '1' then
if HTSwitchEna = '1' then
SwitchHTeffective <= not SwitchHTeffective;
process (Clk)
begin
if Clk'event and Clk = '1' then
if counterReset = '1' then
-- Start at 1 so that WindowDone_seq is set for the next pulse.
PulseCount <= x"0000_0000_0000_0001";
elsif counterEnable = '1' then
PulseCount <= std_logic_vector(unsigned (PulseCount) + 1);
end if;
end if;
end if;
end process;
COne(63 downto 0) <= (0=> '1', others => '0');
counterEnable <= (OE_B or OE_HT) and Run_seq;
end process;
process (Clk)
begin
if Clk'event and Clk = '1' then
if counterReset = '1' then
-- Start at 1 so that WindowDone_seq is set for the next pulse.
PulseCount <= x"0000_0000_0000_0001";
elsif counterEnable = '1' then
PulseCount <= std_logic_vector(unsigned (PulseCount) + 1);
process (PulseCount, wValue)
begin
if InfiniteWindow = '0' and (unsigned(PulseCount) >= unsigned(wValue)) then
WindowDone_seq <= '1';
else
WindowDone_seq <= '0';
end if;
end if;
end process;
end process;
process (PulseCount, wValue)
begin
if InfiniteWindow = '0' and (unsigned(PulseCount) >= unsigned(wValue)) then
WindowDone_seq <= '1';
else
WindowDone_seq <= '0';
end if;
end process;
wValueOne <= '1' when wValue = x"0000_0000_0000_0001" else '0';
wValueOne <= '1' when wValue = x"0000_0000_0000_0001" else '0';
wValueZero <= '1' when wValue = x"0000_0000_0000_0000" else '0';
wValueZero <= '1' when wValue = x"0000_0000_0000_0000" else '0';
wValueOne_seq <= (wValueOne or SinglePulseMode) and (not InfiniteWindow);
wValueOne_seq <= (wValueOne or SinglePulseMode) and (not InfiniteWindow);
InfiniteWindow <= InfiniteWindowMode or LowFreqGenerationMode;
end block blk_seq;
InfiniteWindow <= InfiniteWindowMode or LowFreqGenerationMode;
blk_syncless: block
begin
B_DataShifterHT_SyncLess: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0')
port map (CoarseZero => open,
DataOut => DataOutHTSyncLess,
OutputEnabled => OE_SyncLess,
Clk => Clk,
Delay => htValue_effective,
DataIn => DataInHTSyncLess,
Enabled => SyncLessEna,
SyncPulse => open);
StartSyncLess <= Start and SyncLessOperationMode;
-- Pulse on Start when in syncless.
B_RSFFSyncLessMux: entity work.RSFF
port map (Clk => Clk,
Set => StartSyncLess,
Clr => SetStartData,
Rst => Rst,
Q => SetStartData);
StartSyncLess <= Start and SyncLessOperationMode;
process (DataOutHTSyncLess, SetStartData)
begin
case SetStartData is
when '0' =>
-- Loopback in normal mode.
DataInHTSyncLess <= DataOutHTSyncLess;
when others =>
-- On start
DataInHTSyncLess <= x"01";
end case;
end process;
-- Pulse on Start when in syncless.
B_RSFFSyncLessMux: entity work.RSFF
port map (Clk => Clk,
Set => StartSyncLess,
Clr => SetStartData,
Rst => Rst,
Q => SetStartData);
SyncLessEna <= SyncLessOperationMode and (not RstOrStopSeq);
process (DataOutHTSyncLess, SetStartData)
begin
case SetStartData is
when '0' =>
-- Loopback in normal mode.
DataInHTSyncLess <= DataOutHTSyncLess;
when others =>
-- On start
DataInHTSyncLess <= x"01";
end case;
end process;
SyncLessDisabled <= not SyncLessEna;
SyncLessEna <= SyncLessOperationMode and (not RstOrStopSeq);
B_RSFFRunSyncLess: entity work.RSFF
port map (Clk => Clk,
Set => StartSyncLess,
Clr => SyncLessDisabled,
Rst => Rst,
Q => RunSyncLess);
end block blk_syncless;
SyncLessDisabled <= not SyncLessEna;
blk_playmem: block
begin
B_PlayMemRunningFF: entity work.RSFF
port map (Clk => Clk,
Set => StartPlayMem,
Clr => StopPlayMem,
Rst => Rst,
Q => RunPlayMem_i);
B_FirstSyncFF: entity work.RSFF
port map (Clk => Clk,
Set => RunPlayAndSyncPulse,
Clr => StopPlayMem,
Rst => Rst,
Q => FirstSyncArrived);
B_PlayingMemFF: entity work.RSFF
port map (Clk => Clk,
Set => SetPlayingMem,
Clr => StopPlayMem,
Rst => Rst,
Q => PlayingMem_i);
B_PlayMemLogic: entity work.PlayMemLogic
port map (Clk => Clk,
RunPlayMem => RunPlayMem,
FirstOutput => FirstOutput,
PlayingMem => PlayingMem,
LastElem => Mem_LastElem(14 downto 0),
RdData => Mem_RdData(7 downto 0),
RdDataPrev => Mem_RdData_prev(7 downto 0),
RdDataZero => Mem_RdDataZero(7 downto 0),
FirstBit => FirstBit(2 downto 0),
LastBit => Mem_LastBit(2 downto 0),
Mem_Addr => Mem_Addr_i(14 downto 0),
DataOut => DataOutPlayMem(7 downto 0));
StartPlayMem <= Start_i and PlayMemoryMode;
StopPlayMem <= (not PlayMemoryMode) or RstOrStopSeq;
RunPlayMem <= (RunPlayMem_i or StartPlayMem) and (not StopPlayMem);
RunPlayAndSyncPulse <= RunPlayMem and SyncPulse_i;
SetPlayingMem <= FirstSyncArrived and OE_B;
PlayingMem <= (PlayingMem_i or SetPlayingMem) and (not StopPlayMem);
Mem_RdEna <= RunPlayMem;
B_RSFFRunSyncLess: entity work.RSFF
port map (Clk => Clk,
Set => StartSyncLess,
Clr => SyncLessDisabled,
Rst => Rst,
Q => RunSyncLess);
process (Clk)
begin
if (Clk'event and Clk = '1') then
PlayingMem_prev <= (PlayingMem);
end if;
end process;
process (Clk, RstOrStopSeq)
begin
if RstOrStopSeq = '1' then
ClkValueSwitch <= '0';
elsif (Clk'event and Clk = '1') then
if DataOutPulse = '1' then
ClkValueSwitch <= not ClkValueSwitch;
process (Clk)
begin
if (Clk'event and Clk = '1') then
Mem_RdData_prev(7 downto 0) <= (Mem_RdData(7 downto 0));
end if;
end if;
end process;
end process;
DataOutPulse <= DataOut_seq(7) or DataOut_seq(6) or DataOut_seq(5)
or DataOut_seq(4) or DataOut_seq(3) or DataOut_seq(2)
or DataOut_seq(1) or DataOut_seq(0);
FirstOutput <= PlayingMem and (not PlayingMem_prev);
process (ClkValueSwitch)
begin
case ClkValueSwitch is
when '0' =>
DataAllEqual <= (others => '0');
when others =>
DataAllEqual <= (others => '1');
end case;
end process;
Mem_Addr(14 downto 0) <= Mem_Addr_i(14 downto 0);
process (DataAllEqual , DataFilled , FilledMuxSel)
begin
case FilledMuxSel is
when '0' =>
DataOutLowFreq <= DataAllEqual;
when others =>
DataOutLowFreq <= DataFilled;
end case;
end process;
Mem_AddrZero(14 downto 0) <= (others => '0');
-- Fill data with ones or zeros after one when DataOutPulse='1'
process(DataOut_seq, DataOutPulse, ClkValueSwitch)
begin
if DataOutPulse = '1' then
if DataOut_seq(7)='1' then
if ClkValueSwitch='1' then
DataFilled <= "10000000";
else
DataFilled <= "01111111";
end if;
elsif DataOut_seq(6)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11000000";
else
DataFilled <= "00111111";
end if;
elsif DataOut_seq(5)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11100000";
else
DataFilled <= "00011111";
end if;
elsif DataOut_seq(4)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11110000";
else
DataFilled <= "00001111";
end if;
elsif DataOut_seq(3)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11111000";
else
DataFilled <= "00000111";
end if;
elsif DataOut_seq(2)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11111100";
else
DataFilled <= "00000011";
end if;
elsif DataOut_seq(1)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11111110";
else
DataFilled <= "00000001";
end if;
process (Mem_Addr_i , Mem_AddrZero)
begin
if Mem_Addr_i(14 downto 0) = Mem_AddrZero(14 downto 0) then
MemAddrIsZero <= '1';
else
if ClkValueSwitch='1' then
DataFilled <= "11111111";
else
DataFilled <= "00000000";
end if;
MemAddrIsZero <= '0';
end if;
else
DataFilled <= (others => '0');
end if;
end process;
FilledMuxSel <= (not RstOrStopSeq) and DataOutPulse;
end process;
StartPlayMem <= Start_i and PlayMemoryMode;
process (Clk)
begin
if (Clk'event and Clk = '1') then
MemAddrIsZeroPrev <= (MemAddrIsZero);
end if;
end process;
StopPlayMem <= (not PlayMemoryMode) or RstOrStopSeq;
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (ReadDataZero = '1') then
Mem_RdDataZero(7 downto 0) <= (Mem_RdData(7 downto 0));
end if;
end if;
end process;
RunPlayMem <= (RunPlayMem_i or StartPlayMem) and (not StopPlayMem);
FirstBit <= "000" when FirstOutput='1' and DataOut_B(0)='1' else
"001" when FirstOutput='1' and DataOut_B(1)='1' else
"010" when FirstOutput='1' and DataOut_B(2)='1' else
"011" when FirstOutput='1' and DataOut_B(3)='1' else
"100" when FirstOutput='1' and DataOut_B(4)='1' else
"101" when FirstOutput='1' and DataOut_B(5)='1' else
"110" when FirstOutput='1' and DataOut_B(6)='1' else
"111" when FirstOutput='1' and DataOut_B(7)='1' else
"000";
RunPlayAndSyncPulse <= RunPlayMem and SyncPulse_i;
ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;
end block blk_playmem;
SetPlayingMem <= FirstSyncArrived and OE_B;
blk_lowfreq: block
begin
process (Clk, RstOrStopSeq)
begin
if RstOrStopSeq = '1' then
ClkValueSwitch <= '0';
elsif (Clk'event and Clk = '1') then
if DataOutPulse = '1' then
ClkValueSwitch <= not ClkValueSwitch;
end if;
end if;
end process;
PlayingMem <= (PlayingMem_i or SetPlayingMem) and (not StopPlayMem);
DataOutPulse <= DataOut_seq(7) or DataOut_seq(6) or DataOut_seq(5)
or DataOut_seq(4) or DataOut_seq(3) or DataOut_seq(2)
or DataOut_seq(1) or DataOut_seq(0);
Mem_RdEna <= RunPlayMem;
process (ClkValueSwitch)
begin
case ClkValueSwitch is
when '0' =>
DataAllEqual <= (others => '0');
when others =>
DataAllEqual <= (others => '1');
end case;
end process;
process (Clk)
begin
if (Clk'event and Clk = '1') then
PlayingMem_prev <= (PlayingMem);
end if;
end process;
process (DataAllEqual, DataFilled, FilledMuxSel)
begin
case FilledMuxSel is
when '0' =>
DataOutLowFreq <= DataAllEqual;
when others =>
DataOutLowFreq <= DataFilled;
end case;
end process;
process (Clk)
begin
if (Clk'event and Clk = '1') then
Mem_RdData_prev(7 downto 0) <= (Mem_RdData(7 downto 0));
end if;
end process;
-- Fill data with ones or zeros after one when DataOutPulse='1'
process (DataOut_seq, DataOutPulse, ClkValueSwitch)
begin
if DataOutPulse = '1' then
if DataOut_seq(7)='1' then
if ClkValueSwitch='1' then
DataFilled <= "10000000";
else
DataFilled <= "01111111";
end if;
elsif DataOut_seq(6)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11000000";
else
DataFilled <= "00111111";
end if;
elsif DataOut_seq(5)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11100000";
else
DataFilled <= "00011111";
end if;
elsif DataOut_seq(4)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11110000";
else
DataFilled <= "00001111";
end if;
elsif DataOut_seq(3)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11111000";
else
DataFilled <= "00000111";
end if;
elsif DataOut_seq(2)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11111100";
else
DataFilled <= "00000011";
end if;
elsif DataOut_seq(1)='1' then
if ClkValueSwitch='1' then
DataFilled <= "11111110";
else
DataFilled <= "00000001";
end if;
else
if ClkValueSwitch='1' then
DataFilled <= "11111111";
else
DataFilled <= "00000000";
end if;
end if;
else
DataFilled <= (others => '0');
end if;
end process;
FirstOutput <= PlayingMem and (not PlayingMem_prev);
FilledMuxSel <= (not RstOrStopSeq) and DataOutPulse;
end block blk_lowfreq;
Mem_Addr(14 downto 0) <= Mem_Addr_i(14 downto 0);
DataOut <= DataOutHTSyncLess when Mode = C_Code_ctuAsVtu_control2_mode_syncLessOperation else
DataOutLowFreq when Mode = C_Code_ctuAsVtu_control2_mode_lowFreqGeneration else
DataOutPlayMem when Mode = C_Code_ctuAsVtu_control2_mode_playMemory else
DataOut_seq;
Mem_AddrZero(14 downto 0) <= (others => '0');
-- Pulse detected.
SyncPulse <= SyncPulse_i;
process (Mem_Addr_i , Mem_AddrZero)
process (htValue, SwitchHTeffective)
begin
if Mem_Addr_i(14 downto 0) = Mem_AddrZero(14 downto 0) then
MemAddrIsZero <= '1';
else
MemAddrIsZero <= '0';
end if;
end process;
case SwitchHTeffective is
when '0' =>
htValue_effective <= htValue;
when others =>
-- Do not care about overflow in the addition. It can only happen when htValue is ffff_ffff_ffff_ffff,
-- and thus the switch happen after the end of the universe.
htValue_effective <= std_logic_vector(unsigned(htValue) + 1);
end case;
end process;
process (Clk)
begin
if (Clk'event and Clk = '1') then
MemAddrIsZeroPrev <= (MemAddrIsZero);
end if;
end process;
HTSwitchEna <= (OE_HT or OE_SyncLess) and htSwitching;
process (Clk)
process (Clk, Run_i)
begin
if (Clk'event and Clk = '1') then
if (ReadDataZero = '1') then
Mem_RdDataZero(7 downto 0) <= (Mem_RdData(7 downto 0));
if Run_i = '0' then
SwitchHTeffective <= '0';
elsif Clk'event and Clk = '1' then
if HTSwitchEna = '1' then
SwitchHTeffective <= not SwitchHTeffective;
end if;
end if;
end process;
FirstBit <= "000" when FirstOutput='1' and DataOut_B(0)='1' else
"001" when FirstOutput='1' and DataOut_B(1)='1' else
"010" when FirstOutput='1' and DataOut_B(2)='1' else
"011" when FirstOutput='1' and DataOut_B(3)='1' else
"100" when FirstOutput='1' and DataOut_B(4)='1' else
"101" when FirstOutput='1' and DataOut_B(5)='1' else
"110" when FirstOutput='1' and DataOut_B(6)='1' else
"111" when FirstOutput='1' and DataOut_B(7)='1' else
"000";
ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;
end vtuCore;
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