Commit 5cdb9ff5 authored by Tristan Gingold's avatar Tristan Gingold

vtuCore: minor reformating.

parent 6069f361
......@@ -1049,6 +1049,31 @@ begin
-- Select start input.
Start_i <= Start when UseSyncAsStart = '0' else SyncPulse_i;
process (htValue, SwitchHTeffective)
begin
case SwitchHTeffective is
when '0' =>
htValue_effective <= htValue;
when others =>
-- Do not care about overflow in the addition. It can only happen when htValue is ffff_ffff_ffff_ffff,
-- and thus the switch happen after the end of the universe.
htValue_effective <= std_logic_vector(unsigned(htValue) + 1);
end case;
end process;
HTSwitchEna <= (OE_HT or OE_SyncLess) and htSwitching;
process (Clk, Run_i)
begin
if Run_i = '0' then
SwitchHTeffective <= '0';
elsif Clk'event and Clk = '1' then
if HTSwitchEna = '1' then
SwitchHTeffective <= not SwitchHTeffective;
end if;
end if;
end process;
blk_seq: block
is
signal wrongHT_s : std_logic;
......@@ -1445,29 +1470,4 @@ begin
-- True if running.
Run_i <= Run_seq or RunSyncLess or PlayingMem;
Run <= Run_i;
process (htValue, SwitchHTeffective)
begin
case SwitchHTeffective is
when '0' =>
htValue_effective <= htValue;
when others =>
-- Do not care about overflow in the addition. It can only happen when htValue is ffff_ffff_ffff_ffff,
-- and thus the switch happen after the end of the universe.
htValue_effective <= std_logic_vector(unsigned(htValue) + 1);
end case;
end process;
HTSwitchEna <= (OE_HT or OE_SyncLess) and htSwitching;
process (Clk, Run_i)
begin
if Run_i = '0' then
SwitchHTeffective <= '0';
elsif Clk'event and Clk = '1' then
if HTSwitchEna = '1' then
SwitchHTeffective <= not SwitchHTeffective;
end if;
end if;
end process;
end vtuCore;
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