vtuCore: more cleanup.

6326222b · Tristan Gingold · e831a704 · 6326222b
Commit 6326222b authored Apr 23, 2020 by Tristan Gingold
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Showing with 33 additions and 36 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +33 -36

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -1271,7 +1271,7 @@ begin
  begin
    B_DataShifterHT_SyncLess: entity work.vtuDataShifter
      generic map (N => 64,
-                  g_DisableDoubleSync => '0')
+                   g_DisableDoubleSync => '0')
      port map (CoarseZero => open,
                DataOut => DataOutHTSyncLess,
                OutputEnabled => OE_SyncLess,
@@ -1285,23 +1285,23 @@ begin

    --  Pulse on Start when in syncless.
    B_RSFFSyncLessMux: entity work.RSFF
-    port map (Clk => Clk,
-              Set => StartSyncLess,
-              Clr => SetStartData,
-              Rst => Rst,
-              Q => SetStartData);
+      port map (Clk => Clk,
+                Set => StartSyncLess,
+                Clr => SetStartData,
+                Rst => Rst,
+                Q => SetStartData);

    process (DataOutHTSyncLess, SetStartData)
    begin
-        case SetStartData is
-          when '0' =>
-            --  Loopback in normal mode.
-            DataInHTSyncLess <=  DataOutHTSyncLess;
-          when others =>
-            --  On start
-            DataInHTSyncLess <=  x"01";
-        end case;
-      end process;
+      case SetStartData is
+        when '0' =>
+          --  Loopback in normal mode.
+          DataInHTSyncLess <=  DataOutHTSyncLess;
+        when others =>
+          --  On start
+          DataInHTSyncLess <=  x"01";
+      end case;
+    end process;

    SyncLessEna <= SyncLessOperationMode and (not RstOrStopSeq);

@@ -1317,7 +1317,6 @@ begin

  blk_playmem: block
  is
-    signal Mem_AddrZero : std_logic_vector(14 downto 0 );
    signal Mem_RdData_prev : std_logic_vector(7 downto 0 ) := (others  => '0');
    signal FirstBit : std_logic_vector(2 downto 0);
    signal MemAddrIsZeroPrev : std_logic;
@@ -1362,14 +1361,14 @@ begin
                RunPlayMem => RunPlayMem,
                FirstOutput => FirstOutput,
                PlayingMem => PlayingMem,
-                LastElem => Mem_LastElem(14 downto 0),
-                RdData => Mem_RdData(7 downto 0),
-                RdDataPrev => Mem_RdData_prev(7 downto 0),
-                RdDataZero => Mem_RdDataZero(7 downto 0),
-                FirstBit => FirstBit(2 downto 0),
-                LastBit => Mem_LastBit(2 downto 0),
-                Mem_Addr => Mem_Addr_i(14 downto 0),
-                DataOut => DataOutPlayMem(7 downto 0));
+                LastElem => Mem_LastElem,
+                RdData => Mem_RdData,
+                RdDataPrev => Mem_RdData_prev,
+                RdDataZero => Mem_RdDataZero,
+                FirstBit => FirstBit,
+                LastBit => Mem_LastBit,
+                Mem_Addr => Mem_Addr_i,
+                DataOut => DataOutPlayMem);

    StartPlayMem <= Start_i and PlayMemoryMode;

@@ -1388,26 +1387,24 @@ begin
    process (Clk)
    begin
      if (Clk'event and Clk = '1') then
-          PlayingMem_prev <= (PlayingMem);
+        PlayingMem_prev <= PlayingMem;
      end if;
    end process;

    process (Clk)
    begin
      if (Clk'event and Clk = '1') then
-        Mem_RdData_prev(7 downto 0) <= (Mem_RdData(7 downto 0));
+        Mem_RdData_prev <= Mem_RdData;
      end if;
    end process;

    FirstOutput <= PlayingMem and (not PlayingMem_prev);

-    Mem_Addr(14 downto 0) <= Mem_Addr_i(14 downto 0);
-
-    Mem_AddrZero(14 downto 0) <= (others => '0');
+    Mem_Addr <= Mem_Addr_i;

-    process (Mem_Addr_i , Mem_AddrZero)
+    process (Mem_Addr_i)
    begin
-      if Mem_Addr_i(14 downto 0) = Mem_AddrZero(14 downto 0) then
+      if Mem_Addr_i = (14 downto 0 => '0') then
        MemAddrIsZero <= '1';
      else
        MemAddrIsZero <= '0';
@@ -1417,15 +1414,17 @@ begin
    process (Clk)
    begin
      if (Clk'event and Clk = '1') then
-          MemAddrIsZeroPrev <= (MemAddrIsZero);
+        MemAddrIsZeroPrev <= MemAddrIsZero;
      end if;
    end process;

+    ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;
+
    process (Clk)
    begin
      if (Clk'event and Clk = '1') then
-        if (ReadDataZero = '1') then
-          Mem_RdDataZero(7 downto 0) <= (Mem_RdData(7 downto 0));
+        if ReadDataZero = '1' then
+          Mem_RdDataZero <= Mem_RdData;
        end if;
      end if;
    end process;
@@ -1439,8 +1438,6 @@ begin
                "110" when FirstOutput='1' and DataOut_B(6)='1' else
                "111" when FirstOutput='1' and DataOut_B(7)='1' else
                "000";
-
-    ReadDataZero <= MemAddrIsZeroPrev and RunPlayMem;
  end block blk_playmem;

  blk_lowfreq: block