vtuCore: add comments, simplify the HDL.

8a352bca · Tristan Gingold · 31b66a77 · 8a352bca
Commit 8a352bca authored Apr 27, 2020 by Tristan Gingold
Hide whitespace changes
Inline Side-by-side

Showing with 35 additions and 60 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +35 -60

No files found.
--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -528,11 +528,17 @@ entity vtuDataShifter is
           --  Avoid pulses between two words
           );
  port (CoarseZero : out std_logic;
-        DataOut : out std_logic_vector(7 downto 0 );
+
+        --  Data output, provided 1 clock cycle after DataIn.
+        --  The first bit to generate is the MSB.
+        DataOut : out std_logic_vector(7 downto 0);
        OutputEnabled : out std_logic;
        Clk : in std_logic;
        Delay : in std_logic_vector(N - 1 downto 0 );
-        DataIn : in std_logic_vector(7 downto 0 );
+
+        --  Input data.  The first bit is the MSB.
+        DataIn : in std_logic_vector(7 downto 0);
+
        Enabled : in std_logic;
        SyncPulse : out std_logic);
 end vtuDataShifter;
@@ -554,7 +560,6 @@ architecture vtuDataShifter of vtuDataShifter is
  signal Sync_i : std_logic;
  signal OutGood : std_logic;
  signal Disabled : std_logic;
-  signal DataRaw : std_logic_vector(15 downto 0 );
  signal CoarseZero_i : std_logic;
  signal UseNextValue : std_logic;
  signal FineDly : std_logic_vector(2 downto 0 );
@@ -647,14 +652,12 @@ begin
  OutputEnabled_i <= OutMuxSel and (not Disabled);
  OutputEnabled <= OutputEnabled_i;

-  DataRaw(15 downto 8) <= DataClean;
-  DataRaw(7 downto 0) <= (others => '0');
-
-  --  Prepare next data output.
-  ShiftReg_proc: process (DataRaw, FineDly)
+  --  Prepare next data output: delay by FineDly.
+  ShiftReg_proc: process (DataClean, FineDly)
    variable DataOut_aux : std_logic_vector(15 downto 0);
  begin
-    DataOut_aux := std_logic_vector(shift_right(unsigned(DataRaw), to_integer(unsigned(FineDly))));
+    --  Delay by FineDly. Because the first bit is the MSB, do a right shift.
+    DataOut_aux := std_logic_vector(shift_right(unsigned(DataClean & x"00"), to_integer(unsigned(FineDly))));
    if DataOut_aux(7 downto 0) = (7 downto 0 => '0') then
      DataOut_i <= DataOut_aux(15 downto 8);
      --  Need to wait one cycle.
@@ -948,57 +951,29 @@ architecture ModeSelDecoder of ModeSelDecoder is
 begin
  process (Mode)
  begin
-
-    if (Mode = C_Code_ctuAsVtu_control2_mode_singlePulse) then
-      SinglePulseMode <= '1';
-      InfiniteWindowMode <= '0';
-      WindowedOperationMode <= '0';
-      SyncLessOperationMode <= '0';
-      LowFreqGenerationMode <= '0';
-      PlayMemoryMode <= '0';
-    elsif (Mode = C_Code_ctuAsVtu_control2_mode_infiniteWindow) then
-      SinglePulseMode <= '0';
-      InfiniteWindowMode <= '1';
-      WindowedOperationMode <= '0';
-      SyncLessOperationMode <= '0';
-      LowFreqGenerationMode <= '0';
-      PlayMemoryMode <= '0';
-    elsif (Mode = C_Code_ctuAsVtu_control2_mode_windowedOperation) then
-      SinglePulseMode <= '0';
-      InfiniteWindowMode <= '0';
-      WindowedOperationMode <= '1';
-      SyncLessOperationMode <= '0';
-      LowFreqGenerationMode <= '0';
-      PlayMemoryMode <= '0';
-    elsif (Mode = C_Code_ctuAsVtu_control2_mode_syncLessOperation) then
-      SinglePulseMode <= '0';
-      InfiniteWindowMode <= '0';
-      WindowedOperationMode <= '0';
-      SyncLessOperationMode <= '1';
-      LowFreqGenerationMode <= '0';
-      PlayMemoryMode <= '0';
-    elsif (Mode = C_Code_ctuAsVtu_control2_mode_lowFreqGeneration) then
-      SinglePulseMode <= '0';
-      InfiniteWindowMode <= '0';
-      WindowedOperationMode <= '0';
-      SyncLessOperationMode <= '0';
-      LowFreqGenerationMode <= '1';
-      PlayMemoryMode <= '0';
-    elsif (Mode = C_Code_ctuAsVtu_control2_mode_playMemory) then
-      SinglePulseMode <= '0';
-      InfiniteWindowMode <= '0';
-      WindowedOperationMode <= '0';
-      SyncLessOperationMode <= '0';
-      LowFreqGenerationMode <= '0';
-      PlayMemoryMode <= '1';
-    else
-      SinglePulseMode <= '0';
-      InfiniteWindowMode <= '0';
-      WindowedOperationMode <= '0';
-      SyncLessOperationMode <= '0';
-      LowFreqGenerationMode <= '0';
-      PlayMemoryMode <= '0';
-    end if ;
+    SinglePulseMode <= '0';
+    InfiniteWindowMode <= '0';
+    WindowedOperationMode <= '0';
+    SyncLessOperationMode <= '0';
+    LowFreqGenerationMode <= '0';
+    PlayMemoryMode <= '0';
+
+    case Mode is
+      when C_Code_ctuAsVtu_control2_mode_singlePulse =>
+        SinglePulseMode <= '1';
+      when C_Code_ctuAsVtu_control2_mode_infiniteWindow =>
+        InfiniteWindowMode <= '1';
+      when C_Code_ctuAsVtu_control2_mode_windowedOperation =>
+        WindowedOperationMode <= '1';
+      when C_Code_ctuAsVtu_control2_mode_syncLessOperation =>
+        SyncLessOperationMode <= '1';
+      when C_Code_ctuAsVtu_control2_mode_lowFreqGeneration =>
+        LowFreqGenerationMode <= '1';
+      when C_Code_ctuAsVtu_control2_mode_playMemory =>
+        PlayMemoryMode <= '1';
+      when others =>
+        null;
+    end case;
  end process;
 end ModeSelDecoder;