vtu_blk, vtu_diag: remove use of gc_sync_edge.

b470113a · Tristan Gingold · 9907a6aa · b470113a · b470113a
Commit b470113a authored May 04, 2020 by Tristan Gingold
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Showing with 38 additions and 14 deletions

vtu_blk.vhd hdl/rtl/vtu_blk.vhd +16 -8

vtu_diag.vhd hdl/rtl/vtu_diag.vhd +22 -6

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--- a/hdl/rtl/vtu_blk.vhd
+++ b/hdl/rtl/vtu_blk.vhd
@@ -110,6 +110,7 @@ architecture rtl of vtu_blk is
    signal vtu_wrongw           : std_logic;
    signal vtu_wrongw_sys       : std_logic;

+    signal start_sys       : std_logic;
    signal start_pulse_sys : std_logic;
    signal start_pulse_2   : std_logic;
    signal start_ready     : std_logic;
@@ -176,18 +177,25 @@ begin
    --     --> vtu_start (clk_vtu)
    --     --> vtu_start_d (clk_vtu, after loading the config)
    --         [read by the vtu]
-    inst_start_isync: entity work.gc_sync_edge
-        generic map (
-            g_edge => "positive"
-        )
+    inst_start_isync: entity work.gc_sync
        port map (
            clk_i     => clk_sys_i,
            rst_n_a_i => rst_sys_n,
-            data_i    => start_i,
-            synced_o  => open,
-            pulse_o   => start_pulse_sys
+            d_i    => start_i,
+            q_o   => start_sys
        );
-
+    inst_start_edge: entity work.gc_edge_detect
+      generic map (
+        g_async_rst => False,
+        g_pulse_edge => "positive",
+        g_clock_edge => "positive"
+      )
+      port map (
+        clk_i => clk_sys_i,
+        rst_n_i => rst_sys_n,
+        data_i => start_sys,
+        pulse_o => start_pulse_sys
+      );
    --  Synchronizer from the external/soft start to the start for VTU.
    inst_start_psync: entity work.gc_pulse_synchronizer2
        port map (

--- a/hdl/rtl/vtu_diag.vhd
+++ b/hdl/rtl/vtu_diag.vhd
@@ -90,6 +90,7 @@ architecture arch of vtu_diag is
  signal counter    : unsigned(31 downto 0);

  signal sig_pulse : std_logic;
+  signal sig_sync : std_logic;

  signal freq_wr : std_logic;
 begin
@@ -102,6 +103,7 @@ begin
  begin
    if rising_edge(sig_i) then
      if gate_pulse_synced = '1' then
+        --  End of windows, restart counter.
        freq_reg  <= std_logic_vector(cntr_meas);
        cntr_meas <= (others => '0');
      else
@@ -116,7 +118,8 @@ begin
  p_gate_counter : process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if cntr_gate = cntr_last then
+      if rst_n_i = '0' or cntr_gate = cntr_last then
+        --  End of the window, start a new one.
        cntr_gate  <= (others => '0');
        gate_pulse <= '1';
        case windows_i is
@@ -138,7 +141,7 @@ begin
    end if;
  end process;

-  --  Synchronizer for the end-of-window pulse.
+  --  Synchronizer for the end-of-window pulse (from clk_i to sig_i).
  U_Sync_Gate : entity work.gc_pulse_synchronizer2
    port map (
      clk_in_i  => clk_i,
@@ -150,14 +153,27 @@ begin
      d_p_i     => gate_pulse,
      q_p_o     => gate_pulse_synced);

-  inst_sig_sync : entity work.gc_sync_edge
+  inst_sig_sync : entity work.gc_sync
    port map (
      clk_i => clk_i,
      rst_n_a_i => rst_n_i,
-      data_i => sig_i,
-      synced_o => open,
-      pulse_o => sig_pulse);
+      d_i => sig_i,
+      q_o => sig_sync);

+  my_inst: entity work.gc_edge_detect
+    generic map (
+      g_async_rst => False,
+      g_pulse_edge => "positive",
+      g_clock_edge => "positive"
+    )
+    port map (
+      clk_i => clk_i,
+      rst_n_i => rst_n_i,
+      data_i => sig_sync,
+      pulse_o => sig_pulse
+    );
+
+  --  Transfer last frequency measure from sig_i to clk_i
  cmp_gc_sync_word_wr : entity work.gc_sync_word_wr
    generic map (
      g_AUTO_WR => TRUE,