Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
wr2rf-vme
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
wr2rf-vme
Commits
e831a704
Commit
e831a704
authored
Apr 23, 2020
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
vtuCore: refactoring of vtuCore.
parent
5418cc30
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
94 additions
and
89 deletions
+94
-89
vtuCore.vhd
dependencies/vtu/rtl/vtuCore.vhd
+94
-89
No files found.
dependencies/vtu/rtl/vtuCore.vhd
View file @
e831a704
...
...
@@ -1065,83 +1065,33 @@ end vtuCore;
architecture
vtuCore
of
vtuCore
is
signal
PlayMemoryMode
:
std_logic
;
signal
SyncLessOperationMode
:
std_logic
;
signal
WindowedOperationMode
:
std_logic
;
signal
InfiniteWindowMode
:
std_logic
;
signal
LowFreqGenerationMode
:
std_logic
;
signal
SinglePulseMode
:
std_logic
;
signal
FilledMuxSel
:
std_logic
;
signal
DataOut_seq_i
:
std_logic_vector
(
7
downto
0
);
signal
RunSyncLess
:
std_logic
;
signal
wrongValue
:
std_logic
;
signal
SyncLessEna
:
std_logic
;
signal
DataOutLowFreq
:
std_logic_vector
(
7
downto
0
);
signal
DataIn_HT
:
std_logic_vector
(
7
downto
0
);
signal
Shifter2Ena
:
std_logic
;
signal
DataInHTSyncLess
:
std_logic_vector
(
7
downto
0
);
signal
wValueOne_seq
:
std_logic
;
signal
BCoarseZero
:
std_logic
;
signal
SwitchOutput
:
std_logic
;
signal
Run_seq
:
std_logic
;
signal
Run_i
:
std_logic
;
signal
PlayMemoryMode
:
std_logic
;
signal
wrongHT_s
:
std_logic
;
signal
counterEnable
:
std_logic
;
signal
DataOutPlayMem
:
std_logic_vector
(
7
downto
0
);
signal
SwitchtoHT
:
std_logic
;
signal
Shifter1Ena
:
std_logic
;
signal
DataOut_HT
:
std_logic_vector
(
7
downto
0
);
signal
HTSwitchEna
:
std_logic
;
signal
PulseCount
:
std_logic_vector
(
63
downto
0
);
signal
SetStartData
:
std_logic
:
=
'0'
;
signal
wrongW_s
:
std_logic
;
signal
WindowedOperationMode
:
std_logic
;
signal
DataOutPulse
:
std_logic
;
signal
InfiniteWindowMode
:
std_logic
;
signal
DataFilled
:
std_logic_vector
(
7
downto
0
);
signal
HTCoarseZero
:
std_logic
;
signal
wValueZero
:
std_logic
;
signal
SwitchHTeffective
:
std_logic
;
signal
WindowDone_seq
:
std_logic
;
signal
htValue_effective
:
std_logic_vector
(
63
downto
0
);
signal
wrongB_s
:
std_logic
;
signal
wValueOne
:
std_logic
;
signal
DataAllEqual
:
std_logic_vector
(
7
downto
0
);
signal
StartSyncLess
:
std_logic
;
signal
counterReset
:
std_logic
;
signal
SyncLessDisabled
:
std_logic
;
signal
LowFreqGenerationMode
:
std_logic
;
signal
ClkValueSwitch
:
std_logic
;
signal
SinglePulseMode
:
std_logic
;
signal
InfiniteWindow
:
std_logic
;
signal
DataOut_seq
:
std_logic_vector
(
7
downto
0
);
signal
DataOutHTSyncLess
:
std_logic_vector
(
7
downto
0
);
signal
SyncLessOperationMode
:
std_logic
;
signal
Start_i
:
std_logic
;
signal
Mem_RdDataZero
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
Run_seq
:
std_logic
;
signal
PlayingMem_prev
:
std_logic
;
signal
StopPlayMem
:
std_logic
;
signal
SyncPulse_i
:
std_logic
;
signal
FirstOutput
:
std_logic
;
signal
RstOrStopSeq
:
std_logic
;
signal
FirstBit
:
std_logic_vector
(
2
downto
0
);
signal
Mem_Addr_i
:
std_logic_vector
(
14
downto
0
);
signal
OE_SyncLess
:
std_logic
;
signal
RunPlayMem
:
std_logic
;
signal
PlayingMem
:
std_logic
;
signal
Stop_seq
:
std_logic
;
signal
Start_seq
:
std_logic
;
signal
RstOrStopSeq
:
std_logic
;
signal
DataOutLowFreq
:
std_logic_vector
(
7
downto
0
);
signal
DataOutPlayMem
:
std_logic_vector
(
7
downto
0
);
signal
DataOut_seq
:
std_logic_vector
(
7
downto
0
);
signal
DataOutHTSyncLess
:
std_logic_vector
(
7
downto
0
);
signal
DataOut_B
:
std_logic_vector
(
7
downto
0
);
signal
SetPlayingMem
:
std_logic
;
signal
PlayingMem_i
:
std_logic
;
signal
MemAddrIsZero
:
std_logic
;
signal
FirstSyncArrived
:
std_logic
:
=
'0'
;
signal
Mem_AddrZero
:
std_logic_vector
(
14
downto
0
);
signal
Mem_RdData_prev
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
OE_SyncLess
:
std_logic
;
signal
OE_B
:
std_logic
;
signal
OE_HT
:
std_logic
;
signal
MemAddrIsZeroPrev
:
std_logic
;
signal
StartPlayMem
:
std_logic
;
signal
RunPlayAndSyncPulse
:
std_logic
;
signal
RunPlayMem_i
:
std_logic
;
signal
ReadDataZero
:
std_logic
;
begin
B_ModeSelDecoder
:
entity
work
.
ModeSelDecoder
port
map
(
Mode
=>
Mode
(
2
downto
0
),
...
...
@@ -1152,6 +1102,35 @@ begin
LowFreqGenerationMode
=>
LowFreqGenerationMode
,
PlayMemoryMode
=>
PlayMemoryMode
);
-- Select start input.
Start_i
<=
Start
when
UseSyncAsStart
=
'0'
else
SyncPulse_i
;
blk_seq
:
block
is
signal
wrongHT_s
:
std_logic
;
signal
wrongW_s
:
std_logic
;
signal
wrongB_s
:
std_logic
;
signal
BCoarseZero
:
std_logic
;
signal
HTCoarseZero
:
std_logic
;
signal
wValueZero
:
std_logic
;
signal
wValueOne
:
std_logic
;
signal
WindowDone_seq
:
std_logic
;
signal
Shifter1Ena
:
std_logic
;
signal
Shifter2Ena
:
std_logic
;
signal
Stop_seq
:
std_logic
;
signal
Start_seq
:
std_logic
;
signal
DataOut_seq_i
:
std_logic_vector
(
7
downto
0
);
signal
wrongValue
:
std_logic
;
signal
DataIn_HT
:
std_logic_vector
(
7
downto
0
);
signal
wValueOne_seq
:
std_logic
;
signal
SwitchOutput
:
std_logic
;
signal
counterEnable
:
std_logic
;
signal
SwitchtoHT
:
std_logic
;
signal
DataOut_HT
:
std_logic_vector
(
7
downto
0
);
signal
PulseCount
:
std_logic_vector
(
63
downto
0
);
signal
counterReset
:
std_logic
;
signal
InfiniteWindow
:
std_logic
;
begin
B_WrongValuesLogic
:
entity
work
.
WrongValuesLogic
port
map
(
wrongB
=>
wrongB_s
,
wrongHT
=>
wrongHT_s
,
...
...
@@ -1164,16 +1143,12 @@ begin
Clk
=>
Clk
,
Rst
=>
Rst
);
wrongValue
<=
wrongB_s
or
wrongHT_s
or
wrongW_s
;
wrongB
<=
wrongB_s
;
wrongHT
<=
wrongHT_s
;
wrongW
<=
wrongW_s
;
blk_seq
:
block
begin
-- Data shifter using B parameters: from Sync pulse to the first pulse.
B_DataShifterB
:
entity
work
.
vtuDataShifter
generic
map
(
N
=>
64
,
...
...
@@ -1216,19 +1191,14 @@ begin
CounterRst
=>
counterReset
,
Run
=>
Run_seq
);
-- Select start input.
Start_i
<=
Start
when
UseSyncAsStart
=
'0'
else
SyncPulse_i
;
-- Start sequencer on start signal if sequencer mode selected.
Start_seq
<=
Start_i
when
(
SyncLessOperationMode
or
PlayMemoryMode
)
=
'0'
else
'0'
;
wrongValue
<=
wrongB_s
or
wrongHT_s
or
wrongW_s
;
-- Stop sequencer on stop signal or if values aren't correct.
Stop_seq
<=
Stop
or
wrongValue
;
-- True if running.
Run_i
<=
Run_seq
or
RunSyncLess
or
PlayingMem
;
Run
<=
Run_i
;
SwitchOutput
<=
SwitchtoHT
or
(
not
Run_seq
);
process
(
DataOut_B
,
DataOut_HT
,
SwitchOutput
)
...
...
@@ -1292,6 +1262,12 @@ begin
end
block
blk_seq
;
blk_syncless
:
block
is
signal
DataInHTSyncLess
:
std_logic_vector
(
7
downto
0
);
signal
SyncLessEna
:
std_logic
;
signal
SetStartData
:
std_logic
:
=
'0'
;
signal
StartSyncLess
:
std_logic
;
signal
SyncLessDisabled
:
std_logic
;
begin
B_DataShifterHT_SyncLess
:
entity
work
.
vtuDataShifter
generic
map
(
N
=>
64
,
...
...
@@ -1340,6 +1316,25 @@ begin
end
block
blk_syncless
;
blk_playmem
:
block
is
signal
Mem_AddrZero
:
std_logic_vector
(
14
downto
0
);
signal
Mem_RdData_prev
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
FirstBit
:
std_logic_vector
(
2
downto
0
);
signal
MemAddrIsZeroPrev
:
std_logic
;
signal
StartPlayMem
:
std_logic
;
signal
RunPlayAndSyncPulse
:
std_logic
;
signal
RunPlayMem_i
:
std_logic
;
signal
SetPlayingMem
:
std_logic
;
signal
PlayingMem_i
:
std_logic
;
signal
MemAddrIsZero
:
std_logic
;
signal
PlayingMem_prev
:
std_logic
;
signal
StopPlayMem
:
std_logic
;
signal
Mem_RdDataZero
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
Mem_Addr_i
:
std_logic_vector
(
14
downto
0
);
signal
FirstOutput
:
std_logic
;
signal
RunPlayMem
:
std_logic
;
signal
FirstSyncArrived
:
std_logic
:
=
'0'
;
signal
ReadDataZero
:
std_logic
;
begin
B_PlayMemRunningFF
:
entity
work
.
RSFF
port
map
(
Clk
=>
Clk
,
...
...
@@ -1449,6 +1444,12 @@ begin
end
block
blk_playmem
;
blk_lowfreq
:
block
is
signal
FilledMuxSel
:
std_logic
;
signal
DataOutPulse
:
std_logic
;
signal
DataFilled
:
std_logic_vector
(
7
downto
0
);
signal
DataAllEqual
:
std_logic_vector
(
7
downto
0
);
signal
ClkValueSwitch
:
std_logic
;
begin
process
(
Clk
,
RstOrStopSeq
)
begin
...
...
@@ -1554,6 +1555,10 @@ begin
-- Pulse detected.
SyncPulse
<=
SyncPulse_i
;
-- True if running.
Run_i
<=
Run_seq
or
RunSyncLess
or
PlayingMem
;
Run
<=
Run_i
;
process
(
htValue
,
SwitchHTeffective
)
begin
case
SwitchHTeffective
is
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment